Datasheet OP191 Datasheet (ANALOG DEVICES)

Micropower Single-Supply

–

+

O

FEATURES

Single-supply operation: 2.7 V to 12 V Wide input voltage range Rail-to-rail output swing Low supply current: 300 μA/amp Wide bandwidth: 3 MHz Slew rate: 0.5 V/μs Low offset voltage: 700 μV No phase reversal

APPLICATIONS

Industrial process control Battery-powered instrumentation Power supply control and protection Telecommunications Remote sensors Low voltage strain gage amplifiers DAC output amplifiers

Rail-to-Rail Input/Output Op Amps

OP191/OP291/OP491

PIN CONFIGURATIONS

OUTA

–INA

+INA

1

2

OP291

3

4

–V

NC

1

INA

2

INA

OP191

3

–V

4

NC = NO CONNECT

8

7

6

5

NC

+V

OUTA

NC

00294-001

Figure 1. 8-Lead Narrow-Body SOIC Figure 2. 8-Lead Narrow-Body SOIC

OUTA

–INA

+INA

+INB

–INB

OUTB

1

2

3

+V

4

OP491

5

6

7

14

OUTD

–IND

13

+IND

12

–V

11

+INC

10

–INC

9

8

OUTC

00294-003

OUTA

–INA

+INA

+INB

–INB

UTB

1

2

+-+

3

+V

4

OP491

5

+-+

6

7

Figure 3. 14-Lead Narrow-Body SOIC Figure 4. 14-Lead PDIP

OUTA

–INA

+INA

+V

+INB

–INB

OUTB

1

2

3

4

5

6

7

OP491

14

OUTD

13

–IND

12

+IND

11

–V

+INC

10

9

–INC

8

OUTC

00294-005

Figure 5. 14-Lead TSSOP

+V

8

OUTB

7

–INB

6

5

+INB

0294-002

14

OUTD

13

–IND

-

+IND

12

–V

11

+INC

10

-

–INC

9

8

OUTC

00294-004

GENERAL DESCRIPTION

The OP191, OP291, and OP491 are single, dual, and quad micropower, single-supply, 3 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. All are guaranteed to operate from a +3 V single supply as well as ±5 V dual supplies.

Fabricated on Analog Devices CBCMOS process, the OPx91 family has a unique input stage that allows the input voltage to safely extend 10 V beyond either supply without any phase inversion or latch-up. The output voltage swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies.

Applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo electric, and resistive transducers.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios.

The OP191/OP291/OP491 are specified over the extended industrial –40°C to +125°C temperature range. The OP191 single and OP291 dual amplifiers are available in 8-lead plastic SOIC surface-mount packages. The OP491 quad is available in a 14-lead PDIP, a narrow 14-lead SOIC package, and a 14-lead TSSOP.

OP191/OP291/OP491

REVISION HISTORY

4/10—Rev. D to Rev. E

Changes to Input Voltage Parameter, Table 4 ............................... 7

Applications Information .............................................................. 19

Single 3 V Supply, Instrumentation Amplifier ....................... 19

Single-Supply RTD Amplifier ................................................... 19

A 2.5 V Reference from a 3 V Supply ...................................... 20

5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 20

A High-Side Current Monitor .................................................. 20

A 3 V, Cold Junction Compensated Thermocouple Amplifier

....................................................................................................... 21

Single-Supply, Direct Access Arrangement for Modems ...... 21

3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 22

Single-Supply, Half-Wave, and Full-Wave Rectifiers ............. 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

3/04—Rev. B to Rev. C.

Changes to OP291 SOIC Pin Configuration ................................. 1



4/06—Rev. C to Rev. D

Changes to Noise Performance, Voltage Density, Table 1 ........... 3

Changes to Noise Performance, Voltage Density, Table 2 ........... 4

Changes to Noise Performance, Voltage Density, Table 3 ........... 5

Changes to Figure 23 and Figure 24 ............................................. 10

Changes to Figure 42 ...................................................................... 13

Changes to Figure 43 ...................................................................... 14

Changes to Figure 57 ...................................................................... 16

Added Figure 58 .............................................................................. 16

Changed Reference from Figure 47 to Figure 12 ........................ 17

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 24

11/03—Rev. A to Rev. B.

Edits to General Description ........................................................... 1

Edits to Pin Configuration ............................................................... 1

Changes to Ordering Guide ............................................................. 5

Updated Outline Dimensions ....................................................... 19

12/02—Rev. 0 to Rev. A.

Edits to General Description ........................................................... 1

Edits to Pin Configuration ............................................................... 1

Changes to Ordering Guide ............................................................. 5

Edits to Dice Characteristics ............................................................ 5

Rev. E | Page 2 of 24

OP191/OP291/OP491

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

@ VS = 3.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage

OP191G VOS 80 500 μV

−40°C ≤ TA ≤ +125°C 1 mV OP291G/OP491G VOS 80 700 μV

−40°C ≤ TA ≤ +125°C 1.25 mV

Input Bias Current IB 30 65 nA

−40°C ≤ TA ≤ +125°C 95 nA

Input Offset Current IOS 0.1 11 nA

−40°C ≤ TA ≤ +125°C 22 nA

Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.9 V 70 90 dB

−40°C ≤ TA ≤ +125°C 65 87 dB

Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.3 V to 2.7 V 25 70 V/mV

−40°C ≤ TA ≤ +125°C 50 V/mV

Offset Voltage Drift ∆VOS/∆T 1.1 μV/°C Bias Current Drift ∆IB/∆T 100 pA/°C Offset Current Drift ∆IOS/∆T 20 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 100 kΩ to GND 2.95 2.99 V

−40°C to +125°C 2.90 2.98 V

R

−40°C to +125°C 2.70 2.80 V

Output Voltage Low VOL RL = 100 kΩ to V+ 4.5 10 mV

−40°C to +125°C 35 mV

R

−40°C to +125°C 130 mV

Short-Circuit Limit ISC Sink/source ±8.75 ±13.50 mA

−40°C to +125°C ±6.0 ±10.5 mA

Open-Loop Impedance Z

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB

−40°C ≤ TA ≤ +125°C 75 110 dB

Supply Current/Amplifier ISY VO = 0 V 200 350 μA

−40°C ≤ TA ≤ +125°C 330 480 μA

DYNAMIC PERFORMANCE

Slew Rate +SR RL = 10 kΩ 0.4 V/μs Slew Rate –SR RL = 10 kΩ 0.4 V/μs Full-Power Bandwidth BWP 1% distortion 1.2 kHz Settling Time tS To 0.01% 22 μs Gain Bandwidth Product GBP 3 MHz Phase Margin θO 45 Degrees Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 μV p-p Voltage Noise Density en f = 1 kHz 30 nV/√Hz Current Noise Density in 0.8 pA/√Hz

f = 1 MHz, AV = 1 200 Ω

OUT

= 2 kΩ to GND 2.8 2.9 V

L

= 2 kΩ to V+ 40 75 mV

L

Rev. E | Page 3 of 24

OP191/OP291/OP491

@ VS = 5.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25°C, unless otherwise noted. +5 V specifications are guaranteed by +3 V and ±5 V testing.

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage

OP191 VOS 80 500 μV

−40°C ≤ TA ≤ +125°C 1.0 mV OP291/OP491 VOS 80 700 μV

−40°C ≤ TA ≤ +125°C 1.25 mV

Input Bias Current IB 30 65 nA

−40°C ≤ TA ≤ +125°C 95 nA

Input Offset Current IOS 0.1 11 nA

−40°C ≤ TA ≤ +125°C 22 nA

Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR VCM = 0 V to 4.9 V 70 93 dB –40°C ≤ TA ≤ +125°C 65 90 dB Large Signal Voltage Gain AVO RL = 10 kΩ, VO = 0.3 V to 4.7 V 25 70 V/mV

−40°C ≤ TA ≤ +125°C 50 V/mV

Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 1.1 μV/°C Bias Current Drift ∆IB/∆T 100 pA/°C Offset Current Drift ∆IOS/∆T 20 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage High VOH RL = 100 kΩ to GND 4.95 4.99 V

−40°C to +125°C 4.90 4.98 V

R

−40°C to +125°C 4.65 4.75 V

Output Voltage Low VOL RL = 100 kΩ to V+ 4.5 10 mV

−40°C to +125°C 35 mV

R

−40°C to +125°C 155 mV

Short-Circuit Limit ISC Sink/source ±8.75 ±13.5 mA

−40°C to +125°C ±6.0 ±10.5 mA

Open-Loop Impedance Z

f = 1 MHz, AV = 1 200 Ω

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB

−40°C ≤ TA ≤ +125°C 75 110 dB

Supply Current/Amplifier ISY VO = 0 V 220 400 μA

−40°C ≤ TA ≤ +125°C 350 500 μA

DYNAMIC PERFORMANCE

Slew Rate +SR RL = 10 kΩ 0.4 V/μs Slew Rate –SR RL = 10 kΩ 0.4 V/μs Full-Power Bandwidth BWP 1% distortion 1.2 kHz Settling Time tS To 0.01% 22 μs Gain Bandwidth Product GBP 3 MHz Phase Margin θO 45 Degrees Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 μV p-p Voltage Noise Density en f = 1 kHz 42 nV/√Hz Current Noise Density in 0.8 pA/√Hz

= 2 kΩ to GND 4.8 4.85 V

L

= 2 kΩ to V+ 40 75 mV

L

Rev. E | Page 4 of 24

OP191/OP291/OP491

@ VO = ±5.0 V, –4.9 V ≤ VCM ≤ +4.9 V, TA = +25°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage OP191 VOS 80 500 μV

−40°C ≤ TA ≤ +125°C 1 mV OP291/OP491 VOS 80 700 μV

−40°C ≤ TA ≤ +125°C 1.25 mV Input Bias Current IB 30 65 nA

−40°C ≤ TA ≤ +125°C 95 nA

Input Offset Current IOS 0.1 11 nA

−40°C ≤ TA ≤ +125°C 22 nA Input Voltage Range −5 +5 V Common-Mode Rejection Ratio CMRR VCM = ±5 V 75 100 dB

−40°C ≤ TA ≤ +125°C 67 97 dB Large Signal Voltage Gain AVO RL = +10 kΩ, VO = ±4.7 V 25 70

−40°C ≤ TA ≤ +125°C 50 V/mV Offset Voltage Drift ∆VOS/∆T 1.1 μV/°C Bias Current Drift ∆IB/∆T 100 pA/°C Offset Current Drift ∆IOS/∆T 20 pA/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing VO RL = 100 kΩ to GND ±4.93 ±4.99 V

−40°C to +125°C ±4.90 ±4.98 V R –40°C ≤ TA ≤ +125°C ±4.65 ±4.75 V Short-Circuit Limit ISC Sink/source ±8.75 ±16.00 mA

−40°C to +125°C ±6 ±13 mA Open-Loop Impedance Z

f = 1 MHz, AV = 1 200 Ω

OUT

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±5 V 80 110 dB

−40°C ≤ TA ≤ +125°C 75 100 dB Supply Current/Amplifier ISY VO = 0 V 260 420 μA

−40°C ≤ TA ≤ +125°C 390 550 μA

DYNAMIC PERFORMANCE

Slew Rate ±SR RL = 10 kΩ 0.5 V/μs Full-Power Bandwidth BWP 1% distortion 1.2 kHz Settling Time tS To 0.01% 22 μs Gain Bandwidth Product GBP 3 MHz Phase Margin θO 45 Degrees Channel Separation CS f = 1 kHz 145 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 μV p-p Voltage Noise Density en f = 1 kHz 42 nV/√Hz Current Noise Density in 0.8 pA/√Hz

= 2 kΩ to GND ±4.80 ±4.95 V

L

Rev. E | Page 5 of 24

OP191/OP291/OP491

INPUT

OUTPUT

5V

100

90

10

0%

5V

V

R A V

=±5V

s

=2k

L

V

IN

200s

=+1 =20Vp-p

00294-006

Figure 6. Input and Output with Inputs Overdriven by 5 V

Rev. E | Page 6 of 24

OP191/OP291/OP491

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 16 V Input Voltage GND to (VS + 10 V) Differential Input Voltage 7 V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range

N, R, RU Packages −65°C to +150°C

Operating Temperature Range

OP191G/OP291G/OP491G −40°C to +125°C

Junction Temperature Range

N, R, RU Packages −65°C to +150°C

Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions; that is, θJA is specified for device in socket for PDIP packages; θ for device soldered in circuit board for TSSOP and SOIC packages.

Table 5. Thermal Resistance

Package Type θJA θJC Unit

8-Lead SOIC (R) 158 43 °C/W 14-Lead PDIP (N) 76 33 °C/W 14-Lead SOIC (R) 120 36 °C/W 14-Lead TSSOP (RU) 180 35 °C/W

is specified

JA

ESD CAUTION

Rev. E | Page 7 of 24

OP191/OP291/OP491

TYPICAL PERFORMANCE CHARACTERISTICS

180

VS = 3V T

= 25°C

A

160

BASED ON 1200 OP AMPS

140

120

100

UNITS

80

60

40

20

= 0V

0.22

12525–40

00294-012

00294-013

7

00294-014

0 –0.18

INPUT OFFSET VOLTAGE (mV)

0.140.06–0.02–0.10

Figure 7. OP291 Input Offset Voltage Distribution, VS = 3 V

120

VS = 3V

100

80

60

UNITS

40

20

0

1

0

INPUT OFFSET VOLTAGE (µV/°C)

–40°C < T BASED ON 600 OP AMPS

< +125°C

A

5

6432

Figure 8. OP291 Input Offset Voltage Drift Distribution, VS = 3 V

0

VS = 3V

–0.02

–0.04

–0.06

–0.08

–0.10

INPUT OFFSET VOLTAGE (mV)

–0.12

–0.14

TEMPERATURE ( °C)

= 0.1V

V

CM

V

CM

= 3V

V

CM

VCM = 2.9V

85

Figure 9. Input Offset Voltage vs. Temperature, VS = 3 V

40

30

20

10

0

= 3V

V

S

–10

–20

–30

INPUT BIAS CURRENT (nA)

–40

–50

–60

–40

TEMPERATURE (° C)

VCM = 3V

= 2.9V

V

CM

V

= 0.1V

CM

V

= 0V

CM

00294-015

12525 85

Figure 10. Input Bias Current vs. Temperature, VS = 3 V

0

–0.2

–0.4

VS = 3V

–0.6

–0.8

–1.0

–1.2

–1.4

INPUT OFFSET CURRENT ( nA)

–1.6

–1.8

–40

TEMPERATURE (° C)

= 0.1V

V

CM

= 2.9V

V

CM

= 3V

V

CM

= 0V

V

CM

85

00294-016

12525

Figure 11. Input Offset Current vs. Temperature, VS = 3 V

36

VS = 3V

30

24

18

12

6

0

–6

–12

–18

INPUT BIAS CURRENT (n A)

–24

–30

–36

0.3

0

INPUT COMMON-MODE VOL TAGE (V)

00294-017

3.0

2.72.42.11.81. 51.20.90. 6

Figure 12. Input Bias Current vs. Input Common-Mode Voltage, VS = 3 V

Rev. E | Page 8 of 24

OP191/OP291/OP491

3.00

2.95

2.90

+VO @ RL = 2k

2.85

OUTPUT VOLTAGE SWING (V)

2.80

VS = 3V

2.75 –40

25

TEMPERATURE ( °C)

+VO @ RL = 100k

85

Figure 13. Output Voltage Swing vs. Temperature, VS = 3 V

160

140

120

100

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

–40

100

1k

FREQUENCY (Hz)

V

S

T

A

Figure 14. Open-Loop Gain and Phase vs. Frequency, VS = 3 V

1200

RL = 100k, V

= 2.9V

1000

800

CM

R

= 100k,

L

V

CM

= 0.1V

=3V = 25°C

00294-018

125

90

45

OPEN PHASE SHIFT (Degrees)

0

–45

–90

10M1M100k10k

00294-019

50

40

30

20

10

0

–10

–20

CLOSED-LOOP GAIN (dB)

–30

–40

–50

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 16. Closed-Loop Gain vs. Frequency, VS = 3 V

160

140

120

100

80

60

CMRR (dB)

40

20

0

–20

–40

100 1k 10M1M100k10k

FREQUENCY (Hz)

Figure 17. CMRR vs. Frequency, VS = 3 V

90

VS = 3V

89

88

VS = 3V T

= 25°C

A

CMRR V

= 3V

S

T

= 25°C

A

00294-021

00294-022

600

400

OPEN-LOOP GAIN (V/mV)

200

0

TEMPERATURE ( °C)

VS = 3V, VO = 0.3V/2.7V

85

Figure 15. Open-Loop Gain vs. Temperature, VS = 3 V

00294-020

12525–40

Rev. E | Page 9 of 24

87

CMRR (dB)

86

85

84

–40

25

TEMPERATURE (° C)

85

125

00294-023

Figure 18. CMRR vs. Temperature, VS = 3 V

OP191/OP291/OP491

160

140

120

100

80

60

PSRR (dB)

40

20

0

–20

–40

100 1k 10M1M100k10k

Figure 19. PSRR vs. Frequency, VS = 3 V

113

112

111

–PSRR

FREQUENCY (Hz)

+PSRR

±PSRR V

= 3V

S

= 25°C

T

A

VS = 3V

0.35

VS = 3V

0.30

0.25

0.20

0.15

0.10

SUPPLY CURRENT/AM PLIFI ER (mA)

00294-024

0.05 –40

25

TEMPERATURE (° C)

85

125

00294-027

Figure 22. Supply Current vs. Temperature, VS = +3 V, +5 V, ±5 V

3.0

2.5

2.0

VIN = 2.8V p-p

= 3V

V

S

A

= +1

V

= 100k

R

L

110

PSRR (dB)

109

108

107

–40

25

TEMPERATURE (° C)

Figure 20. PSRR vs. Temperature, VS = 3 V

1.6

VS = 3V

1.4

1.2

1.0

0.8

0.6

SLEW RATE (V/µ s)

0.4

0.2

0

25–40

TEMPERATURE (° C)

Figure 21. Slew Rate vs. Temperature, VS = 3 V

+SR

–SR

1.5

1.0

MAXIMUM OUTPUT SWING (V)

0.5

85

125

00294-025

0

100 1k 10k 100k

FREQUENCY (Hz)

1M

00294-028

Figure 23. Maximum Output Swing vs. Frequency, VS = 3 V

1k

100

VOLTAGE NOISE DENSITY (nV/ Hz)

00294-026

85

125

10

10 100 1k 10k

FREQUENCY (Hz)

00294-029

Figure 24. Voltage Noise Density, VS = 5 V or ±5 V

Rev. E | Page 10 of 24

OP191/OP291/OP491

70

VS = 5V T

= 25°C

A

60

BASED ON 600 OP AMPS

50

40

UNITS

30

20

10

0 –0.50

0.300. 10–0.10–0.30

0.50

INPUT OFFSET VOLTAGE (mV)

Figure 25. OP291 Input Offset Voltage Distribution, VS = 5 V

120

V

= 5V

S

100

–40°C < T BASED ON 600 OP AMPS

< +125°C

A

80

60

UNITS

40

20

0

1

0

5

6432

INPUT OFFSET VOLTAGE (µV/°C)

Figure 26. OP291 Input Offset Voltage Drift Distribution, VS = 5 V

(mV)

OS

V

0.15

0.10

0.05

–0.05

–0.10

V

= 0V

CM

0

V

= 5V

CM

–40

25

85

TEMPERATURE (° C)

VS = 5V

Figure 27. Input Offset Voltage vs. Temperature, VS = 5 V

125

00294-030

00294-031

7

00294-032

40

VS = 5V

30

V

= 5V

20

CM

+I

B

–I

B

10

0

(nA)

B

I

–10

–20

–30

–40

= 0V

V

CM

–I

B

+I

B

12525 85

TEMPERATURE (° C)

Figure 28. Input Bias Current vs. Temperature, VS = 5 V

1.6

1.4

1.2

1.0

0.8

=0V

V

CM

0.6

0.4

0.2

INPUT OFFSET CURRENT ( nA)

–0.2

0

–40

=5V

V

CM

85

TEMPERATURE (°C)

VS=5V

12525

Figure 29. Input Offset Current vs. Temperature, VS = 5 V

36

VS = 5V

30

24

18

12

6

0

–6

–12

–18

INPUT BIAS CURRENT (n A)

–24

–30

–36

0

4321

5

COMMON-MO DE INPUT VOL TAGE (V)

Figure 30. Input Bias Current vs. Common-Mode Input Voltage, VS = 5 V

00294-033

00294-034

00294-035

Rev. E | Page 11 of 24

OP191/OP291/OP491

5.00

4.95

4.90

4.85

= 2k

R

L

4.80

OUTPUT VOLTAGE SWING (V)

4.75

= 5V

V

S

4.70 –40

25

TEMPERATURE (° C)

Figure 31. Output Voltage Swing vs. Temperature, VS = 5 V

160

140

120

100

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

–40

100

1k

FREQUENCY (Hz)

Figure 32. Open-Loop Gain and Phase vs. Frequency, VS = 5 V

140

= 100k, VCM = 5V

R

120

100

OPEN-LOOP GAIN (V/mV)

L

80

60

40

20

0

–40

RL = 2k, VCM = 5V

R

= 2k, VCM = 0V

L

R

= 100k, VCM = 0V

L

25

TEMPERATURE (° C)

Figure 33. Open-Loop Gain vs. Temperature, VS = 5 V

85

RL = 100k

VS=5V T

= 25°C

A

10M1M100k10k

VS = 5V

125

90

45

0

–45

–90

125

00294-036

OPEN PHASE SHIFT (Degrees)

00294-038

00294-037

50

40

30

20

10

0

–10

–20

CLOSED-LOOP GAIN (dB)

–30

–40

–50

10 100 1k

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 34. Closed-Loop Gain vs. Frequency, VS = 5 V

160

140

120

100

80

60

CMRR (dB)

40

20

0

–20

–40

100 1k 10M1M100k10k

FREQUENCY ( Hz)

Figure 35. CMRR vs. Frequency, VS = 5V

96

VS = 5V

95

94

93

92

91

CMRR (dB)

90

89

88

87

86

–40

25

TEMPERATURE (° C)

Figure 36. CMRR vs. Temperature, VS = 5 V

V

= 5V

S

= 25°C

T

A

CMRR V

=5V

S

T

=25°C

A

85 125

00294-039

00294-040

00294-041

Rev. E | Page 12 of 24

OP191/OP291/OP491

160

140

120

100

80

60

PSRR (dB)

40

20

0

–20

–40

100 1k 10M1M100k10k

FREQUENCY (Hz)

+PSRR

–PSRR

Figure 37. PSRR vs. Frequency, VS = 5 V

0.6

0.5

0.4

0.3

SR (V/µs)

0.2

0.1

0

–40

+SR –S R

25

TEMPERATURE (°C)

85

Figure 38. OP291 Slew Rate vs. Temperature, VS = 5 V

0.50 = 5V

V

S

0.45

0.40

0.35

0.30

0.25

SR (V/µs)

0.20

0.15

0.10

0.05

0

–40

+SR

–SR

25

TEMPERATURE (° C)

85

Figure 39. OP491 Slew Rate vs. Temperature, VS = 5 V

±PSRR V

= 5V

S

T

= 25°C

A

00294-042

V

=5V

S

00294-043

125

00294-044

125

20

18

16

14

+I

12

10

SHORT-CIRCUIT CURRENT (mA)

, VS = +3V

SC

8

6

4

25–40

TEMPERATURE ( °C)

–I

SC

+I

, VS = ±5V

SC

–ISC, VS = +3V

85

125

Figure 40. Short-Circuit Current vs. Temperature, VS = +3 V, +5 V, ±5 V

80

70

60

50

40

30

VOLTAGE (V)

20

10

0

A

V

= 10V p-p @ 1kHz

IN

10k

FREQUENCY (Hz)

10k

VS = ±5V

1k

V

B

200015001000500

O

2500

Figure 41. Channel Separation, VS = ±5 V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

MAXIMUM OUTPUT SWING (V)

1.0

0.5

0

FREQUENCY (Hz)

VIN = 4.8V p-p V

= 5V

S

A

= +1

V

R

= 100k

L

1M100 1k 10k 100k

Figure 42. Maximum Output Swing vs. Frequency, VS = 5 V

00294-045

00294-046

00294-047

Rev. E | Page 13 of 24

OP191/OP291/OP491

10

8

6

4

MAXIMUM OUTPUT SWING (V)

2

0

FREQUENCY (Hz)

Figure 43. Maximum Output Swing vs. Frequency, VS = ±5 V

0.15

0.10

= –5V

V

CM

0.05

0

=+5V

V

INPUT OFFSET VOLTAGE (mV)

–0.05

CM

VIN = 9.8V p-p V

= ±5V

S

A

= +1

V

R

= 100k

L

VS=±5V

1.6 VS=±5V

1.4

1.2

1.0

V

= –5V

CM

0.8

0.6

0.4

0.2

INPUT OFF SET CURRENT (n A)

V

=+5V

CM

0

00294-048

1M100 1k 10k 100k

–0.2

–40

85

00294-051

12525

TEMPERATURE (°C)

Figure 46. Input Offset Current vs. Temperature, VS = ±5 V

36

VS = ±5V

24

12

0

–12

INPUT BIAS CURRENT (n A)

–24

–0.10

–40

25

85

TEMPERATURE (°C)

Figure 44. Input Offset Voltage vs. Temperature, VS = ±5 V

50

VS = ±5V

40

30

20

= +5V

V

CM

+I

10

0

(nA)

B

I

–10

–20

–30

= –5V

V

CM

–40

–50

–40

TEMPERATURE (° C)

Figure 45. Input Bias Current vs. Temperature, VS = ±5 V

125

00294-049

–36

–5

00294-052

5–4

43210–1–2–3

COMMON-MODE INPUT VOLTAGE (V)

Figure 47. Input Bias Current vs. Common-Mode Voltage, VS = ±5 V

5.00

R

= 2k

B

–I

B

4.95

4.90

4.85

4.80

4.75

V

= ±5V

S

0

L

RL= 2k

–4.75

–4.80

–I

B

+I

B

00294-050

12525 85

OUTPUT VOLT AGE SWING (V)

–4.85

–4.90

–4.95

–5.00

–40

R

= 2k

L

R

= 2k

L

25

85

00294-053

125

TEMPERATURE (° C)

Figure 48. Output Voltage Swing vs. Temperature, VS = ±5 V

Rev. E | Page 14 of 24

OP191/OP291/OP491

70

60

50

40

30

20

10

0

OPEN-LOOP GAIN (dB)

–10

–20

–30

1k 10M1M100k10k

FREQUENCY (Hz)

VS = ±5V T

= 25°C

A

Figure 49. Open-Loop Gain and Phase vs. Frequency, VS = ±5 V

200

180

160

140

120

100

80

65

OPEN-LOOP GAIN (V/mV)

40

25

0

–40

= 2k

R

L

R

= 2k

L

25

TEMPERATURE ( °C)

85

Figure 50. Open-Loop Gain vs. Temperature, VS = ±5 V

50

40

30

20

10

0

–10

–20

CLOSED-LOOP GAIN (dB)

–30

–40

–50

10 100 1k

10k 100k 1M 10M

FREQUENCY (Hz)

V T

Figure 51. Closed-Loop Gain vs. Frequency, VS = ±5 V

VS = ±5V

= ±5V

S

= 25°C

A

0

45

90

135

180

225

270

125

PHASE SHIFT (Degrees)

00294-054

00294-055

00294-056

160

140

120

100

80

60

CMRR (dB)

40

20

0

–20

–40

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 52. CMRR vs. Frequency, VS = ±5 V

102

VS = ±5V

101

100

99

98

97

CMRR (dB)

96

95

94

93

92

–40

25

TEMPERATURE (° C)

85

Figure 53. CMRR vs. Temperature, VS =± 5 V

160

140

120

100

80

60

PSRR (dB)

40

20

0

–20

–40

100 1k 10k 100k 1M 10M

–PSRR

FREQUENCY (Hz)

+PSRR

Figure 54. PSRR vs. Frequency, VS = ±5 V

CMRR V

= ±5V

S

T

= 25°C

A

±PSRR V

= ±5V

S

T

= 25°C

A

00294-057

00294-058

125

00294-059

Rev. E | Page 15 of 24

OP191/OP291/OP491

O

115

= ±5V

V

S

110

OP291

105

PSRR (dB)

100

1k

OP491

100

95

90

–40

25

85

TEMPERATURE (° C)

Figure 55. OP291/OP491 PSRR vs. Temperature, VS = ±5 V

0.7 V

=±5V

S

0.6

+SR

0.5

0.4

0.3

SR (V/µs)

–SR

0.2

0.1

0

TEMPERATURE (°C)

Figure 56. Slew Rate vs. Temperature, VS = ±5 V

1k

VS = 3V

100

AV = +100

125

12525–40 85

VOLTAGE NOISE DENSI TY (nV/ Hz)

00294-060

10

10 100 1k 10k

FREQUENCY (Hz)

Figure 58. Voltage Noise Density, V

= 3 V

S

00294-078

1.00V

100

90

INPUT

OUTPUT

00294-061

10

0%

2.00µs

VS=3V R

= 200k 

L

100mV500mV

00294-063

Figure 59. Large Signal Transient Response, VS = 3 V

2.00V

100

90

AV = +10

10

OUTPUT IMPEDANCE ()

1

0.1

1k 10k 100k 1M 2M

AV = +1

FREQUENCY (Hz)

Figure 57. Output Impedance vs. Frequency

00294-062

INPUT

UTPUT

V

=±5V

S

= 200k 

R

2.00µs

A

L

=+1V/V

V

100mV1.00V

10

0%

Figure 60. Large Signal Transient Response, VS = ±5 V

0294-064

Rev. E | Page 16 of 24

OP191/OP291/OP491

THEORY OF OPERATION

The OP191/OP291/OP491 are single-supply, micropower amplifiers featuring rail-to-rail inputs and outputs. To achieve wide input and output ranges, these amplifiers employ unique input and output stages. In Figure 61 , the input stage comprises two differential pairs, a PNP pair and an NPN pair. These two stages do not work in parallel. Instead, only one stage is on for any given input signal level. The PNP stage (Transistor Q1 and Transistor Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. On the other hand, the NPN stage (Transistor Q5 and Transistor Q6) is needed for input voltages up to and including the positive rail.

For the majority of the input common-mode range, the PNP stage is active, as is shown in Figure 12. Notice that the bias current switches direction at approximately 1.2 V to 1.3 V below the positive rail. At voltages below this, the bias current flows out of the OP291, indicating a PNP input stage. Above this voltage, however, the bias current enters the device, revealing the NPN stage. The actual mechanism within the amplifier for switching between the input stages comprises Transistor Q3, Transistor Q4, and Transistor Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually, the emitters of Q1 and Q2 are high enough to turn on Q3, which diverts the 8 µA of tail current away from the PNP input stage, turning it off. Instead, the current is mirrored through Q4 and Q7 to activate the NPN input stage.

Notice that the input stage includes 5 kΩ series resistors and differential diodes, a common practice in bipolar amplifiers to protect the input transistors from large differential voltages. These diodes turn on whenever the differential voltage exceeds approximately 0.6 V. In this condition, current flows between the input pins, limited only by the two 5 kΩ resistors. This characteristic is important in circuits where the amplifier may be operated open-loop, such as a comparator. Evaluate each circuit carefully to make sure that the increase in current does not affect the performance.

The output stage in OP191 devices uses a PNP and an NPN transistor, as do most output stages; however, Q32 and Q33, the output transistors, are actually connected with their collectors to the output pin to achieve the rail-to-rail output swing. As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage does have inherent gain arising from the collectors and any external load impedance. Because of this, the open-loop gain of the amplifier is dependent on the load resistance.

+IN

5k

Q1

Q2

8µA

Q4

Q3

5k

–IN

Q5 Q6

Q7

Q10Q8

Q11

Q9

Figure 61. Simplified Schematic

Q14Q12

Q13 Q15

Q16

Q17

Q18 Q19

Q22

Q20

Q21

Q25 Q29

Q23

Q24

Q27

Q28

Q26

Q30

Q31

10pF

Q32

Q33

V

OUT

0294-065

Rev. E | Page 17 of 24

OP191/OP291/OP491

INPUT OVERVOLTAGE PROTECTION

As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, check the input overvoltage characteristic. When an overvoltage occurs, the amplifier could be damaged depending on the voltage level and the magnitude of the fault current. Figure 62 shows the characteristics for the OP191 family. This graph was generated with the power supplies at ground and a curve tracer connected to the input. When the input voltage exceeds either supply by more than 0.6 V, internal PN junctions energize, allowing current to flow from the input to the supplies. As described, the OP291/OP491 do have 5 kΩ resistors in series with each input to help limit the current. Calculating the slope of the current vs. voltage in the graph confirms the 5 kΩ resistor.

I

IN

+2mA

+1mA

–5V +10V–10V +5V

–1mA

–2mA

Figure 62. Input Overvoltage Characteristics

This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. For an input of 10 V over the supply, the current is limited to 1.8 mA. If the voltage is large enough to cause more than 5 mA of current to flow, then an external series resistor should be added. The size of this resistor is calculated by dividing the maximum overvoltage by 5 mA and subtracting the internal 5 kΩ resistor. For example, if the input voltage could reach 100 V, the external resistor should be (100 V/5 mA) − 5 k = 15 kΩ. This resistance should be placed in series with either or both inputs if they are subjected to the overvoltages.

V

IN

00294-066

OUTPUT VOLTAGE PHASE REVERSAL

Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically, for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these devices, external clamping diodes with the anode connected to ground and the cathode to the inputs prevent input signal excursions from exceeding the device’s negative supply (that is, GND), preventing a condition that could cause the output voltage to change phase. JFET input amplifiers can also exhibit phase reversal, and, if so, a series input resistor is usually required to prevent it.

The OP191 is free from reasonable input voltage range restrictions due to its novel input structure. In fact, the input signal can exceed the supply voltage by a significant amount without causing damage to the device. As shown in Figure 64, the OP191 family can safely handle a 20 V p-p input signal on ±5 V supplies without exhibiting any sign of output voltage phase reversal or other anomalous behavior. Thus, no external clamping diodes are required.

OVERDRIVE RECOVERY

The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large transient event, such as a comparator. The circuit shown in Figure 63 was used to evaluate the OPx91 overdrive recovery time. The OPx91 takes approximately 8 µs to recover from positive saturation and approximately 6.5 µs to recover from negative saturation.

R1

9k

V

IN

10V STEP

V

S

= ±5V

R2

10k

Figure 63. Overdrive Recovery Time Test Circuit

3

+

1/2

OP291

2

–

R3

10k

1

V

OUT

00294-068

V

20V p-p

5µs5µs

+5V

IN

8

3

+

1/2

OP291

–

2

4

–5V

1

V

OUT

100

90

(2.5V/DIV)

IN

V

10

0%

TIME (2 00µs/DIV)

100

90

(2V/DIV)

OUT

V

10

0%

20mV 20mV

TIME (200µ s/DIV)

00294-067

Figure 64. Output Voltage Phase Reversal Behavior

Rev. E | Page 18 of 24

OP191/OP291/OP491

V

APPLICATIONS INFORMATION

SINGLE 3 V SUPPLY, INSTRUMENTATION AMPLIFIER

The OP291 low supply current and low voltage operation make it ideal for battery-powered applications, such as the instrumentation amplifier shown in Figure 65. The circuit uses the classic two op amp instrumentation amplifier topology, with four resistors to set the gain. The equation is simply that of a noninverting amplifier, as shown in Figure 65. The two resistors labeled R1 should be closely matched both to each other and to the two resistors labeled R2 to ensure good common-mode rejection performance. Resistor networks ensure the closest matching as well as matched drifts for good temperature stability. Capacitor C1 is included to limit the bandwidth and, therefore, the noise in sensitive applications. The value of this capacitor should be adjusted depending on the desired closedloop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a frequency equal to 1/(2π × R1C1). If AC-CMRR is critical, then a matched capacitor to C1 should be included across the second resistor labeled R1.

3

8

+

V

IN

–

3

1/2

OP291

2

R1 R2 R2 R1

V

OUT

1

R1

= (1 + ) = V

R2

Figure 65. Single 3 V Supply Instrumentation Amplifier

Because the OP291 accepts rail-to-rail inputs, the input common-mode range includes both ground and the positive supply of 3 V. Furthermore, the rail-to-rail output range ensures the widest signal range possible and maximizes the dynamic range of the system. Also, with its low supply current of 300 µA/device, this circuit consumes a quiescent current of only 600 µA yet still exhibits a gain bandwidth of 3 MHz.

A question may arise about other instrumentation amplifier topologies for single-supply applications. For example, a variation on this topology adds a fifth resistor between the two inverting inputs of the op amps for gain setting. While that topology works well in dual-supply applications, it is inherently inappropriate for single-supply circuits. The same could be said for the traditional three op amp instrumentation amplifier. In both cases, the circuits simply cannot work in single-supply situations unless a false ground between the supplies is created.

5

1/2

7

V

OP291

6

4

C1

IN

100pF

OUT

00294-069

SINGLE-SUPPLY RTD AMPLIFIER

The circuit in Figure 66 uses three op amps of the OP491 to develop a bridge configuration for an RTD amplifier that operates from a single 5 V supply. The circuit takes advantage of the OP491 wide output swing range to generate a high bridge excitation voltage of 3.9 V. In fact, because of the rail-to-rail output swing, this circuit works with supplies as low as 4.0 V. Amplifier A1 servos the bridge to create a constant excitation current in conjunction with the AD589, a 1.235 V precision reference. The op amp maintains the reference voltage across the parallel combination of the 6.19 kΩ and 2.55 MΩ resistors, which generate a 200 µA current source. This current splits evenly and flows through both halves of the bridge. Thus, 100 µA flows through the RTD to generate an output voltage based on its resistance. A 3-wire RTD is used to balance the line resistance in both 100 Ω legs of the bridge to improve accuracy.

A2

GAIN = 274

OP491

5V

1/4

100k

0.01pF

A3

V

OUT

00294-070

200

10 TURNS

100

RTD

2.55M

6.19k

AD589

26.7k

5V

26.7k

OP491

37.4k

100

1/4

A1

1/4

OP491

365 365

100k

ALL RESISTORS 1% OR BETTER

Figure 66. Single-Supply RTD Amplifier

Amplifier A2 and Amplifier A3 are configured in the two op amp instrumentation amplifier topology described in the Single 3 V Supply, Instrumentation Amplifier section. The resistors are chosen to produce a gain of 274, such that each 1°C increase in temperature results in a 10 mV change in the output voltage, for ease of measurement. A 0.01 µF capacitor is included in parallel with the 100 kΩ resistor on Amplifier A3 to filter out any unwanted noise from this high gain circuit. This particular RC combination creates a pole at 1.6 kHz.

Rev. E | Page 19 of 24

OP191/OP291/OP491

A

V

A 2.5 V REFERENCE FROM A 3 V SUPPLY

In many single-supply applications, the need for a 2.5 V reference often arises. Many commercially available monolithic

2.5 V references require a minimum operating supply voltage of 4 V. The problem is exacerbated when the minimum operating system supply voltage is 3 V. The circuit illustrated in Figure 67 is an example of a 2.5 V reference that operates from a single 3 V supply. The circuit takes advantage of the OP291 rail-to-rail input and output voltage ranges to amplify an AD589 1.235 V output to 2.5 V. The OP291 low TCV maintain an output voltage temperature coefficient of less than 200 ppm/°C. The circuit overall temperature coefficient is dominated by the temperature coefficient of R2 and R3. Lower temperature coefficient resistors are recommended. The entire circuit draws less than 420 µA from a 3 V supply at 25°C.

3V

17.4k

D589

R1

R3

100k

3

1/2

OP291

2

R2

100k

3V

8

1

4

R1

5k

Figure 67. A 2.5 V Reference that Operates on a Single 3 V Supply

5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL

The OPx91 family is ideal for use with a CMOS DAC to generate a digitally controlled voltage with a wide output range. Figure 68 shows the DAC8043 used in conjunction with the AD589 to generate a voltage output from 0 V to 1.23 V. The DAC is operated in voltage switching mode, where the reference is connected to the current output, I is taken from the V noninverting as opposed to the classic current output mode, which is inverting and, therefore, unsuitable for single supply.

R1

17.8k

1.23V

D589

3

I

OUT

pin. This topology is inherently

REF

5

8

V

DD

DAC8043

GND CLK SR1

4765

DIGIT AL

CONTROL

2

R

FB

1

V

REF

LD

of 1 µV/°C helps

OS

2.5V

REF

RESISTORS = 1%, 100ppm/° C

POTENTI OMETER = 10 TURN, 100p pm/°C

, and the output voltage

OUT

5V

8

3

1/2

OP291

2

1

4

V

OUT

D

= –––– (5V)

4096

The OP291 serves two functions. First, it is required to buffer the high output impedance of the DAC V

pin, which is on the

REF

order of 10 kΩ. The op amp provides a low impedance output to drive any following circuitry. Second, the op amp amplifies the output signal to provide a rail-to-rail output swing. In this particular case, the gain is set to 4.1 to generate a 5.0 V output when the DAC is at full scale. If other output voltage ranges are needed, such as 0 V to 4.095 V, the gain can easily be adjusted by altering the value of the resistors.

A HIGH-SIDE CURRENT MONITOR

In the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistor’s longterm reliability over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime importance in these designs. The circuit illustrated in Figure 69 is an example of a 5 V, single-supply, high-side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. This design uses an OP291 rail-to-rail input voltage range to sense the voltage drop across a 0.1 Ω current shunt. A p-channel MOSFET used

00294-071

as the feedback element in the circuit converts the op amp differential input voltage into a current. This current is then applied to R2 to generate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by

R

SENSE

R

⎞

I

⎟

L

⎠

⎛

ROutputMonitor ×

×=12

⎜ ⎝

For the element values shown, the monitor output transfer characteristic is 2.5 V/A.

R

SENSE

0.1

S

G

D

MONITOR

OUTPUT

5V

100

3N163

2.49k

R1

M1

R2

Figure 69. A High-Side Load Current Monitor

I

L

3

1/2

OP291

2

5V

8

1

4

00294-073

R2

R3

2321%32.4k

1%

R4

100k

1%

00294-072

Figure 68. 5 V Only, 12-Bit DAC Swings Rail-to-Rail

Rev. E | Page 20 of 24

OP191/OP291/OP491

V

F

A 3 V, COLD JUNCTION COMPENSATED THERMOCOUPLE AMPLIFIER

The OP291 low supply operation makes it ideal for 3 V batterypowered applications such as the thermocouple amplifier shown in Figure 70. The K-type thermocouple terminates in an isothermal block where the junction ambient temperature is continuously monitored using a simple 1N914 diode. The diode corrects the thermal EMF generated in the junctions by feeding a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to the op amp.

The transmit signal, TXA, is inverted by A2 and then reinverted by A3 to provide a differential drive to the transformer, where each amplifier supplies half the drive signal. This is needed because of the smaller swings associated with a single supply as opposed to a dual supply. Amplifier A1 provides some gain for the received signal, and it also removes the transmit signal present at the transformer from the received signal. To do this, the drive signal from A2 is also fed to the noninverting input of A1 to cancel the transmit signal from the transformer.

390p

To calibrate this circuit, immerse the thermocouple measuring junction in a 0°C ice bath and adjust the 500 Ω potentiometer to 0 V out. Next, immerse the thermocouple in a 250°C temperature bath or oven and adjust the scale adjust potentiometer for an output voltage of 2.50 V. Within this temperature range, the K-type thermocouple is accurate to within ±3°C without linearization.

1.235

24.9k 1%

2.1k

1%

10k

24.3k 1%

4.99k

500 10 TURN

ZERO ADJUST

1%

3.0V

2

OP291

3

1.33M 20k

8

1/2

4

SCALE ADJUST

1

0V = 0°C 3V = 300° C

V

OUT

ISOTHERMAL

ALUMEL

AL

CR

CHROMEL

K-TYPE THERMOCOUPLE

40.7V/°C

BLOCK

1N914

AD589

7.15k

1.5M 1%

COLD JUNCTIONS

11.2mV

475

1%

Figure 70. A 3 V, Cold Junction Compensated Thermocouple Amplifier

SINGLE-SUPPLY, DIRECT ACCESS ARRANGEMENT FOR MODEMS

An important building block in modems is the telephone line interface. In the circuit shown in Figure 71, a direct access arrangement is used to transmit and receive data from the telephone line. Amplifier A1 is the receiving amplifier; Amplifier A2 and Amplifier A3 are the transmitters. The fourth amplifier, A4, generates a pseudo ground halfway between the supply voltage and ground. This pseudo ground is needed for the ac-coupled bipolar input signals.

37.4k

A1

0.1F

RXA

14

0.0047F

10

OP491

9

TXA

0.1F 20k,1%

750pF

6

OP491

5

00294-074

1

A4

1/4

OP491

3.3k

A2

1/4

37.4k,1%

20k,1%

A3

1/4

4

1/4

OP491

11

13

12

8

7

3V OR 5V

2

3

100k

20k,1%

475,1%

0.033F

5.1V TO 6. 2V ZENER 5

100k

10F0.1F

T1

1:1

0294-075

Figure 71. Single-Supply, Direct Access Arrangement for Modems

The OP491 bandwidth of 3 MHz and rail-to-rail output swings ensure that it can provide the largest possible drive to the transformer at the frequency of transmission.

Rev. E | Page 21 of 24

OP191/OP291/OP491

T

V

p

3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH FALSE GROUND

To process ac signals in a single-supply system, it is often best to use a false ground biasing scheme. Figure 72 illustrates a circuit that uses this approach. In this circuit, a false-ground circuit biases an active notch filter used to reject 50 Hz/60 Hz power line interference in portable patient monitoring equipment. Notch filters are quite commonly used to reject power line frequency interference that often obscures low frequency physiological signals, such as heart rates, blood pressure readings, EEGs, and EKGs. This notch filter effectively squelches 60 Hz pickup at a filter Q of 0.75. Substituting

3.16 kΩ resistors for the 2.67 kΩ resistors in the twin-T section (R1 through R5) configures the active filter to reject 50 Hz interference.

R2

2.67k

1

A1

R11

100k

1/4

OP491

R1

2.67k

R3

2.67k

C3

2F

(1F × 2)

C5

0.01F

8

A3

with False Ground

C1

1F1F

R12

499

C2

R5

1.33k (2.67k ÷ 2)

C6

1.5V

1F

R4

2.67k

5

6

R8 1k

1/4

OP491

R7

1k

V

OU

7

A2

3V

11

2

1/4

OP491

IN

3

4

R6 100k

3V

R9

1F

1M

C4

R10 1M

9

10

Figure 72. A 3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter

Amplifier A3 is the heart of the false ground bias circuit. It buffers the voltage developed by R9 and R10 and is the reference for the active notch filter. Because the OP491 exhibits a rail-to-rail input common-mode range, R9 and R10 are chosen to split the 3 V supply symmetrically. An in-the-loop compensation scheme used around the OP491 allows the op amp to drive C6, a 1 µF capacitor, without oscillation. C6 maintains a low impedance ac ground over the operating frequency range of the filter.

The filter section uses a pair of OP491s in a twin-T configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin-T section. Mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the pass band symmetry of the filter. Using 1% resistors and 5% capacitors produces satisfactory results.

SINGLE-SUPPLY, HALF-WAVE, AND FULL-WAVE RECTIFIERS

An OPx91 device configured as a voltage follower operating on a single supply can be used as a simple half-wave rectifier in low frequency (<2 kHz) applications. A full-wave rectifier can be configured with a pair of OP291s, as illustrated in Figure 73. The circuit works in the following way. When the input signal is above 0 V, the output of Amplifier A1 follows the input signal. Because the noninverting input of Amplifier A2 is connected to the output of A1, op amp loop control forces the inverting input of the A2 to the same potential. The result is that both terminals of R1 are equipotential; that is, no current flows. Because there is no current flow in R1, the same condition exists for R2; thus, the output of the circuit tracks the input signal. When the input signal is below 0 V, the output voltage of A1 is forced to 0 V. This condition now forces A2 to operate as an inverting voltage follower because the noninverting terminal of A2 is also at 0 V. The output voltage at V of the input signal. If needed, a buffered, half-wave rectified version of the input signal is available at V

5V

V

IN

3

2V p-

<2kHz

00294-076

V

IN

(1V/DIV)

V

A

OUT

(0.5V/DIV)

V

B

OUT

(0.5V/DIV)

Figure 73. Single-Supply, Half-Wave, and Full-Wave Rectifiers

OP291

2

100

90

10

0%

1/2

1V

8

4

A is then a full-wave rectified version

OUT

B.

OUT

R1

100k

1

A1

500mV

500mV 200s

TIME (200s/DIV)

6

1/2

OP291

5

R2

100k

V

OUT

7

A2

V

OUT

Using an OP291

A

FULL-WAVE RECTIFIE D OUTPUT

B

HALF-WAVE RECTIFIED OUTPUT

00294-077

Rev. E | Page 22 of 24

OP191/OP291/OP491

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT Y

0.10

4.00 (0.1574)

3.80 (0.1497)

SEATING

PLANE

85

1

1.27 (0.0500)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8° 0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

Figure 74. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8) [S-Suffix]

Dimensions shown in millimeters and (inches)

8.75 (0.3445)

8.55 (0.3366)

BSC

8

6.20 (0.2441)

5.80 (0.2283)

7

1.75 (0.0689)

1.35 (0.0531)

SEATING PLANE

8° 0°

0.25 (0.0098)

0.17 (0.0067)

14

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

Figure 75. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-14) [S-Suffix]

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC ST ANDARDS MO-153-AB-1

8

6.40 BSC

7

1.20

0.20

MAX

0.09

SEATING PLANE

8° 0°

Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

Rev. E | Page 23 of 24

0.75

0.60

0.45

060606-A

061908-A

OP191/OP291/OP491

0.210 (5.33) MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.775 (19.69)

0.750 (19.05)

0.735 (18.67)

14

1

0.100 (2.54) BSC

0.070 (1.78)

0.050 (1.27)

0.045 (1.14)

CONTROLL ING DIMENS IONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OF F INCH EQUI VALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN. CORNER LEADS M AY BE CONFIGURED AS WHOLE OR HAL F LEADS.

8

0.280 (7. 11)

0.250 (6.35)

0.240 (6.10)

7

0.060 (1.52) MAX

0.015 (0.38)

MIN

SEATING PLANE

0.005 (0.13) MIN

COMPLIANT TO JEDEC STANDARDS MS-001

GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92) MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

070606-A

Figure 77. 14-Lead Plastic Dual In-Line Package [PDIP]

(N-14)

[P-Suffix]

Dimensions shown s and (millimeters)

in inche

ORDERING GUIDE

Model1

OP191GS −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GS-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GS-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GSZ OP191GSZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP191GSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GS −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GS-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GS-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GSZ −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GSZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP291GSZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix] OP491GP −40°C to +125°C 14-Lead PDIP N-14 [P-Suffix] OP491GPZ −40°C to +125°C 14-Lead PDIP N-14 [P-Suffix] OP491GRU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 OP491GRUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14 OP491GS −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GS-REEL −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GS-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GSZ −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GSZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix] OP491GSZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 [S-Suffix]

1

Z = RoHS Compliant Part.

Temperature Range Package Description Package Option

−40°C to +125°C 8-Lead SOIC_N R-8 [S-Suffix]

Rev. E | Page 24 of 24

Datasheet OP191 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

PIN CONFIGURATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

INPUT OVERVOLTAGE PROTECTION

OUTPUT VOLTAGE PHASE REVERSAL

OVERDRIVE RECOVERY

APPLICATIONS INFORMATION

SINGLE 3 V SUPPLY, INSTRUMENTATION AMPLIFIER

SINGLE-SUPPLY RTD AMPLIFIER

A 2.5 V REFERENCE FROM A 3 V SUPPLY

5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL

A HIGH-SIDE CURRENT MONITOR

A 3 V, COLD JUNCTION COMPENSATED THERMOCOUPLE AMPLIFIER

SINGLE-SUPPLY, DIRECT ACCESS ARRANGEMENT FOR MODEMS

3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH FALSE GROUND

SINGLE-SUPPLY, HALF-WAVE, AND FULL-WAVE RECTIFIERS

OUTLINE DIMENSIONS

ORDERING GUIDE