ANALOG DEVICES MAT12 Service Manual
Audio, Dual-Matched
2
T
FEATURES
Very low voltage noise: 1 nV/√Hz maximum @ 100 Hz
Excellent current gain match: 0.5% typical
Low offset voltage (V
Outstanding offset voltage drift: 0.03 μV/°C typical
High gain bandwidth product: 200 MHz
GENERAL DESCRIPTION
The MAT12 is a dual, NPN-matched transistor pair that is
specifically designed to meet the requirements of ultralow
noise audio systems.
With its extremely low input base spreading resistance (rbb'
is typically 28 Ω) and high current gain (h
600 at I
to-noise ratios. The high current gain results in superior
performance compared to systems incorporating commercially
available monolithic amplifiers.
Excellent matching of the current gain (Δh
and low V
for symmetrically balanced designs, which reduce high-order
amplifier harmonic distortion.
Stability of the matching parameters is guaranteed by protection
diodes across the base emitter junction. These diodes prevent
= 1 mA), the MAT12 can achieve outstanding signal-
C
of less than 10 μV typical make the MAT12 ideal
OS
): 200 μV maximum
OS
typically exceeds
FE
) to about 0.5%
FE
NPN Transistor
MAT12
PIN CONFIGURATION
1
C
1
2
B
1
3
E
1
NOTE
1. SUBSTRATE IS CONNECTED
TO CASE ON TO-78 PACKAGE.
. SUBSTRATE IS NO RMALLY
CONNECTED TO THE M OS
NEGATI V E CIRCUIT P OTENTIAL,
BUT CAN BE FLOATED.
Figure 1. 6-Lead TO-78
degradation of beta and matching characteristics due to reverse
biasing of the base emitter junction.
The MAT12 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, because
the accuracy of a current mirror degrades exponentially with
mismatches of V
between transistor pairs, the low VOS of
BE
the MAT12 does not need offset trimming in most circuit
applications.
The MAT12 is a good replacement for the MAT02, and its
performance and characteristics are guaranteed over the
extended temperature range of −40°C to +85°C.
C
6
2
B
5
2
4
E
2
09044-001
Rev. 0
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Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
MAT12
TABLE OF CONTENTS
Features.............................................................................................. 1
Pin Configuration............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings............................................................ 4
REVISION HISTORY
7/10—Revision 0: Initial Version
Thermal Resistance.......................................................................4
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information.................................................................8
Fast Logarithmic Amplifier..........................................................8
Outline Dimensions....................................................................... 10
Ordering Guide .......................................................................... 10
Rev. 0 | Page 2 of 12
MAT12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCB = 15 V, IO = 10 μA, TA = 25°C, unless otherwise specified.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC AND AC CHARACTERISTICS
Current Gain1 h
−40°C ≤ TA ≤ +85°C 300
I
−40°C ≤ TA ≤ +85°C 200
Current Gain Match2 ΔhFE 10 μA ≤ IC ≤ 1 mA 0.5 5 %
Noise Voltage Density3 e
f
f
f
f
Low Frequency Noise (0.1 Hz to 10 Hz) eN p-p IC = 1 mA 0.4 μV p-p
Offset Voltage VOS V
−40°C ≤ TA ≤ +85°C 220 μV
Offset Voltage Change vs. VCB ΔVOS/ΔVCB 0 V ≤ VCB ≤ V
Offset Voltage Change vs. IC ΔVOS/ΔIC 1 μA ≤ IC ≤ 1 mA5, VCB = 0 V 5 70 μV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 0.08 1 μV/°C
−40°C ≤ TA ≤ +85°C, V
Breakdown Voltage, Collector to Emitter BV
Gain Bandwidth Product fT I
Collector-to-Base Leakage Current I
−40°C ≤ TA ≤ +85°C 3 nA
Collector-to-Collector Leakage Current
6, 7
−40°C ≤ TA ≤ +85°C 4 nA
Collector-to-Emitter Leakage Current
6, 7
I
−40°C ≤ TA ≤ +85°C 4 nA
Input Bias Current IB I
−40°C ≤ TA ≤ +85°C 50 nA
Input Offset Current IOS I
−40°C ≤ TA ≤ +85°C 13 nA
Input Offset Current Drift6 ΔIOS/ΔT IC = 10 μA, −40°C ≤ TA ≤ +85°C 40 150 pA/°C
Collector Saturation Voltage V
Output Capacitance COB V
Bulk Resistance6 R
Collector-to-Collector Capacitance CCC V
1
Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to V
2
Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(h
3
Noise voltage density is guaranteed, but not 100% tested.
4
This is the maximum change in VOS as VCB is swept from 0 V to 40 V.
5
Measured at IC = 10 μA and guaranteed by design over the specified range of IC.
6
Guaranteed by design.
7
ICC and I
are verified by the measurement of I
CES
CBO
.
I
FE
I
N
40 V
CEO
V
CBO
ICC V
V
CES
I
CE (SAT)
10 μA ≤ IC ≤ 10 mA 0.3 1.6 Ω
BE
FE min
= 1 mA 300 605
C
= 10 μA 200 550
C
= 1 mA, VCB = 0 V
C
= 10 Hz 1.6 2 nV/√Hz
O
= 100 Hz 0.9 1 nV/√Hz
O
= 1 kHz 0.85 1 nV/√Hz
O
= 10 kHz 0.85 1 nV/√Hz
O
= 0 V, IC = 1 mA 10 200 μV
CB
4
,1 μA ≤ IC ≤ 1 mA5 10 50 μV
MAX
trimmed to 0 V 0.03 0.3 μV/°C
OS
= 100 mA, VCE = 10 V 200 MHz
C
= V
CB
CC
CE
= 10 μA 50 nA
C
= 10 μA 6.2 nA
C
= 1 mA, IB = 100 μA 0.05 0.2 V
C
CB
CC
)/IC).
25 500 pA
MAX
= V
MAX
= V
, VBE = 0 V 35 500 pA
MAX
35 500 pA
= 15 V, IE = 0 μA 23 pF
= 0 V 35 pF
at the indicated collector currents.
MAX
Rev. 0 | Page 3 of 12
MAT12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Breakdown Voltage of
Collector-to-Base Voltage (BV
Breakdown Voltage of
Collector-to-Emitter Voltage (BV
Breakdown Voltage of
Collector-to-Collector Voltage (BV
Breakdown Voltage of
Emitter-to-Emitter Voltage (BV
Collector Current (IC) 20 mA
Emitter Current (IE) 20 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
CBO
)
)
CEO
CC
)
EE
40 V
40 V
40 V
)
40 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
6-Lead TO-78 150 45 °C/W
Unit
JC
ESD CAUTION
Rev. 0 | Page 4 of 12
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