Datasheet MAT12 Datasheet (ANALOG DEVICES)

Audio, Dual-Matched

2

T

FEATURES

Very low voltage noise: 1 nV/√Hz maximum @ 100 Hz
Excellent current gain match: 0.5% typical
Low offset voltage (V
Outstanding offset voltage drift: 0.03 μV/°C typical
High gain bandwidth product: 200 MHz

GENERAL DESCRIPTION

The MAT12 is a dual, NPN-matched transistor pair that is
specifically designed to meet the requirements of ultralow
noise audio systems.

With its extremely low input base spreading resistance (rbb'
is typically 28 Ω) and high current gain (h
600 at I
to-noise ratios. The high current gain results in superior
performance compared to systems incorporating commercially
available monolithic amplifiers.

Excellent matching of the current gain (Δh
and low V
for symmetrically balanced designs, which reduce high-order
amplifier harmonic distortion.

Stability of the matching parameters is guaranteed by protection
diodes across the base emitter junction. These diodes prevent

= 1 mA), the MAT12 can achieve outstanding signal-

C

of less than 10 μV typical make the MAT12 ideal

OS

): 200 μV maximum

OS

typically exceeds

FE

) to about 0.5%

FE

NPN Transistor

MAT12

PIN CONFIGURATION

1

C

1

2

B

1

3

E

1

NOTE

1. SUBSTRATE IS CONNECTED
TO CASE ON TO-78 PACKAGE.

. SUBSTRATE IS NO RMALLY
CONNECTED TO THE M OS
NEGATI V E CIRCUIT P OTENTIAL,
BUT CAN BE FLOATED.

Figure 1. 6-Lead TO-78

degradation of beta and matching characteristics due to reverse
biasing of the base emitter junction.

The MAT12 is also an ideal choice for accurate and reliable
current biasing and mirroring circuits. Furthermore, because
the accuracy of a current mirror degrades exponentially with
mismatches of V

between transistor pairs, the low VOS of

BE

the MAT12 does not need offset trimming in most circuit
applications.

The MAT12 is a good replacement for the MAT02, and its
performance and characteristics are guaranteed over the
extended temperature range of −40°C to +85°C.

C

6

2

B

5

2

4

E

2

09044-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

MAT12

TABLE OF CONTENTS

Features.............................................................................................. 1

Pin Configuration............................................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Absolute Maximum Ratings............................................................ 4

REVISION HISTORY

7/10—Revision 0: Initial Version

Thermal Resistance.......................................................................4

ESD Caution...................................................................................4

Typical Performance Characteristics ..............................................5

Applications Information.................................................................8

Fast Logarithmic Amplifier..........................................................8

Outline Dimensions....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. 0 | Page 2 of 12

MAT12

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VCB = 15 V, IO = 10 μA, TA = 25°C, unless otherwise specified.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

DC AND AC CHARACTERISTICS

Current Gain1 h

−40°C ≤ TA ≤ +85°C 300
I

−40°C ≤ TA ≤ +85°C 200
Current Gain Match2 ΔhFE 10 μA ≤ IC ≤ 1 mA 0.5 5 %
Noise Voltage Density3 e

f
f
f
f

Low Frequency Noise (0.1 Hz to 10 Hz) eN p-p IC = 1 mA 0.4 μV p-p
Offset Voltage VOS V

−40°C ≤ TA ≤ +85°C 220 μV
Offset Voltage Change vs. VCB ΔVOS/ΔVCB 0 V ≤ VCB ≤ V
Offset Voltage Change vs. IC ΔVOS/ΔIC 1 μA ≤ IC ≤ 1 mA5, VCB = 0 V 5 70 μV
Offset Voltage Drift ΔVOS/ΔT −40°C ≤ TA ≤ +85°C 0.08 1 μV/°C

−40°C ≤ TA ≤ +85°C, V
Breakdown Voltage, Collector to Emitter BV
Gain Bandwidth Product fT I
Collector-to-Base Leakage Current I

−40°C ≤ TA ≤ +85°C 3 nA
Collector-to-Collector Leakage Current

6, 7

−40°C ≤ TA ≤ +85°C 4 nA
Collector-to-Emitter Leakage Current

6, 7

I

−40°C ≤ TA ≤ +85°C 4 nA
Input Bias Current IB I

−40°C ≤ TA ≤ +85°C 50 nA
Input Offset Current IOS I

−40°C ≤ TA ≤ +85°C 13 nA
Input Offset Current Drift6 ΔIOS/ΔT IC = 10 μA, −40°C ≤ TA ≤ +85°C 40 150 pA/°C
Collector Saturation Voltage V
Output Capacitance COB V
Bulk Resistance6 R
Collector-to-Collector Capacitance CCC V

1

Current gain is guaranteed with collector-to-base voltage (VCB) swept from 0 V to V

2

Current gain match (ΔhFE) is defined as follows: ΔhFE = (100(ΔIB)(h

3

Noise voltage density is guaranteed, but not 100% tested.

4

This is the maximum change in VOS as VCB is swept from 0 V to 40 V.

5

Measured at IC = 10 μA and guaranteed by design over the specified range of IC.

6

Guaranteed by design.

7

ICC and I

are verified by the measurement of I

CES

CBO

.

I

FE

I

N

40 V

CEO

V

CBO

ICC V

V

CES

I

CE (SAT)

10 μA ≤ IC ≤ 10 mA 0.3 1.6 Ω

BE

FE min

= 1 mA 300 605

C

= 10 μA 200 550

C

= 1 mA, VCB = 0 V

C

= 10 Hz 1.6 2 nV/√Hz

O

= 100 Hz 0.9 1 nV/√Hz

O

= 1 kHz 0.85 1 nV/√Hz

O

= 10 kHz 0.85 1 nV/√Hz

O

= 0 V, IC = 1 mA 10 200 μV

CB

4

,1 μA ≤ IC ≤ 1 mA5 10 50 μV

MAX

trimmed to 0 V 0.03 0.3 μV/°C

OS

= 100 mA, VCE = 10 V 200 MHz

C

= V

CB

CC

CE

= 10 μA 50 nA

C

= 10 μA 6.2 nA

C

= 1 mA, IB = 100 μA 0.05 0.2 V

C

CB

CC

)/IC).

25 500 pA

MAX

= V

MAX

= V

, VBE = 0 V 35 500 pA

MAX

35 500 pA

= 15 V, IE = 0 μA 23 pF

= 0 V 35 pF

at the indicated collector currents.

MAX

Rev. 0 | Page 3 of 12

MAT12

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Breakdown Voltage of

Collector-to-Base Voltage (BV

Breakdown Voltage of

Collector-to-Emitter Voltage (BV

Breakdown Voltage of

Collector-to-Collector Voltage (BV

Breakdown Voltage of

Emitter-to-Emitter Voltage (BV
Collector Current (IC) 20 mA
Emitter Current (IE) 20 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

CBO

)

)

CEO

CC

)

EE

40 V

40 V

40 V

)

40 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA θ

6-Lead TO-78 150 45 °C/W

Unit

JC

ESD CAUTION

Rev. 0 | Page 4 of 12

MAT12

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VCE = 5 V, unless otherwise specified.

CH1 4.92V p-p

1

900

800

700

)

FE

600

500

= +125° C

T

A

TA =+25°C

CH1 2.00V M4.00s A CH1 15.8V

Figure 2. Low Frequency Noise (0.1 Hz to 10 Hz), I

1k

100

= 1µA TEST

I

C

10

1

NOISE VOLTAGE DENSITY (nV/ Hz)

0.1

0.1 1 10 100 1k 10k 100k

= 10µA TEST

I

C

IC = 1mA TEST

FREQUENCY (Hz)

Figure 3. Noise Voltage Density vs. Frequency

100

09044-002

= 1 mA, Gain = 10,000,000

C

400

CURRENT GAIN ( h

300

200

100

0.001 10.10.01
COLLECTOR CURRENT (mA)

Figure 5. Current Gain vs. Collector Current (V

T

=–55°C

A

= 0 V)

CB

09044-005

900

800

700

)

FE

600

500

400

300

CURRENT GAIN (h

200

100

0

–100 –50 0 50 100 150

09044-003

TEMPERATURE ( °C)

Figure 6. Current Gain vs. Temperature (Excludes I

1mA

1µA

CBO

09044-006

)

0.70

80

60

40

TOTAL NOISE (nV/ Hz)

20

0

0.001 10.10.01

RS = 100kΩ

R

= 10kΩ

S

R

= 1kΩ

S

COLLECTO R CURRENT , IC (mA)

Figure 4. Total Noise vs. Collector Current, f = 1 kHz

09044-004

Rev. 0 | Page 5 of 12

0.65

(V)

0.60

BE

0.55

0.50

0.45

0.40

BASE EMITT E R VO L TAGE, V

0.35

0.30

0.001 0.01 0.1 1 10
COLLECTOR CURRENT , IC (mA)

VCE = 5V

Figure 7. Base Emitter Voltage vs. Collector Current

09044-007

MAT12

h

m

100

1000

10

(MΩ)

IE

1

VCE = 5V

0.1

INPUT RESISTANCE,

0.01

0.001

0.001 0.01 0.1 1 10
COLLECTOR CURRENT , IC (mA)

Figure 8. Small Signal Input Resistance vs. Collector Current

1

0.1m

(mho)

OE

0.01m
VCE = 5V

1µ

CONDUCTANCE , h

0.1µ

100

(nA)

10

CBO

1

CURRENT, I

0.1

0.01
25 50 75 100 125

09044-008

TEMPERATURE ( °C)

09044-010

Figure 11. Collector-to-Base Leakage Current vs. Temperature

40

35

30

(pF)

25

CB

20

15

CAPACITANCE, C

10

5

0.01µ

0.001 10001001010.10.01
COLLECTOR CURRE N T, IC (mA)

Figure 9. Small Signal Output Conductance vs. Collector Current

100

T

= –55°C

(mA)

C

0.1

COLLECTOR CURRENT, I

0.01

A

10

T

A

1

0 0.10.20.30.40.50.60.70.80.9

SATURATION VOLTAGE, V

= +25°C

T

= +125°C

A

SAT

(V)

Figure 10. Collector Current vs. Saturation Voltage

0

0 1020304050

09044-009

REVERSE BIAS VOLTAGE (V)

09044-011

Figure 12. Collector-to-Base Capacitance vs. Reverse Bias Voltage

40

35

30

(pF)

25

CC

20

15

CAPACITANCE, C

10

5

0

0 1020304050

09044-018

COLLECTOR-TO-SUBSTRATE VOLTAGE (V)

09044-012

Figure 13. Collector-to-Collector Capacitance vs.

Collector-to-Substrate Voltage

Rev. 0 | Page 6 of 12

MAT12

R

R

1000

100

(nA)

CC

10

1

LEAKAGE CURRENT , I

COLLECTOR-TO-COLLECTO

0.1

4.0

3.5

3.0

(pF)

2.5

CC

2.0

1.5

CAPACITANCE, C

1.0

COLLECTOR-TO-COLLECTO

0.5

0.01
25 50 75 100 125

TEMPERAT UR E ( °C)

Figure 14. Collector-to-Collector Leakage Current vs. Temperature

0

0 1020304050

09044-013

REVERSE BIAS VOLTAGE (V)

09044-014

Figure 15. Collector-to-Collector Capacitance vs. Reverse Bias Voltage

Rev. 0 | Page 7 of 12

MAT12

V

APPLICATIONS INFORMATION

FAST LOGARITHMIC AMPLIFIER

The circuit of Figure 16 is a modification of a standard logarith­mic amplifier configuration. Running the MAT12 at 2.5 mA per
side (full scale) allows for a fast response with a wide dynamic
range. The circuit has a seven decade current range and a five
decade voltage range, and it is capable of 2.5 μs settling time to
1% with a 1 V to 10 V step. The output follows the equation:

V

kT

RR

+

V ln

=

O

23

R

2

REF

V

q

IN

V

IN

(0V TO 10V)

To compensate for the temperature dependence of the kT/q term, a
resistor with a positive 0.35%/°C temperature coefficient is selected
for R

. The output is inverted with respect to the input and is

2

nominally −1 V/decade using the component values indicated.

+15

R

S

4kΩ

2

3

330pF

8

AD8512

–15V

1

4

R

3

7.5kΩ

V

O

4kΩ

MAT12

R

2

500Ω
R

= 0.35%/°C

2

09044-015

330pF

R

1

V

REF

10V

4kΩ

6

5

1/2

AD8512

7

Figure 16. Fast Logarithmic Amplifier

Rev. 0 | Page 8 of 12

MAT12

I

I

Δ

LOG CONFORMANCE TESTING

The log conformance of the MAT12 is tested using the circuit

Because I
Equation 2 becomes

shown in Figure 18. The circuit employs a dual transdiode
logarithmic converter operating at a fixed ratio of collector
currents that are swept over a 10:1 range. The output of each
transdiode converter is the V
term, which is the product of the collector current and r
bulk emitter resistance. The difference of the V

of the transistor plus an error

BE

is amplified at

BE

BE

, the

As viewed on an oscilloscope, the change in ΔV
change in I

a gain of ×100 by the AMP02 instrumentation amplifier. The
differential emitter base voltage (ΔV

) consists of a temperature-

BE

dependent dc level plus an ac error voltage, which is the deviation
from true log conformity as the collector currents vary.

The output of the transdiode logarithmic converter comes from
the following idealized intrinsic transistor equation (for silicon)

kT

V ln= (1)

BE

C

I

q

S

where:

k is Boltzmann’s constant (1.38062 × 10
q is the unit electron charge (1.60219 × 10
T is the absolute temperature, K (= °C + 273.2).
I

is the extrapolated current for VBE → 0 (V

S

I

is the collector current.

C

An error term must be added to Equation 1 to allow for the
bulk resistance (r

) of the transistor. Error due to the op amp

BE

–23

J/K).

–19

°C).

tending to zero).

BE

With the oscilloscope ac-coupled, the temperature dependent
term becomes a dc offset and the trace represents the deviation
from true log conformity. The bulk resistance can be calculated
from the voltage deviation, ΔV

current (9 mA):
input current is limited by use of the AD8512 dual op amp. The
resulting AMP02 input is:

kT

V

BE

q

A ramp function that sweeps from 1 V to 10 V is converted by

C1

I

C2

BE1

C1

rIrI

−+==Δ ln (2)

BE2

C2

This procedure solves for r

provides the r

= R2.

R

1

the op amps to a collector current ramp through each transistor.

SIDE A DUT

V

1kΩ

1kΩ

CC

I

V

CC

I

C1

C2

Q1

+

100pF

100pF

+

–

Q2

SIDE B DUT

–

V

+15V

BE

500Ω

1N914

AV = 100

500Ω

1N914

V

BE

1/2

AD8512

–15V

–15V

1/2

AD8512

+15V

Figure 18. Log Conformance Circuit

is made equal to 10 IC2, and assuming TA = 25°C,

C1

ΔV

= 59 mV + 0.9 I

BE

is shown in Figure 17.

C

61.5

61.0

(mV)

60.5

BE

60.0

59.5

LOGGING ERROR,∆V

59.0

58.5
1 10 100

COLLECTOR CURRENT ( mA)

C1 rBE

(ΔrBE ~ 0)

Figure 17. Emitter Base, Log Conformity

, and the change in collector

O

V

1

r

BE

=

+15V

AMP02

–15V

O

mA9

BE

(3)

×

100

for Side A. Switching R1 and R2

BE

for Side B. Differential rBE is found by making

V

= 100∆V

OUT

BE

09044-017

for a 10:1

BE

09044-016

Rev. 0 | Page 9 of 12

MAT12

OUTLINE DIMENSIONS

REFERENCE P LANE

0.750 (19.05)

0.185 (4. 70 )

0.165 (4. 19 )

0.370 (9.40)

0.335 (8.51)

0.335 (8. 5 1)

0.305 (7. 7 5)

0.040 (1.0 2) MA X

0.045 (1.1 4)

0.010 (0.2 5)

CONTROLLING D IMENSIONS AR E IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE F OR USE IN DESIGN.

0.500 (12.70)

0.250 (6.35 ) MIN

0.050 (1. 27 ) MAX

0.019 (0.48 )

0.016 (0.41 )

0.021 (0.53)

0.016 (0.41)

BASE & SEATING PLANE

0.200

(5.08)

BSC

0.100
(2.54)

0.100 (2.54) BS C

3

2

BSC

4

5

1

0.034 (0.8 6)

0.027 (0.6 9)

BSC

Figure 19. 6-Pin Metal Header Package [TO-78]

(H-06)

Dimensions shown in inches and (millimeters)

0.160 (4.06)

0.110 (2.79)

0.045 (1.14)

0.027 (0.69)

6

45°

022306-A

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

MAT12AHZ −40°C to +85°C 6-Pin Metal Header Package [TO-78] H-06

1

Z = RoHS Compliant Part.

Rev. 0 | Page 10 of 12

MAT12

NOTES

Rev. 0 | Page 11 of 12

MAT12

NOTES

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09044-0-7/10(0)

Rev. 0 | Page 12 of 12