Low Noise, Matched
a
FEATURES
Dual Matched PNP Transistor
Low Offset Voltage: 100 mV max
Low Noise: 1 nV/√
High Gain: 100 min
High Gain Bandwidth: 190 MHz typ
Tight Gain Matching: 3% max
Excellent Logarithmic Conformance: rBE . 0.3 V typ
Available in Die Form
GENERAL DESCRIPTION
The MAT03 dual monolithic PNP transistor offers excellent
parametric matching and high frequency performance. Low
noise characteristics (1 nV/
(190 MHz typical), and low offset voltage (100 µV max), makes
the MAT03 an excellent choice for demanding preamplifier applications. Tight current gain matching (3% max mismatch) and
high current gain (100 min), over a wide range of collector current, makes the MAT03 an excellent choice for current mirrors.
A low value of bulk resistance (typically 0.3 Ω) also makes the
MAT03 an ideal component for applications requiring accurate
logarithmic conformance.
Hz @ 1 kHz max
√
Hz max @ 1 kHz), high bandwidth
Dual PNP Transistor
MA T03
PIN CONNECTION
TO-78
(H Suffix)
Each transistor is individually tested to data sheet specifications.
Device performance is guaranteed at 25°C and over the extended
industrial and military temperature ranges. To insure the longterm stability of the matching parameters, internal protection
diodes across the base-emitter junction clamp any reverse baseemitter junction potential. This prevents a base-emitter breakdown condition which can result in degradation of gain and
matching performance due to excessive breakdown current.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
MAT03–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ TA = +258C, unless otherwise noted.)
MAT03A MAT03E MAT03F
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units
Current Gain
Current Gain Matching
Offset Voltage
1
3
h
FE
2
Dh
FE
V
OS
VCB = 0 V, –36 V
= 1 mA 100 165 100 165 80 165
I
C
= 100 µA 90 150 90 150 70 150
I
C
IC = 10 µA 80 120 80 120 60 120
IC = 100 µA,VCB = 0 V 0.5 3 0.5 3 0.5 6 %
VCB = 0 V, IC = 100 µA 40 100 40 100 40 200 µV
Offset Voltage Change DVOS/DVCBIC = 100 µA
vs. Collector Voltage V
= 0 V 11 150 11 150 11 200 µV
CB1
= –36 V 11 150 11 150 11 200 µV
V
CB2
Offset Voltage Change DVOS/DICVCB = 0 V 12 50 12 50 12 75 µV
vs. Collector Current I
Bulk Resistance r
BE
= 10 µA, IC2 = 1 mA 12 50 12 50 12 75 µV
C1
VCB = 0 V 0.3 0.75 0.3 0.75 0.3 0.75 Ω
10 µA ≤ IC ≤ 1 mA 0.3 0.75 0.3 0.75 0.3 0.75 Ω
Offset Current I
OS
IC = 100 µA, VCB = 0 V 6 35 6 35 6 45 nA
Collector-Base
Leakage Current I
Noise Voltage Density
CB0
4
e
N
VCB = –36 V = V
MAX
IC = 1 mA, VCB = 0
= 10 Hz 0.8 2 0.8 0.8 nV/÷Hz
f
O
50 200 50 200 50 400 pA
fO = 100 Hz 0.7 1 0.7 0.7 nV/÷Hz
= 1 kHz 0.7 1 0.7 0.7 nV/÷Hz
f
O
= 10 kHz 0.7 1 0.7 0.7 nV/÷Hz
f
O
Collector Saturation
Voltage V
CE(SAT)
IC = 1 mA, IB = 100 µA 0.025 0.1 0.025 0.1 0.025 0.1 V
ELECTRICAL CHARACTERISTICS
(at –558C ≤ TA ≤ +1258C, unless otherwise noted.)
MAT03A
Parameter Symbol Conditions Min Typ Max Units
Current Gain h
FE
VCB = 0 V, –36 V
IC = 1 mA 70 110
= 100 µA 60 100
I
C
= 10 µA5085
I
Offset Voltage V
Offset Voltage Drift
5
Offset Current I
Breakdown Voltage BV
OS
TCV
OS
CEO
OS
ELECTRICAL CHARACTERISTICS
C
IC = 100 µA, VCB = 0 V 40 150 µV
IC = 100 µA, VCB = 0 V 0.3 0.5 µV/°C
IC = 100 µA, VCB = 0 V 15 85 nA
36 54 V
(at –408C ≤ TA ≤ +858C, unless otherwise noted.)
MAT03E MAT03F
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
Current Gain h
Offset Voltage V
Offset Voltage Drift
5
Offset Current I
FE
TCV
OS
Breakdown Voltage BV
OS
OS
CEO
VCB = 0 V, –36 V
I
= 1 mA 70 120 60 120
C
I
= 100 µA 60 105 50 105
C
I
= 10 µA 5090 4090
C
IC = 100 µA, VCB = 0 V 30 135 30 265 µV
IC = 100 µA, VCB = 0 V 0.3 0.5 0.3 1.0 µV/°C
IC = 100 µA, VCB = 0 V 10 85 10 200 nA
36 36 V
NOTES
1
Current gain is measured at collector-base voltages (VCB) swept from 0 to V
2
Current gain matching (∆hFE) is defined as: ∆h
3
Offset voltage is defined as: VOS = V
4
Sample tested. Noise tested and specified as equivalent input voltage for each transistor.
5
Guaranteed by VOS test (TCVOS = VOS/T for VOS ! VBE) where T = 298°K for TA = 25°C.
Specifications subject to change without notice.
BE1
– V
100(∆IB)hFE(min )
FE =
, where VOS is the differential voltage for IC1 = IC2: VOS = V
BE2
I
C
at indicated collector current. Typicals are measured at VCB = 0 V.
MAX
.
–2–
BE1
– V
BE2
=
I
KT
C1
In
q
.
I
C2
REV. B
MAT03
WARNING!
ESD SENSITIVE DEVICE
W AFER TEST LIMITS
Parameter Symbol Conditions Limits Units
Breakdown Voltage BV
Offset Voltage V
Current Gain h
Current Gain Match ∆h
Offset Voltage Change vs. V
Offset Voltage Change ∆V
vs. Collector Current I
Bulk Resistance r
Collector Saturation Voltage V
NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
DICE CHARACTERISTICS
(at 258C, unless otherwise noted.)
CEO
OS
FE
FE
CB
∆VOS/∆V
BE
CB
/∆I
OS
C
CE (SAT)
1. COLLECTOR (1 )
2. BASE (1 )
3. EMITTER (1 )
4. COLLECTOR (2)
5. BASE (2)
6. EMITTER (2 )
SUBSTRATE CAN BE
CONNECTED TO V– OR
FLOATED
MAT03N
36 V min
IC = 100 µA, VCB = 0 V 200 µV max
10 µA ≤ I
≤ 1 mA 200 µV max
C
IC = 1 mA, VCB = 0 V, –36 V 80 min
I
= 10 µA, VCB = 0 V, –36 V 60 min
C
IC = 100 µA, VCB = 0 V 6 % max
V
= 0 V, IC = 100 µA 200 µV max
CB1
V
= –36 V 200 µV max
CB2
VCB = 0 75 µV max
= 10 µA, IC2 = 1 mA 75 µV max
C1
10 µA ≤ IC ≤ 1 mA 0.75 Ω max
IC = 1 mA, IB = 100 µA 0.1 V max
ABSOLUTE MAXIMUM RATINGS
Collector-Base Voltage (BV
CBO
Collector-Emitter Voltage (BV
Collector-Collector Voltage (BV
Emitter-Emitter Voltage (BV
Collector Current (I
Emitter Current (I
C
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
E
EE
) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Total Power Dissipation
Ambient Temperature ≤ 70°C
1
) . . . . . . . . . . . . . . . . . . . .36 V
) . . . . . . . . . . . . . . . . . .36 V
CEO
) . . . . . . . . . . . . . . . . . .36 V
CC
) . . . . . . . . . . . . . . . . . . . . .36 V
2
. . . . . . . . . . . . . . . .500 mW
Operating Temperature Range
MAT03A . . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
MAT03E/F . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
ORDERING GUIDE
1
VOS max Temperature Package
Model (TA = +258C) Range Option
MAT03AH
2
100 µV –55°C to +125°C TO-78
MAT03EH 100 µV –40°C to +85°C TO-78
MAT03FH 200 µV –40°C to +85°C TO-78
NOTES
1
Burn-in is available on industrial temperature range parts.
2
For devices processed in total compliance to MIL-STD-883, add/883 after part
number. Consult factory for 883 data sheet.
Operating Junction Temperature . . . . . . . . . .–55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
Junction Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
NOTES
1
Absolute maximum ratings apply to both DICE and packaged devices.
2
Rating applies to TO-78 not using a heat sink, and LCC; devices in free air only. For
TO-78, derate linearly at 6.3 mW/°C above 70°C ambient temperature; for LCC,
derate at 7.8 mW/°C.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT03 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
MAT03
Figure 1. Current Gain vs.
Collector Current
Figure 4. Base-Emitter Voltage
vs. Collector Current
Figure 2. Current Gain
vs. Temperature
Figure 5. Small-Signal Input Resistance
) vs. Collector Current
(h
ie
Figure 3. Gain Bandwidth vs.
Collector Current
Figure 6. Small Signal Output Conductance (h
) vs. Collector Current
oe
–4–
REV. B
MAT03
Figure 7. Saturation Voltage
vs. Collector Current
Figure 10. Total Noise vs. Collector Current
Figure 8. Noise Voltage Density
vs. Frequency
Figure 11. Collector-Base Capacitance vs. V
Figure 9. Noise Voltage Density
CB
REV. B
–5–
MAT03
Figure 12. SPICE or SABER Model
APPLICATIONS INFORMATION
MAT03 MODELS
The MAT03 model (Figure 12) includes parasitic diodes D
3
through D6. D1 and D2 are internal protection diodes which
prevent zenering of the base-emitter junctions.
The analysis programs, SPICE and SABER, are primarily used
in evaluating the functional performance of systems. The models are provided only as an aid in utilizing these simulation
programs.
MAT03 NOISE MEASUREMENT
All resistive components (Johnson noise, e
0.13√
R nV/√Hz, where R is in kΩ) and semiconductor junctions
2
= 4kTBR, or en =
n
(Shot noise, caused by current flowing through a junction, produces voltage noise in series impedances such as transistorcollector load resistors, I
= 0.566 √I pA/√Hz where I is in µA)
n
contribute to the system input noise.
Figure 13 illustrates a technique for measuring the equivalent
input noise voltage of the MAT03. 1 mA of stage current is used
Figure 13. MAT03 Voltage Noise Measurement Circuit
–6–
REV. B
MAT03
to bias each side of the differential pair. The 5 kΩ collector resistors noise contribution is insignificant compared to the voltage noise of the MAT03. Since noise in the signal path is
referred back to the input, this voltage noise is attenuated by the
gain of the circuit. Consequently, the noise contribution of the
collector load resistors is only 0.048 nV/√
ably less than the typical 0.8 nV/√
MAT03 transistor.
The noise contribution of the OP27 gain stages is also negligible
due to the gain in the signal path. The op amp stages amplify
the input referred noise of the transistors to increase the signal
strength to allow the noise spectral density (e
measured with a spectrum analyzer. And, since we assume
equal noise contributions from each transistor in the MAT03,
the output is divided by √
input noise.
Air currents cause small temperature changes that can appear
as
low frequency noise. To eliminate this noise source, the
2 to determine a single transistor’s
Hz. This is consider-
Hz input noise voltage of the
× 10000) to be
in
measurement circuit must be thermally isolated. Effects of extraneous noise sources must also be eliminated by totally shielding
the circuit.
SUPER LOW NOISE AMPLIFIER
The circuit in Figure 14a is a super low noise amplifier with
equivalent input voltage noise of 0.32 nV/√
three MAT03 matched pairs, a further reduction of amplifier
noise is attained by a reduction of the base spreading resistance
by a factor of 3, and consequently the noise by √
the shot noise contribution is reduced by maintaining a high collector current (2 mA/device) which reduces the dynamic emitter
resistance and decreases voltage noise. The voltage noise is inversely proportional to the square root of the stage current, and
current noise increases proportionally to the square root of the
stage current. Accordingly, this amplifier capitalizes on voltage
noise reduction techniques at the expense of increasing the current noise. However, high current noise is not usually important
when dealing with low impedance sources.
Hz. By paralleling
3. Additionally,
REV. B
Figure 14a. Super Low Noise Amplifier
–7–
MAT03
This amplifier exhibits excellent full power ac performance,
0.08% THD into a 600 Ω load, making it suitable for exacting
audio applications (see Figure 14b).
Figure 14b. Super Low Noise Amplifier—Total
Harmonic Distortion
LOW NOISE MICROPHONE PREAMPLIFIER
Figure 15 shows a microphone preamplifier that consists of a
MAT03 and a low noise op amp. The input stage operates at a
relatively high quiescent current of 2 mA per side, which reduces
the MAT03 transistor’s voltage noise. The 1/ƒ corner is less than
1 Hz. Total harmonic distortion is under 0.005% for a 10 V p-p
signal from 20 Hz to 20 kHz. The preamp gain is 100, but can be
modified by varying R
A total input stage emitter current of 4 mA is provided by Q
The constant current in Q
or R6 (V
5
is set by using the forward voltage of
2
OUT/VIN
= R5/R6 + 1).
.
2
a GaAsP LED as a reference. The difference between this voltage
and the V
of a silicon transistor is predictable and constant (to
BE
a few percent) over a wide temperature range. The voltage difference, approximately 1 V, is dropped across the 250 Ω resistor
which produces a temperature stabilized emitter current.
CURRENT SOURCES
A fundamental requirement for accurate current mirrors and active load stages is matched transistor components. Due to the
excellent V
matching (the voltage difference between VBE’s
BE
required to equalize collector current) and gain matching, the
MAT03 can be used to implement a variety of standard current
mirrors that can source current into a load such as an amplifier
stage. The advantages of current loads in amplifiers versus resistors is an increase of voltage gain due to higher impedances,
larger signal range, and in many applications a wider signal
bandwidth.
Figure 16 illustrates a cascode current mirror consisting of two
MAT03 transistor pairs.
The cascode current source has a common base transistor in series with the output which causes an increase in output impedance of the current source since V
stays relatively constant.
CE
High frequency characteristics are improved due to a reduction
of Miller capacitance. The small-signal output impedance can
be determined by consulting “h
vs. Collector Current” typical
OF
graph. Typical output impedance levels approach the performance of a perfect current source.
Considering a typical collector current of 100 µA, we have:
ro
=
Q3
1
= 1 M
µ
MHOS
1.0
Ω
Figure 15. Low Noise Microphone Preamplifier
–8–
REV. B
MAT03
Q2 and Q3 are in series and operate at the same current levels so
the total output impedance is:
RO = hFE roQ3 @ (160)(1 MΩ) = 160 MΩ.
Figure 16. Cascode Current Source
CURRENT MATCHING
The objective of current source or mirror design is generation of
currents that are either matched or must maintain a constant ratio. However, mismatch of base-emitter voltages cause output
current errors. Consider the example of Figure 17a. If the resistors and transistors are equal and the collector voltages are the
same, the collector currents will match precisely. Investigating
the current-matching errors resulting from a nonzero V
define ∆I
as the current error between the two transistors.
C
OS
, we
Graph 17b describes the relationship of current matching errors
versus offset voltage for a specified average current I
. Note that
C
since the relative error between the currents is exponentially proportional to the offset voltage, tight matching is required to design high accuracy current sources. For example, if the offset
voltage is 5 mV at 100 µA collector current, the current match-
ing error would be 20%. Additionally, temperature effects such
as offset drift (3 µV/°C per mV of V
if Q
and Q2 are not well matched.
1
DIGITALLY PROGRAMMABLE BIPOLAR CURRENT
PUMP
) will degrade performance
OS
The circuit of Figure 18 is a digitally programmable current
pump. The current pump incorporates a DAC08, and a fast
Wilson current source using the MAT03. Examining Figure 18,
the DAC08 is set for 2 mA full-scale range so that bipolar current operation of ±2 mA is achieved. The Wilson current mirror
maintains linearity within the LSB range of the 8-bit DAC08
(±2 mA/256 = 15.6 µA resolution) as seen in Figure 19. A
negative feedback path established by Q
regulates the collector
2
current so that it matches the reference current programmed by
the DAC08.
Collector-emitter voltages across both Q
by D
, with Q3’s collector-emitter voltage remaining constant,
1
and Q3 are matched
1
independent of the voltage across the current source output.
Since Q
maintain the same collector current. D
clamp which prevents Q
buffers Q3, both transistors in the MAT03, Q1 and Q3,
2
from turning off, thereby improving
2
and D3 form a Baker
2
the switching speed of the current mirror. The feedback serves
to increase the output impedance and improves accuracy by reducing the base-width modulation which occurs with varying
collector-emitter voltages. Accuracy and linearity performance
of the current pump is summarized in Figure 19.
Figure 17a. Current Matching Circuit
Figure 17b. Current Matching Accuracy %
vs. Offset Voltage
REV. B
Figure 18. Digitally Programmable Bipolar Current Pump
–9–
MAT03
Figure 19. Digitally Programmable Current
Pump—INL Error as Digital Code
The full-scale output of the DAC08, I
of I
REF
256
IFR =
The current mirror output is I
I
REF
I = 2 I
= 2
256
= 2 mA:
– 1.992 mA
OUT
Input Code
256
× I
, and I
REF
(2 mA) – 1.992 mA.
OUT
OUT
+
–
, is a linear function
OUT
= I
REF
= 1, so that if
I
I
OUT
OUT
256
256
DIGITAL CURRENT PUMP CODING
Digital Input
B1 . . . B8 Output Current
FULL RANGE 1111 1111 I = 1.992 mA
HALF-RANGE 1000 0000 I = 0.008 mA
ZERO-SCALE 0000 0000 I = –1.992 mA
–10–
REV. B
0.185 (4.70)
0.165 (4.19)
0.370 (9.40)
0.335 (8.51)
0.335 (8.51)
0.305 (7.75)
0.040 (1.02) MAX
0.045 (1.14)
0.010 (0.25)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
TO-78 Metal Can
REFERENCE PLANE
0.750 (19.05)
0.500 (12.70)
0.250 (6. 35) MIN
0.050 (1.27) MAX
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
BASE & SEATING PLANE
0.200
(5.08)
BSC
0.100
(2.54)
BSC
0.100 (2.54) BSC
4
3
2
1
0.034 (0.86)
0.027 (0.69)
0.160 (4.06)
0.110 (2.79)
5
6
45° BSC
0.045 (1.14)
0.027 (0.69)
MAT03
REV. B
–11–
000000000
–12–
PRINTED IN U.S.A.
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