Analog Devices MAT03 Datasheet

Low Noise, Matched

a

FEATURES
Dual Matched PNP Transistor
Low Offset Voltage: 100 mV max
Low Noise: 1 nV/√
High Gain: 100 min
High Gain Bandwidth: 190 MHz typ
Tight Gain Matching: 3% max
Excellent Logarithmic Conformance: rBE . 0.3 V typ
Available in Die Form

GENERAL DESCRIPTION

The MAT03 dual monolithic PNP transistor offers excellent
parametric matching and high frequency performance. Low
noise characteristics (1 nV/
(190 MHz typical), and low offset voltage (100 µV max), makes
the MAT03 an excellent choice for demanding preamplifier ap­plications. Tight current gain matching (3% max mismatch) and
high current gain (100 min), over a wide range of collector cur­rent, makes the MAT03 an excellent choice for current mirrors.
A low value of bulk resistance (typically 0.3 Ω) also makes the
MAT03 an ideal component for applications requiring accurate
logarithmic conformance.

Hz @ 1 kHz max

√

Hz max @ 1 kHz), high bandwidth

Dual PNP Transistor

MA T03

PIN CONNECTION

TO-78

(H Suffix)

Each transistor is individually tested to data sheet specifications.
Device performance is guaranteed at 25°C and over the extended
industrial and military temperature ranges. To insure the long­term stability of the matching parameters, internal protection
diodes across the base-emitter junction clamp any reverse base­emitter junction potential. This prevents a base-emitter break­down condition which can result in degradation of gain and
matching performance due to excessive breakdown current.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

MAT03–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ TA = +258C, unless otherwise noted.)

MAT03A MAT03E MAT03F

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

Current Gain

Current Gain Matching
Offset Voltage

1

3

h

FE

2

Dh

FE

V

OS

VCB = 0 V, –36 V

= 1 mA 100 165 100 165 80 165

I

C

= 100 µA 90 150 90 150 70 150

I

C

IC = 10 µA 80 120 80 120 60 120
IC = 100 µA,VCB = 0 V 0.5 3 0.5 3 0.5 6 %
VCB = 0 V, IC = 100 µA 40 100 40 100 40 200 µV

Offset Voltage Change DVOS/DVCBIC = 100 µA

vs. Collector Voltage V

= 0 V 11 150 11 150 11 200 µV

CB1

= –36 V 11 150 11 150 11 200 µV

V

CB2

Offset Voltage Change DVOS/DICVCB = 0 V 12 50 12 50 12 75 µV

vs. Collector Current I

Bulk Resistance r

BE

= 10 µA, IC2 = 1 mA 12 50 12 50 12 75 µV

C1

VCB = 0 V 0.3 0.75 0.3 0.75 0.3 0.75 Ω
10 µA ≤ IC ≤ 1 mA 0.3 0.75 0.3 0.75 0.3 0.75 Ω

Offset Current I

OS

IC = 100 µA, VCB = 0 V 6 35 6 35 6 45 nA

Collector-Base

Leakage Current I

Noise Voltage Density

CB0

4

e

N

VCB = –36 V = V

MAX

IC = 1 mA, VCB = 0

= 10 Hz 0.8 2 0.8 0.8 nV/÷Hz

f

O

50 200 50 200 50 400 pA

fO = 100 Hz 0.7 1 0.7 0.7 nV/÷Hz

= 1 kHz 0.7 1 0.7 0.7 nV/÷Hz

f

O

= 10 kHz 0.7 1 0.7 0.7 nV/÷Hz

f

O

Collector Saturation

Voltage V

CE(SAT)

IC = 1 mA, IB = 100 µA 0.025 0.1 0.025 0.1 0.025 0.1 V

ELECTRICAL CHARACTERISTICS

(at –558C ≤ TA ≤ +1258C, unless otherwise noted.)

MAT03A

Parameter Symbol Conditions Min Typ Max Units

Current Gain h

FE

VCB = 0 V, –36 V

IC = 1 mA 70 110

= 100 µA 60 100

I

C

= 10 µA5085

I
Offset Voltage V
Offset Voltage Drift

5

Offset Current I
Breakdown Voltage BV

OS

TCV

OS

CEO

OS

ELECTRICAL CHARACTERISTICS

C

IC = 100 µA, VCB = 0 V 40 150 µV
IC = 100 µA, VCB = 0 V 0.3 0.5 µV/°C
IC = 100 µA, VCB = 0 V 15 85 nA

36 54 V

(at –408C ≤ TA ≤ +858C, unless otherwise noted.)

MAT03E MAT03F

Parameter Symbol Conditions Min Typ Max Min Typ Max Units

Current Gain h

Offset Voltage V
Offset Voltage Drift

5

Offset Current I

FE

TCV

OS

Breakdown Voltage BV

OS

OS

CEO

VCB = 0 V, –36 V

I

= 1 mA 70 120 60 120

C

I

= 100 µA 60 105 50 105

C

I

= 10 µA 5090 4090

C

IC = 100 µA, VCB = 0 V 30 135 30 265 µV
IC = 100 µA, VCB = 0 V 0.3 0.5 0.3 1.0 µV/°C
IC = 100 µA, VCB = 0 V 10 85 10 200 nA

36 36 V

NOTES

1

Current gain is measured at collector-base voltages (VCB) swept from 0 to V

2

Current gain matching (∆hFE) is defined as: ∆h

3

Offset voltage is defined as: VOS = V

4

Sample tested. Noise tested and specified as equivalent input voltage for each transistor.

5

Guaranteed by VOS test (TCVOS = VOS/T for VOS ! VBE) where T = 298°K for TA = 25°C.

Specifications subject to change without notice.

BE1

– V

100(∆IB)hFE(min )

FE =

, where VOS is the differential voltage for IC1 = IC2: VOS = V

BE2

I

C

at indicated collector current. Typicals are measured at VCB = 0 V.

MAX

.

–2–

BE1

– V

BE2

=

I





KT

C1





In

q

.

I





C2

REV. B

MAT03

WARNING!

ESD SENSITIVE DEVICE

W AFER TEST LIMITS

Parameter Symbol Conditions Limits Units

Breakdown Voltage BV
Offset Voltage V

Current Gain h
Current Gain Match ∆h

Offset Voltage Change vs. V
Offset Voltage Change ∆V

vs. Collector Current I
Bulk Resistance r
Collector Saturation Voltage V

NOTE:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

DICE CHARACTERISTICS

(at 258C, unless otherwise noted.)

CEO

OS

FE

FE

CB

∆VOS/∆V

BE

CB

/∆I

OS

C

CE (SAT)

1. COLLECTOR (1 )

2. BASE (1 )

3. EMITTER (1 )

4. COLLECTOR (2)

5. BASE (2)

6. EMITTER (2 )

SUBSTRATE CAN BE
CONNECTED TO V– OR
FLOATED

MAT03N

36 V min
IC = 100 µA, VCB = 0 V 200 µV max
10 µA ≤ I

≤ 1 mA 200 µV max

C

IC = 1 mA, VCB = 0 V, –36 V 80 min
I

= 10 µA, VCB = 0 V, –36 V 60 min

C

IC = 100 µA, VCB = 0 V 6 % max
V

= 0 V, IC = 100 µA 200 µV max

CB1

V

= –36 V 200 µV max

CB2

VCB = 0 75 µV max

= 10 µA, IC2 = 1 mA 75 µV max

C1

10 µA ≤ IC ≤ 1 mA 0.75 Ω max
IC = 1 mA, IB = 100 µA 0.1 V max

ABSOLUTE MAXIMUM RATINGS

Collector-Base Voltage (BV

CBO

Collector-Emitter Voltage (BV
Collector-Collector Voltage (BV
Emitter-Emitter Voltage (BV
Collector Current (I
Emitter Current (I

C

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

E

EE

) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Total Power Dissipation

Ambient Temperature ≤ 70°C

1

) . . . . . . . . . . . . . . . . . . . .36 V

) . . . . . . . . . . . . . . . . . .36 V

CEO

) . . . . . . . . . . . . . . . . . .36 V

CC

) . . . . . . . . . . . . . . . . . . . . .36 V

2

. . . . . . . . . . . . . . . .500 mW

Operating Temperature Range

MAT03A . . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C

MAT03E/F . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C

ORDERING GUIDE

1

VOS max Temperature Package

Model (TA = +258C) Range Option

MAT03AH

2

100 µV –55°C to +125°C TO-78
MAT03EH 100 µV –40°C to +85°C TO-78
MAT03FH 200 µV –40°C to +85°C TO-78

NOTES

1

Burn-in is available on industrial temperature range parts.

2

For devices processed in total compliance to MIL-STD-883, add/883 after part
number. Consult factory for 883 data sheet.

Operating Junction Temperature . . . . . . . . . .–55°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C

Junction Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C

NOTES

1

Absolute maximum ratings apply to both DICE and packaged devices.

2

Rating applies to TO-78 not using a heat sink, and LCC; devices in free air only. For
TO-78, derate linearly at 6.3 mW/°C above 70°C ambient temperature; for LCC,
derate at 7.8 mW/°C.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT03 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–3–

MAT03

Figure 1. Current Gain vs.
Collector Current

Figure 4. Base-Emitter Voltage
vs. Collector Current

Figure 2. Current Gain
vs. Temperature

Figure 5. Small-Signal Input Resistance

) vs. Collector Current

(h

ie

Figure 3. Gain Bandwidth vs.
Collector Current

Figure 6. Small Signal Output Con­ductance (h

) vs. Collector Current

oe

–4–

REV. B