Datasheet MAT02 Datasheet (Analog Devices)

Low Noise, Matched

FEATURES Low Offset Voltage: 50 mV max Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/√Hz max High Gain (h

Excellent Log Conformance: r Low Offset Voltage Drift: 0.1 mV/8C max Improved Direct Replacement for LM194/394 Available in Die Form

PRODUCT DESCRIPTION

The design of the MAT02 series of NPN dual monolithic transistors is optimized for very low noise, low drift, and low r Precision Monolithics’ exclusive Silicon Nitride “TriplePassivation” process stabilizes the critical device parameters over wide ranges of temperature and elapsed time. Also, the high current gain (h range of collector current. Exceptional characteristics of the MAT02 include offset voltage of 50 µV max (A/E grades) and 150 µV max F grade. Device performance is specified over the full military temperature range as well as at 25°C.

Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection diodes. This results in complete isolation between the transistors.

The MAT02 should be used in any application where low noise is a priority. The MAT02 can be used as an input stage to make an amplifier with noise voltage of less than 1.0 nV/√ Other applications, such as log/antilog circuits, may use the excellent logging conformity of the MAT02. Typical bulk resistance is only 0.3 Ω to 0.4 Ω. The MAT02 electrical characteristics approach those of an ideal transistor when operated over a collector current range of 1 µA to 10 mA. For applications re- quiring multiple devices see MAT04 Quad Matched Transistor data sheet.

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

): 500 min at IC = 1 mA

300 min at I

) of the MAT02 is maintained over a wide

= 1 mA

. 0.3 V

Hz at 100 Hz.

Dual Monolithic Transistor

MAT02

PIN CONNECTION

TO-78

(H Suffix)

NOTE Substrate is connected to case on TO-78 package. Substrate is normally connected to the most negative circuit potential, but can be floated.

ABSOLUTE MAXIMUM RATINGS

Collector-Base Voltage (BV

CBO

Collector-Emitter Voltage (BV Collector-Collector Voltage (BV Emitter-Emitter Voltage (BV Collector Current (I Emitter Current (I

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Total Power Dissipation

Case Temperature ≤ 40°C

) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Ambient Temperature ≤ 70°C

Operating Temperature Range

MAT02A . . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C

MAT02E, F . . . . . . . . . . . . . . . . . . . . . . . . .–25°C to +85°C

Operating Junction Temperature . . . . . . . . . .–55°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C

Junction Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C

NOTES

Absolute maximum ratings apply to both DICE and packaged devices.

Rating applies to applications using heat sinking to control case temperature.

Derate linearly at 16.4 mW/°C for case temperature above 40°C.

Rating applies to applications not using a heat sinking; devices in free air only. Derate linearly at 6.3 mW/°C for ambient temperature above 70 °C.

ORDERING GUIDE

VOS max Temperature Package

Model (TA = +258C) Range Option

MAT02AH250 µV –55°C to +125°C TO-78 MAT02EH 50 µV –55°C to +125°C TO-78 MAT02FH 150 µV –55°C to +125°C TO-78

NOTES

Burn-in is available on commercial and industrial temperature range parts in TO-can packages.

For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

) . . . . . . . . . . . . . . . . . . . .40 V

) . . . . . . . . . . . . . . . . . .40 V

CEO

) . . . . . . . . . . . . . . . . . .40 V

) . . . . . . . . . . . . . . . . . . . . .40 V

. . . . . . . . . . . . . . . . . . . . .1.8 W

. . . . . . . . . . . . . . . .500 mW

MAT02–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VCB = 15 V, IC = 10 mA, TA = 258C, unless otherwise noted.)

MAT02A/E MAT02F

Parameter Symbol Conditions Min Typ Max Min Typ Max Units

Current Gain h

Current Gain Match ∆h Offset Voltage V Offset Voltage ∆V

Change vs. V

Offset Voltage Change ∆V

/∆VCB0 ≤ VCB ≤ V

/∆I

IC = 1 mA I

= 100 µA 500 590 400 590

= 10 µA 400 550 300 550

= 1 µA 300 485 200 485

10 µA ≤ IC ≤ 1 mA VCB = 0, 1 µA ≤ IC ≤ 1 mA

1 µA ≤ IC ≤ 1 mA VCB = 0 V 5 25 5 50 µV

vs. Collector Current 1 µA ≤ I

MAX

≤ 1 mA

500 605 400 605

0.5 2 0.5 4 % 10 50 80 150 µV 10 25 10 50 µV 10 25 10 50 µV

525 5 50µV

Offset Current

Change vs. V

Bulk Resistance r

∆IOS/∆V

0 ≤ VCB ≤ V

10 µA ≤ IC ≤ 10 mA

MAX

30 70 30 70 pA/V

0.3 0.5 0.3 0.5 Ω

Collector-Base

Leakage Current I

CBO

Collector-Collector

Leakage Current I

Collector-Emitter V

Leakage Current I

Noise Voltage Density e

CES

VCB = V VCC = V VBE = 0 35 200 35 400 pA

IC = 1 mA, VCB = 0

= V

MAX

MAX MAX

5, 6 5, 6

25 200 25 400 pA 35 200 35 400 pA

fO = 10 Hz 1.6 2 1.6 3 nV/√Hz f

= 100 Hz 0.9 1 0.9 2 nV/√Hz

= 1 kHz 0.85 1 0.85 2 nV/√Hz

= 10 kHz 0.85 1 0.85 2 nV/√Hz

Collector Saturation

Voltage V Input Bias Current I Input Offset Current I

B OS

Breakdown Voltage BV Gain-Bandwidth Product f

Output Capacitance C

CE(SAT)

CEO

IC = 1 mA, IB = 100 µA 0.05 0.1 0.05 0.2 V IC = 10 µA2534nA IC = 10 µA 0.6 1.3 nA

40 40 V IC = 10 mA, VCE = 10 V 200 200 MHz VCB = 15 V, IE = 0 23 23 pF

Collector-Collector

Capacitance C

NOTES

Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to V

Current gain match (∆hFE) is defined as: ∆h

Measured at IC = 10 µA and guaranteed by design over the specified range of IC.

This is the maximum change in VOS as VCB is swept from 0 V to 40 V.

Guaranteed by design.

ICC and I

Sample tested.

Specifications subject to change without notice.

are verified by measurement of I

CES

VCC = 0 35 35 pF

at the indicated collector currents.

100 (∆IB) (hFE min)

FE =

CBO

MAX

–2–

REV. C

MAT02

ELECTRICAL CHARACTERISTICS

(VCB = 15 V, –258C ≤ TA ≤ +858C, unless otherwise noted.)

MAT02E MAT02F

Parameter Symbol Conditions Min Typ Max Min Typ Max Units

Offset Voltage V Average Offset

Voltage Drift TCV

Input Offset Current I Input Offset

Current Drift TCI Input Bias Current I Current Gain h

Collector-Base I

CBO

VCB = 0 70 220 µV 1 µA ≤ I

10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ V

≤ 1 mA

Trimmed to Zero

MAX

0.08 0.3 0.08 1 µV/°C

0.03 0.1 0.03 0.3

IC = 10 µA813nA

MAX

40 90 40 150 pA/°C

325 300

23nA

IC = 10 µA IC = 10 µA4550nA IC = 1 mA I

= 100 µA 275 250

= 10 µA 225 200

= 1 µA 200 150

VCB = V

Leakage Current Collector-Emitter I

CES

VCE = V

, VBE = 0 3 4 nA

MAX

Leakage Current Collector-Collector I

VCC = V

MAX

34nA

Leakage Current

ELECTRICAL CHARACTERISTICS

(VCB = 15 V, –558C ≤ TA ≤ +1258C, unless otherwise noted.)

MAT02A

Parameter Symbol Conditions Min Typ Max Units

Offset Voltage V Average Offset

Voltage Drift TCV Input Offset Current I

Input Offset

Current Drift TCI Input Bias Current I Current Gain h

Collector-Base I

CBO

VCB = 0 80 µV 1 µA ≤ I

≤ 1 mA

10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ V V

Trimmed to Zero

MAX

0.08 0.3 µV/°C

0.03 0.1 µV/°C

IC = 10 µA9nA

MAX

40 90 pA/°C

275

IC = 10 µA IC = 10 µA60nA IC = 1 mA I

= 100 µA 225

= 10 µA 125

= 1 µA 150

VCB = V

Leakage Current TA = 125°C15nA Collector-Emitter I

CES

Leakage Current T Collector-Collector I

VCE = V

= 125°C50nA

VCC = V

MAX

, VBE = 0

Leakage Current TA = 125°C30nA

NOTES

Measured at IC = 10 µA and guaranteed by design over the specified range of IC.

Guaranteed by VOS test (TCVOS ≅

The initial zero offset voltage is established by adjusting the ratio of IC1 to IC2 at TA = 25°C. This ratio must be held to 0.003% over

the entire temperature range. Measurements are taken at the temperature extremes and 25°C.

Guaranteed by design.

Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to V

Specifications subject to change without notice.

for VOS ! VBE) T = 298°K for TA = 25°C.

at the indicated collector current.

MAX

REV. C

–3–

MAT02 W AFER TEST LIMITS

Parameter Symbol Conditions Limits Units

Breakdown Voltage BV Offset Voltage V Input Offset Current I Input Bias Current I Current Gain h

Current Gain Match ∆h Offset Voltage ∆V

Change vs. V

Offset Voltage Change ∆VOS/∆I

vs. Collector Current 10 µA ≤ I Bulk Resistance r Collector Saturation Voltage V

(@ 258C for VCB = 15 V and IC = 10 mA, unless otherwise noted.)

CEO

OS OS B

/∆V

CE (SAT)

10 µA ≤ IC ≤ 1 mA VCB = 0 V 34 nA max

IC = 1 mA, VCB = 0 V 400 min I

= 10 µA, VCB = 0 V 300

10 µA ≤ IC ≤ 1 mA, VCB = 0 V 4 % max

0 V ≤ VCB ≤ 40 V 50 µV max 10 µA ≤ IC ≤ 1 mA

VCB = 0 50 µV max

≤ 1 mA

100 µA ≤ IC ≤ 10 mA 0.5 Ω max IC = 1 mA 0.2 V max

MAT02N

40 V min 150 µV max

1.2 nA max

IB = 100 µA

NOTES

Measured at lC = 10 µA and guaranteed by design over the specified range of IC.

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS

(VCB = 15 V, IC = 10 mA, TA = +258C, unless otherwise noted.)

MAT02N

Parameter Symbol Conditions Limits Units

Average Offset TCV

Voltage Drift 0 ≤ V

Average Offset TCI

10 µA ≤ IC ≤ 1 mA 0.08 µV/°C

≤ V

MAX

IC = 10 µA 40 pA/°C

Current Drift

Gain-Bandwidth f

VCE = 10 V, IC = 10 mA 200 MHz

Product

Offset Current Change vs. V

∆IOS/∆V

0 ≤ VCB ≤ 40 V 70 pA/V

DICE CHARACTERISTICS

1. COLLECTOR (1)

2. BASE (1)

3. EMITTER (1)

4. COLLECTOR (2)

5. BASE (2)

6. EMITTER (2)

7. SUBSTRATE

Die Size 0.061 × 0.057 inch, 3,477 sq. mils

(1.549

1.448 mm, 224 sq. mm)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the MAT02 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. C

MAT02

Figure 1. Current Gain vs. Collector Current

Figure 4. Base-Emitter-On Voltage vs. Collector Current

Figure 2. Current Gain vs. Temperature

Figure 5. Small Signal Input Resistance vs. Collector Current

Figure 3. Gain Bandwidth vs. Collector Current

Figure 6. Small-Signal Output Conductance vs. Collector Current

Figure 7. Saturation Voltage vs. Collector Current

REV. C

Figure 8. Noise Voltage Density vs. Frequency

–5–

Figure 9. Noise Voltage Density vs. Collector Current

MAT02

Figure 10. Noise Current Density vs. Frequency

Figure 13. Collector-to-Collector Leakage vs. Temperature

Figure 11. Total Noise vs. Collective Current

Figure 14. Collector-to-Collector Capacitance vs. Collector-to Substrate Voltage

Figure 12. Collector-to-Base Leakage vs. Temperature

Figure 15. Collector-Base Capacitance vs. Reverse Bias Voltage

Figure 16. Collector-to-Collector Capacitance vs. Reverse Bias Voltage

Figure 17. Emitter-Base Capacitance vs. Reverse Bias Voltage

–6–

REV. C

MAT02

Figure 18. Log Conformance Test Circuit

LOG CONFORMANCE TESTING

The log conformance of the MAT02 is tested using the circuit shown above. The circuit employs a dual transdiode logarithmic converter operating at a fixed ratio of collector currents that are swept over a 10:1 range. The output of each transdiode converter is the V is the product of the collector current and r resistance. The difference of the V

of the transistor plus an error term which

is amplified at a gain of

, the bulk emitter

×100 by the AMP01 instrumentation amplifier. The differential emitter-base voltage (∆V

) consists of a temperature-

dependent dc level plus an ac error voltage which is the deviation from true log conformity as the collector currents vary.

The output of the transdiode logarithmic converter comes from the idealized intrinsic transistor equation (for silicon):

where (1)

-23

J/°K)

-19

°C)

k = Boltzmann’s Constant (1.38062 × 10 q = Unit Electron Charge (1.60219 × 10 T = Absolute Temperature, °K (= °C + 273.2)

= Extrapolated Current for VBE→0

= Collector Current

An error term must be added to this equation to allow for the bulk resistance (r

) of the transistor. Error due to the op amp

input current is limited by use of the OP15 BiFET-input op amp. The resulting AMP01 input is:

∆

VBE =

+ IC1 r

BE1

– IC2 r

BE2

(2)

A ramp function which sweeps from 1 V to 10 V is converted by the op amps to a collector current ramp through each transistor. Because I

is made equal to 10 IC2, and assuming TA = 25°C,

the previous equation becomes:

∆

VBE = 59 mV + 0.9 IC1 rBE (∆rBE ~ 0)

As viewed on an oscilloscope, the change in ∆V change in I

is then displayed as shown below:

for a 10:1

REV. C

–7–

MAT02

With the oscilloscope ac coupled, the temperature dependent term becomes a dc offset and the trace represents the deviation from true log conformity. The bulk resistance can be calculated from the voltage deviation ∆V

and the change in collector cur-

rent (9 mA):

This procedure finds r provide the r R

= R2.

for Side B. Differential rBE is found by making

∆V

9mA

for Side A. Switching R1 and R2 will

100

(3)

APPLICATIONS: NONLINEAR FUNCTIONS

MULTIPLIER/DIVIDER CIRCUIT

The excellent log conformity of the MAT02 over a very wide range of collector current makes it ideal for use in log-antilog circuits. Such nonlinear functions as multiplying, dividing, squaring, and square-rooting are accurately and easily implemented with a log-antilog circuit using two MAT02 pairs (see Figure 19). The transistor circuit accepts three input currents (I

, I2, and I3) and provides an output current IO according to

= I1I2/I3. All four currents must be positive in the log-antilog

circuit, but negative input voltages can be easily accommodated

by various offsetting techniques. Protective diodes across each base-to-emitter junction would normally be needed, but these diodes are built into the MAT02. External protection diodes are therefore not needed.

For the circuit shown in Figure 19, the operational amplifiers make I

= VX/R1, I2 = VY/R2, I3 = VZ/R3, and IO = VO/RO. The

output voltage for this one-quadrant, log-antilog multiplier/divider is ideally:

R3R

VXV

R1R

If all the resistors (R V

. Resistor values of 50 kΩ to 100 kΩ are recommended

XVY/VZ

(VX, VY, VZ > 0) (4)

, R1, R2, R3) are made equal, then VO =

assuming an input range of 0.1 V to +10 V.

ERROR ANALYSIS

The base-to-emitter voltage of the MAT02 in its forward active operation is:

+ rBEIC, VCB ~ 0 (5)

The first term comes from the idealized intrinsic transistor equation previously discussed (see equation (1)).

Figure 19. One-Quadrant Multiplier/Divider

–8–

REV. C

Figure 20. Compensation of Bulk Resistance Error

Extrinsic resistive terms and the early effect cause departure from the ideal logarithmic relationship. For small V

, all of these effects can be lumped together as a total effective bulk resistance r logarithmic relationship. The r than 0.5 Ω and ∆r

. The rBEIC term causes departure from the desired

between the two sides is negligible.

term for the MAT02 is less

Returning to the multiplier/divider circuit of Figure 1 and using Equation (4):

BE1A

+ V

BE2A

– V

BE2B

–V

+ (I1 + I2 – IO – I3) rBE = 0

BE1B

If the transistor pairs are held to the same temperature, then:

1I2

I3I

S1AIS2A

S1BIS2B

+ (I1 + I2 – IO – I3) r

(6)

If all the terms on the right-hand side were zero, then we would have In (I

1 I2/I3 IO

) equal to zero which would lead directly to

the desired result:

I1I

, where I1, I2, I3, IO > 0 (7)

Note that this relationship is temperature independent. The right-hand side of Equation (6) is near zero and the output current I

will be approximately I1 I2/I3. To estimate error, define ø

as the right-hand side terms of Equation (6):

MAT02

approximately 26 mV and the error due to an rBEIC term will be r

/26 mV. Using an rBE of 0.4 Ω for the MAT02 and assum-

BEIC

ing a collector current range of up to 200 µA, then a peak error of 0.3% could be expected for an r the MAT02. Total error is dependent on the specific application configuration (multiply, divide, square, etc.) and the required dynamic range. An obvious way to reduce I duce the maximum collector current, but then op amp offsets and leakage currents become a limiting factor at low input levels. A design range of no greater than 10 µA to 1 mA is generally recommended for most nonlinear function circuits.

A powerful technique for reducing error due to I Figure 20. A small voltage equal to I sistor base. For this circuit:

V1 and ICrBE =

The error from r R

. Since the MAT02 bulk resistance is approximately 0.39 Ω,

an R

of 3.9 Ω and R2 of 10 R1 will give good error cancellation.

is cancelled if RC/R2 is made equal to rBE/

BEIC

In more complex circuits, such as the circuit in Figure 19, it may be inconvenient to apply a compensation voltage to each individual base. A better approach is to sum all compensation to the bases of Q1. The “A” side needs a base voltage of (V V

) rBE and the “B” side needs a base voltage of (VX/R1+VY/

Z/R3

) rBE. Linearity of better than ±0.1% is readily achievable with

this compensation technique. Operational amplifier offsets are another source of error. In Fig-

ure 20, the input offset voltage and input bias current will cause an error in collector current of (V amp, such as the OP07 with less than 75 µV of V less than ±3 nA, is recommended. The OP22/OP32, a programmable micropower op amp, should be considered if low power consumption or single-supply operation is needed. The value of frequency-compensating capacitor (C amp frequency response and peak collector current. Typical values for C

. . .

range from 30 pF to 300 pF.

error term when using

BEIC

error is to re-

CrBE

is applied to the tran-

CrBE

) + IB. A low offset op

OS/R1

) is dependent on the op

CrBE

and IB of

is shown in

(10)

O/RO

ø = In

For the MAT02, In (I

ø, ε

~ 1 + ø and therefore:

S1AIS2A

S1BIS2B

(I1 + I2 – IO – I3) r

) and ICrBE are very small. For small

SA/ISB

I1I

= 1 + ø

I3I

(8)

(9)

1I2

(1 – ø)

The In (I

) terms in ø cause a fixed gain error of less than

SA/ISB

±0.6% from each pair when using the MAT02, and this gain error is easily trimmed out by varying R

. The ICrBE terms are

more troublesome because they vary with signal levels and are multiplied by absolute temperature. At 25°C, kT/q is

REV. C

FOUR-QUADRANT MULTIPLIER

A simplified schematic for a four-quadrant log/antilog multiplier is shown in Figure 21. As with the previously discussed onequadrant multiplier, the circuit makes I input currents, I

and I2, are each offset in the positive direction.

= I1 I2/I3. The two

This positive offset is then subtracted out at the output stage. Assuming ideal op amps, the currents are:

I1=

,I2=

(11)

IO=

O O

,I3=

From IO = I1 I2/I3, the output voltage will be:

ROR

VXV

(12)

–9–

MAT02

Collector-current range is the key design decision. The inherently low r collector current. For input scaling of ± 10 V full-scale and using a 10 V reference, we have a collector-current range for I and I2 of:

Practical values for R 100 kΩ. Choosing an R collector-current range of approximately 39 µA to 283 µA. An R

of 108 kΩ will then make the output scale factor 1/10 and

= VXVY/10. The output, as well as both inputs, are scaled

for ±10 V full scale. Linear error for this circuit is substantially improved by the

small correction voltage applied to the base of Q1 as shown in Figure 21. Assuming an equal bulk emitter resistance for each MAT02 transistor, then the error is nulled if:

The currents are known from the previous discussion, and the relationship needed is simply:

The output voltage is attenuated by a factor of r plied to the base of Q1 to cancel the summation of voltage drops due to r nearly zero which will thereby make I rate relationship. Linearity of better than 0.1% is readily achievable with this circuit if the MAT02 pairs are carefully kept at the same temperature.

of the MAT02 allows the use of a relatively high



–10





+ I2 – I3 – IO) rBE + ρVO = 0

BEIC







and R2 would range from 50 kΩ to

terms. This will make In (I1 I2/I3 IO) more

≤I



≤











of 82 kΩ and R2 of 62 kΩ provides a

and ap-

BE/RO

= I1 I2/I3 a more accu-

(13)

(14)

MULTIFUNCTION CONVERTER

The multifunction converter circuit provides an accurate means of squaring, square rooting, and of raising ratios to arbitrary powers. The excellent log conformity of the MAT02 allows a wide range of exponents. The general transfer function is:





= VY

, VY, and VZ are input voltages and the exponent “m” has a

practical range of approximately 0.2 to 5. Inputs V









(15)

and VY are often taken from a fixed reference voltage. With a REF01 providing a precision +10 V to both V

and VY, the transfer func-

tion would simplify to:





= 10









(16)

As with the multiplier/divider circuits, assume that the transistor pairs have excellent matching and are at the same temperature. The In I

will then be zero. In the circuit of Figure 22, the

SA/ISB

voltage drops across the base-emitter junctions of Q1 provide:

RB+ KR

is VZ/R1 and IX is VX/R1. Similarly, the relationship for Q2 is:

RB+ 1– K

()

is VO/RO and IY is VY/R1. These equations for Q1 and Q2 can

VA=

(17)

(18)

then be combined.

Figure 21. Four-Quadrant Multiplier

RB+ KR

RB+ 1– K

()

= In

(19)

–10–

REV. C

MAT02

Substituting in the voltage relationships and simplifying leads to:





, where









(20)

m =

RB+ KR

RB+ 1– K

()

The factor “K” is a potentiometer position and varies from zero to 1.0, so “m” ranges from R Practical values are 125 Ω for R

/(RA + RB) to (RB + RA)/RB.

and 500 Ω for RA; these val-

ues will provide an adjustment range of 0.2 to 5.0. A value of 100 kΩ is recommended for the R

resistors assuming a full-

scale input range of 10 V. As with the one-quadrant multiplier/ divider circuit previously discussed, the V

, VY, and VZ inputs

must all be positive. The op amps should have the lowest possible input offsets. The

OP07 is recommended for most applications, although such programmable micropower op amps as the OP22 or OP32 offer advantages in low-power or single-supply circuits. The micropower op amps also have very low input bias-current drift, an important advantage in log/antilog circuits. External offset nulling may be needed, particularly for applications requiring a wide dynamic range. Frequency compensating capacitors, on the order of 50 pF, may be required for A A

is likely to need a larger capacitor, typically 0.0047 µF, to as-

and A3. Amplifier

sure stability.

Accuracy is limited at the higher input levels by bulk emitter resistance, but this is much lower for the MAT02 than for other transistor pairs. Accuracy at the lower signal levels primarily depends on the op amp offsets. Accuracies of better than 1% are readily achievable with this circuit configuration and can be better than ±0.1% over a limited operating range.

FAST LOGARITHMIC AMPLIFIER

The circuit of Figure 23 is a modification of a standard logarithmic amplifier configuration. Running the MAT02 at 2.5 mA per side (full-scale) allows a fast response with wide dynamic range. The circuit has a 7 decade current range, a 5 decade voltage range, and is capable of 2.5 µs settling time to 1% with a 1 V to 10 V step.

The output follows the equation:

R3+ R

REF

(21)

The output is inverted with respect to the input, and is nominally –1 V/decade using the component values indicated.

LOW-NOISE 31000 AMPLIFIER

The MAT02 noise voltage is exceptionally low, only 1 nV/√Hz at 10 Hz when operated over a collector-current range of 1 mA to 4 mA. A single-ended ×1000 amplifier that takes advantage of this low MAT02 noise level is shown in Figure 24. In addition to low noise, the amplifier has very low drift and high CMRR. An OP32 programmable low-power op amp is used for the second stage to obtain good speed with minimal power consumption. Small-signal bandwidth is 1 MHz, slew rate is 2.4 V/µs, and total supply current is approximately 2.8 mA.

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Figure 22. Multifunction Converter

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MAT02

Transistors Q2 and Q3 form a 2 mA current source (0.65 V/ 330 Ω ~ 2 mA). OP32 inputs are 3 V below the positive supply voltage (R

Each collector of Q1 operates at 1 mA. The

LIC

~ 3 V). The OP32’s low input offset current, typically less than 1 nA, and low offset voltage of 1 mV cause negligible error when referred to the amplifier input. Input stage gain is g which is approximately 100 when operating at I R

of 3 kΩ. Since the OP32 has a minimum open-loop gain of

of 1 mA with

mRL

500,000, total open-loop gain for the composite amplifier is over 50 million. Even at closed-loop gain of 1000, the gain error due to finite open-loop gain will be negligible. The OP32 features excellent symmetry of slew-rate and very linear gain. Signal distortion is minimal.

Frequency compensation is very easy with this circuit; just vary the set-resistor R

for the desired frequency response.

Gain-bandwidth of the OP32 varies directly with the supply

current. A set resistor of 549 kΩ was found to provide the best step response for this circuit. The resultant supply current is found from:

V +

–V–

–2V

()

SET

,ISY=15I

of 549 kΩ, is ap-

SET

(22)

The I

SET

()

, using ±15 V supplies and an R

SET

proximately 52 µA which will result in supply current of 784 µA. Dynamic range of this amplifier is excellent; the OP32 has an

output voltage swing of ±14 V with a ±15 V supply. Input characteristics are outstanding. The MAT02F has offset

voltage of less than 150 µV at 25°C and a maximum offset drift of 1 µV/°C. Nulling the offset will further reduce offset drift. This can be accomplished by slightly unbalancing the collector load resistors. This adjustment will reduce the drift to less than

0.1 µV/°C. Input bias current is relatively low due to the high current gain

of the MAT02. The minimum β of 400 at 1 mA for the MAT02F implies an input bias current of approximately 2.5 µA. This circuit should be used with signals having relatively low source impedance. A high source impedance will degrade offset and noise performance.

This circuit configuration provides exceptionally low input noise voltage and low drift. Noise can be reduced even further by raising the collector currents from 1 mA to 3 mA, but power consumption is then increased.

000000000

Figure 23. Fast Logarithmic Amplifier

0.185 (4.70)

0.165 (4.19)

0.370 (9.40)

0.335 (8.51)

0.305 (7.75)

0.040 (1.02) MAX

0.045 (1.14)

0.010 (0.25)

OUTLINE DIMENSION

Dimensions shown in inches and (mm).

6-Lead Metal Can

(TO-78)

REFERENCE PLANE

0.750 (19.05)

0.500 (12.70)

0.250 (6. 35) MIN

0.050 (1.27) MAX

0.019 (0.48)

0.016 (0.41)

0.021 (0.53)

0.016 (0.41)

BASE & SEATING PLANE

0.200 (5.08)

BSC

0.100 (2.54)

BSC

0.100 (2.54) BSC

0.034 (0.86)

0.027 (0.69)

0.160 (4.06)

0.110 (2.79)

45° BSC

0.045 (1.14)

0.027 (0.69)

PRINTED IN U.S.A.

Figure 24. Low-Noise, Single-Ended X1000 Amplifier

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Datasheet MAT02 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual