ANALOG DEVICES LTC 3411 EMS Datasheet

FEATURES

LTC3411

1.25A, 4MHz, Synchronous

Step-Down DC/DC Converter

U

DESCRIPTIO

■

Small 10-Lead MSOP or DFN Package

■

Uses Tiny Capacitors and Inductor

■

High Frequency Operation: Up to 4MHz

■

High Switch Current: 1.6A

■

Low R

■

High Efficiency: Up to 95%

■

Stable with Ceramic Capacitors

■

Current Mode Operation for Excellent Line

Internal Switches: 0.110Ω

DS(ON)

and Load Transient Response

■

Short-Circuit Protected

■

Low Dropout Operation: 100% Duty Cycle

■

Low Shutdown Current: IQ ≤ 1µA

■

Low Quiescent Current: 60µA

■

Output Voltages from 0.8V to 5V

■

Selectable Burst Mode® Operation

■

Sychronizable to External Clock

U

APPLICATIO S

■

Notebook Computers

■

Digital Cameras

■

Cellular Phones

■

Handheld Instruments

■

Board Mounted Power Supplies

The LTC®3411 is a constant frequency, synchronous,
step- down DC/DC converter. Intended for medium power
applications, it operates from a 2.63V to 5.5V input voltage
range and has a user configurable operating frequency up
to 4MHz, allowing the use of tiny, low cost capacitors and
inductors 2mm or less in height. The output voltage is
adjustable from 0.8V to 5V. Internal sychronous 0.11Ω
power switches with 1.6A peak current ratings provide
high efficiency. The LTC3411’s current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.

The LTC3411 can be configured for automatic power
saving Burst Mode operation to reduce gate charge losses
when the load current drops below the level required for
continuous operation. For reduced noise and RF interfer­ence, the SYNC/MODE pin can be configured to skip
pulses or provide forced continuous operation.

To further maximize battery life, the P-channel MOSFET is
turned on continuously in dropout (100% duty cycle) with
a low quiescent current of 60µA. In shutdown, the device
draws <1µA.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a registered trademark of Linear Technology Corporation.

TYPICAL APPLICATIO

2.63V TO 5.5V

SYNC/MODEV

IN

PGOOD

LTC3411

I

TH

SHDN/R

13k

1000pF

NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)

324k

T

Figure 1. Step-Down 2.5V/1.25A Regulator

PV

IN

SV

IN

SW

V

FB

PGNDSGND

U

V

IN

L1

2.2µH

887k

412k

3411 F01

C1
22µF

V

2.5V/1.25A

C2
22µF

OUT

EFFICIENCY (%)

Efficiency vs Load Current

100

95

90

85

80

VIN = 3.3V

= 2.5V

V

OUT

75

f

= 1MHz

O

Burst Mode OPERATION

70

1 100 1000

10

LOAD CURRENT (mA)

3411 TA01

3411f

1

LTC3411

WW

W

ABSOLUTE AXI U RATI GS

PVIN, SV

Voltages .....................................–0.3V to 6V

IN

U

(Note 1)

VFB, ITH, SHDN/RT Voltages .......... –0.3V to (VIN + 0.3V)

SYNC/MODE Voltage .................... –0.3V to (VIN + 0.3V)

SW Voltage ................................... –0.3V to (VIN + 0.3V)

PGOOD Voltage ...........................................–0.3V to 6V

Operating Ambient Temperature Range

(Note 2) .................................................. – 40°C to 85°C

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

SHDN/R

SYNC/MODE

1

T

2
3

SGND

4

SW

5

PGND

10-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

(EXPOSED PAD MUST BE SOLDERED TO PCB)

DD PACKAGE

= 125°C, θJA = 43°C/W, θJC = 3°C/W

10

9
8
7
6

I

TH

V

FB

PGOOD
SV

IN

PV

IN

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ORDER PART

NUMBER

LTC3411EDD

DD PART MARKING

LADT

Junction Temperature (Notes 5, 8) ....................... 125°C

Storage Temperature Range

DD Package ...................................... –65°C to 125°C

MS Package .................................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ORDER PART

TOP VIEW

1

SHDN/R

SYNC/MODE

T

2

SGND

3

SW

4

PGND

5

MS PACKAGE

10-LEAD PLASTIC MSOP

T

= 125°C, θJA = 120°C/W, θJC = 10°C/W

JMAX

10
9
8
7
6

I

TH

V

FB

PGOOD
SV

IN

PV

IN

NUMBER

LTC3411EMS

MS PART MARKING

LTQT

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

FB

V

FB

∆V

LINEREG

∆V

LOADREG

g

m(EA)

I

S

V

SHDN/RT

f

OSC

f

SYNC

I

LIM

R

DS(ON)

I

SW(LKG)

V

UVLO

Operating Voltage Range 2.625 5.5 V
Feedback Pin Input Current (Note 3) ±0.1 µA
Feedback Voltage (Note 3) ● 0.784 0.8 0.816 V
Reference Voltage Line Regulation VIN = 2.7V to 5V 0.04 0.2 %/V
Output Voltage Load Regulation ITH = 0.36, (Note 3) ● 0.02 0.2 %

I

= 0.84, (Note 3) ● –0.02 –0.2 %

TH

Error Amplifier Transconductance ITH Pin Load = ±5µA (Note 3) 800 µS
Input DC Supply Current (Note 4)

Active Mode V
Sleep Mode V
Shutdown V

= 0.75V, SYNC/MODE = 3.3V 240 350 µA

FB
SYNC/MODE
SHDN/RT

= 3.3V, VFB = 1V 62 100 µA

= 3.3V 0.1 1 µA

Shutdown Threshold High VIN – 0.6 VIN – 0.4 V
Active Oscillator Resistor 324k 1M Ω

Oscillator Frequency RT = 324k 0.85 1 1.15 MHz

(Note 7) 4 MHz
Synchronization Frequency (Note 7) 0.4 4 MHz
Peak Switch Current Limit ITH = 1.3 1.6 2 A
Top Switch On-Resistance (Note 6) VIN = 3.3V 0.11 0.15 Ω
Bottom Switch On-Resistance (Note 6) VIN = 3.3V 0.11 0.15 Ω
Switch Leakage Current VIN = 6V, V

= 0V, VFB = 0V 0.01 1 µA

ITH/RUN

Undervoltage Lockout Threshold VIN Ramping Down 2.375 2.5 2.625 V

3411f

2

LTC3411

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PGOOD Power Good Threshold VFB Ramping Up, SHDN/RT = 1V 6.8 %

R

PGOOD

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC3411E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating ambient
termperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: The LTC3411 is tested in a feedback loop which servos V
midpoint for the error amplifier (V

Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.

Power Good Pull-Down On-Resistance 118 200 Ω

= 0.6V).

ITH

The ● denotes the specifications which apply over the full operating

V

Ramping Down, SHDN/RT = 1V –7.6 %

FB

is calculated from the ambient TA and power dissipation P

J

LTC3411EDD: TJ = TA + (PD • 43°C/W)
LTC3411EMS: T

= TA + (PD • 120°C/W)

J

to the

FB

Note 5: T
according to the following formula:

Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.

Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).

Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

D

UUU

PI FU CTIO S

SHDN/RT (Pin 1): Combination Shutdown and Timing
Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing this
pin to SVIN causes the device to be shut down. In shut­down all functions are disabled.

SYNC/MODE (Pin 2): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the op­eration of the device. When tied to SVIN or SGND, Burst
Mode operation or pulse skipping mode is selected, re­spectively. If this pin is held at half of SVIN, the forced
continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to this
pin. When synchronized to an external clock pulse skip
mode is selected.

SGND (Pin 3): The Signal Ground Pin. All small signal
components and compensation components should be
connected to this ground (see Board Layout Consider­ations).

SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PVIN to PGND.

PGND (Pin 5): Main Power Ground Pin. Connect to the
(–) terminal of C

, and (–) terminal of CIN.

OUT

PVIN (Pin 6): Main Supply Pin. Must be closely decoupled
to PGND.

SVIN (Pin 7): The Signal Power Pin. All active circuitry is
powered from this pin. Must be closely decoupled to
SGND. SVIN must be greater than or equal to PVIN.

PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within ±7.5% of regulation.

VFB (Pin 9): Receives the feedback voltage from the
external resistive divider across the output. Nominal volt­age for this pin is 0.8V.

ITH (Pin 10): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.

3411f

3

LTC3411

UUU

PI FU CTIO S

NOMINAL (V) ABSOLUTE MAX (V)

PIN NAME DESCRIPTION MIN TYP MAX MIN MAX

1 SHDN/R
2 SYNC/MODE Mode Select/Sychronization Pin 0 SV

Shutdown/Timing Resistor –0.3 0.8 SV

T

IN
IN

–0.3 SVIN + 0.3

–0.3 SVIN + 0.3
3 SGND Signal Ground 0
4 SW Switch Node 0 PV

IN

–0.3 PVIN + 0.3
5 PGND Main Power Ground 0
6PVINMain Power Supply –0.3 5.5 – 0.3 SVIN + 0.3
7SVINSignal Power Supply 2.5 5.5 –0.3 6
8 PGOOD Power Good Pin 0 SV

IN

–0.3 6
9VFBOutput Feedback Pin 0 0.8 1.0 – 0.3 SVIN + 0.3
10 I

TH

Error Amplifier Compensation and Run Pin 0 1.5 –0.3 SVIN + 0.3

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Burst Mode Operation Pulse Skipping Mode Forced Continuous Mode

V

OUT

10mV/

DIV

I

L1

100mA/

DIV

VIN = 3.3V 2µs/DIV 3411 G01.eps
V

= 2.5V

OUT

= 50mA

I

LOAD

CIRCUIT OF FIGURE 7

Efficiency vs Load Current

100

Burst Mode

OPERATION

95

90

85

PULSE SKIP FORCED CONTINUOUS

80

75

EFFICIENCY (%)

70

65

60

1 100 1000 10000

10

LOAD CURRENT (mA)

VIN = 3.3V

= 2.5V

V

OUT

CIRCUIT OF FIGURE 7

3411 G04

V

OUT

10mV/

DIV

I

L1

100mA/

DIV

= 3.3V 2µs/DIV 3411 G02.eps

V

IN

V

= 2.5V

OUT

= 50mA

I

LOAD

CIRCUIT OF FIGURE 7

Efficiency vs V

100

I

OUT

95

90

I

OUT

85

80

75

EFFICIENCY (%)

70

65

V

= 2.5V

OUT

CIRCUIT OF FIGURE 7

60

2.5 3.5 4.5 5.5

IN

= 400mA

= 1.25A

VIN (V)

3411 G05

V

OUT

10mV/

DIV

I

L1

100mA/

DIV

VIN = 3.3V 2µs/DIV 3411 G03.eps
V

= 2.5V

OUT

= 50mA

I

LOAD

CIRCUIT OF FIGURE 7

Load Step

V

OUT

100mV/

DIV

I

L1

0.5mA/
DIV

VIN = 3.3V 40µs/DIV 3411 G06.eps
V

= 2.5V

OUT

I

= 0.25mA TO 1.25A

LOAD

CIRCUIT OF FIGURE 7

4

3411f

2 3 4 5 6

VIN (V)

FREQUENCY VARIATION (%)

10

8
6
4
2

0
–2
–4
–6
–8

–10

3411 G09

V

OUT

= 1.8V

I

OUT

= 1.25A

T

A

= 25°C

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3411

Load Regulation Line Regulation Frequency vs V

0.4

0.3

0.2
PULSE SKIP

0.1

0

CONTINUOUS

–0.1

ERROR (%)

OUT

–0.2

V

–0.3

–0.4

–0.5

1 10 100 1000 10000

FORCED

LOAD CURRENT (mA)

Burst Mode
OPERATION

VIN = 3.3V
V

= 2.5V

OUT

3411 G07

0.50
V

= 1.8V

OUT

0.45

= 25°C

T

A

0.40

0.35

0.30

0.25

ERROR (%)

0.20

OUT

V

0.15

0.10

0.05

0

2 3 4 5 6

I

OUT

= 1.25A

I

VIN (V)

OUT

= 400mA

3411 G08

Frequency Variation
vs Temperature

10

8
6
4
2

0
–2
–4

REFERENCE VARIATION (%)

–6
–8

–10

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

3411 G10

Efficiency vs Frequency

100

95

EFFICIENCY (%)

90

85

0

12

FREQUENCY (MHz)

VIN = 3.3V

= 2.5V

V

OUT

= 500mA

I

OUT

T

= 25°C

A

34

3411 G11

R

120

TA = 25°C

115

110

(mΩ)

105

DS(ON)

R

100

95

90

2.5 3 3.5 4 4.5 5 5.5 6

DS(ON)

vs V

IN

SYNCHRONOUS SWITCH

MAIN SWITCH

VIN (V)

IN

3411 G12

3411f

5

LTC3411

BLOCK DIAGRA

W

V

PGOOD

IN

VOLTAGE

REFERENCE

SGND

SV

7

0.8V

+

9

FB

0.74V

–

ERROR
AMPLIFIER

+

–

I

TH

10

3

I

TH

LIMIT

BCLAMP

B

–

+

V

B

BURST
COMPARATOR
HYSTERESIS = 80mV

OSCILLATOR

PMOS CURRENT
COMPARATOR

+

–

SLOPE

COMPENSATION

PV

IN

6

4

SW

+

0.86V

–

8

LOGIC

NMOS

COMPARATOR

+

–

1

SHDN/R

–

5

REVERSE

COMPARATOR

2

SYNC/MODE

T

+

PGND

3411 BD

6

3411f

OPERATIO

LTC3411

U

The LTC3411 uses a constant frequency, current mode
architecture. The operating frequency is determined by
the value of the RT resistor or can be synchronized to an
external oscillator. To suit a variety of applications, the
selectable Mode pin, allows the user to trade-off noise for
efficiency.

The output voltage is set by an external divider returned to
the VFB pin. An error amplfier compares the divided output
voltage with a reference voltage of 0.8V and adjusts the
peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the PGOOD output low
if the output voltage is not within ±7.5%.

Main Control Loop

During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage is below the the reference voltage.
The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor flows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.

The peak inductor current is controlled by the voltage on
the ITH pin, which is the output of the error amplifier.This
amplifier compares the VFB pin to the 0.8V reference.
When the load current increases, the VFB voltage de­creases slightly below the reference. This decrease causes
the error amplifier to increase the ITH voltage until the
average inductor current matches the new load current.

The main control loop is shut down by pulling the SHDN/R
pin to SVIN. A digital soft-start is enabled after shutdown,
which will slowly ramp the peak inductor current up over
1024 clock cycles or until the output reaches regulation,
whichever is first. Soft-start can be lengthened by ramping
the voltage on the ITH pin (see Applications Information
section).

Low Current Operation

Three modes are available to control the operation of the
LTC3411 at low currents. All three modes automatically
switch from continuous operation to to the selected mode
when the load current is low.

T

To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3411
automatically switches into Burst Mode operation in which
the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses of
the power MOSFETs are minimized. The main control loop
is interrupted when the output voltage reaches the desired
regulated value. The hysteretic voltage comparator B trips
when ITH is below 0.24V, shutting off the switch and
reducing the power. The output capacitor and the inductor
supply the power to the load until ITH/RUN exceeds 0.31V,
turning on the switch and the main control loop which
starts another cycle.

For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3411
continues to switch at a constant frequency down to very
low currents, where it will eventually begin skipping pulses.

Finally, in forced continuous mode, the inductor current is
constantly cycled which creates a fixed output voltage
ripple at all output current levels. This feature is desirable
in telecommunications since the noise is at a constant
frequency and is thus easy to filter out. Another advantage
of this mode is that the regulator is capable of both
sourcing current into a load and sinking some current
from the output.

Dropout Operation

When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.

Low Supply Operation

The LTC3411 incorporates an undervoltage lockout circuit
which shuts down the part when the input voltage drops
below about 2.5V to prevent unstable operation.

3411f

7

LTC3411

RT (kΩ)

0

0

FREQUENCY (MHz)

0.5

1.5

2.0

2.5

1000

4.5
T

A

= 25°C

3411 F02

1.0

500 1500

3.0

3.5

4.0

U

WUU

APPLICATIO S I FOR ATIO

A general LTC3411 application circuit is shown in
Figure␣ 5. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L1. Once L1 is chosen, CIN and C
selected.

Operating Frequency

Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.

The operating frequency, fO, of the LTC3411 is determined
by an external resistor that is connected between the R
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator and can be calculated
by using the following equation:

OUT

can be

T

A reasonable starting point for setting ripple current is
∆IL␣ =␣ 0.3 • I

, where I

LIM

is the peak switch current limit.

LIM

The largest ripple current ∆IL occurs at the maximum
input voltage. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:

V

OUT

L

=

fIVV

∆

•

OL



−

1

•





IN MAX



OUT





()

The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation begins
when the peak inductor current falls below a level set by the
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower induc­tance values will cause the burst frequency to increase.

or can be selected using Figure 2.
The maximum usable operating frequency is limited by the

minimum on-time and the duty cycle. This can be calcu­lated as:

The minimum frequency is limited by leakage and noise
coupling due to the large resistance of RT.

Inductor Selection

Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ∆IL decreases with
higher inductance and increases with higher VIN or V

Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.

8

−

.

108

()Ω()

/ V

OUT

V

OUT

V

IN

IN(MAX)






OUT

•

O

•1

11






Rf

=

978 10

.•

TO

f

≈ 6.67 • (V

O(MAX)

V

∆= −

I

L

fL

) (MHz)

OUT

Figure 2. Frequency vs R

T

Inductor Core Selection

Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-

:

oid or shielded pot cores in ferrite or permalloy materials
are small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc­tor to use often depends more on the price vs size require­ments and any radiated field/EMI requirements than on
what the LTC3411 requires to operate. Table 1 shows some

3411f

LTC3411

U

WUU

APPLICATIO S I FOR ATIO

typical surface mount inductors that work well in LTC3411
applications.

Table 1. Representative Surface Mount Inductors

MANU- MAX DC
FACTURER PART NUMBER VALUE CURRENT DCR HEIGHT

Toko A914BYW-2R2M-D52LC 2.2µH 2.05A 49mΩ 2mm
Toko A915AY-2ROM-D53LC 2µH 3.3A 22mΩ 3mm
Coilcraft D01608C-222 2.2µH 2.3A 70mΩ 3mm
Coilcraft LP01704-222M 2.2µH 2.4A 120mΩ 1mm
Sumida CDRH4D282R2 2.2µH 2.04A 23mΩ 3mm
Sumida CDC5D232R2 2.2µH 2.16A 30mΩ 2.5mm
Taiyo Yuden N06DB2R2M 2.2µH 3.2A 29mΩ 3.2mm
Taiyo Yuden N05DB2R2M 2.2µH 2.9A 32mΩ 2.8mm
Murata LQN6C2R2M04 2.2µH 3.2A 24mΩ 5mm

Catch Diode Selection

Although unnecessary in most applications, a small im­provement in efficiency can be obtained in a few applica­tions by including the optional diode D1 shown in Figure␣ 5,
which conducts when the synchronous switch is off.
When using Burst Mode operation or pulse skip mode, the
synchronous switch is turned off at a low current and the
remaining current will be carried by the optional diode. It
is important to adequately specify the diode peak current
and average power dissipation so as not to exceed the
diode ratings. The main problem with Schottky diodes is
that their parasitic capacitance reduces the efficiency,
usually negating the possible benefits for LTC3411 cir­cuits. Another problem that a Schottky diode can intro­duce is higher leakage current at high temperatures, which
could reduce the low current efficiency.

Remember to keep lead lengths short and observe proper
grounding (see Board Layout Considerations) to avoid
ringing and increased dissipation when using a catch
diode.

Input Capacitor (CIN) Selection

In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately V
VIN. To prevent large voltage transients, a low equivalent

OUT

/

series resistance (ESR) input capacitor sized for the maxi­mum RMS current must be used. The maximum RMS
capacitor current is given by:

VVV

II

≈

RMS MAX

OUT IN OUT

where the maximum average output current I

−()

V

IN

MAX

equals
the peak current minus half the peak-to-peak ripple cur­rent, I

This formula has a maximum at VIN = 2V
I

RMS

= I

MAX

= I

OUT

– ∆IL/2.

LIM

/2. This simple worst case is commonly used

OUT

, where

to design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours life­time. This makes it advisable to further derate the capaci­tor, or choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recom-
mended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.

Output Capacitor (C

The selection of C

) Selection

OUT

is driven by the required ESR to

OUT

minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (∆V

) is deter-

OUT

mined by:



∆≈∆ +

V I ESR

OUT L




8

fC

O OUT

where f = operating frequency, C



1




= output capacitance

OUT

and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3 • I

the output ripple

LIM

will be less than 100mV at maximum VIN and fO = 1MHz
with:

ESRC

< 150mΩ

OUT

3411f

9

LTC3411

C

I

fV

OUT

OUT

O DROOP

≈∆25.

•

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APPLICATIO S I FOR ATIO

Once the ESR requirements for C
RMS current rating generally far exceeds the I
requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Alumi­num electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface mount tantalums, avalable in case heights rang­ing from 2mm to 4mm. Aluminum electrolytic capacitors
have a significantly larger ESR, and is often used in
extremely cost-sensitive applications provided that con­sideration is given to ripple current ratings and long term
reliability. Ceramic capacitors have the lowest ESR and
cost but also have the lowest capacitance density, a high
voltage and temperature coefficient and exhibit audible
piezoelectric effects. In addition, the high Q of ceramic
capacitors along with trace inductance can lead to signifi­cant ringing. Other capacitor types include the Panasonic
specialty polymer (SP) capacitors.

In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3411 in parallel with the
main capacitors for high frequency decoupling.

have been met, the

OUT

RIPPLE(P-P)

pacitors remain capacitive to beyond 300kHz and ususally
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramic capacitors is available from Taiyo Yuden, TDK and
Murata.

Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.

Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation compo­nents and the output capacitor size. Typically, 3 to 4 cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
V
first cycle. Thus, a good place to start is with the output
capacitor size of approximately:

, is usually about 2 to 3 times the linear drop of the

DROOP

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt­ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generates a loop “zero” at 5kHz to 50kHz that is instrumen­tal in giving acceptable loop phase margin. Ceramic ca-

10

More capacitance may be required depending on the duty
cycle and load step requirements.

In most applications, the input capacitor is merely re­quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.

3411f

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APPLICATIO S I FOR ATIO

Setting the Output Voltage

The LTC3411 develops a 0.8V reference voltage between
the feedback pin, VFB, and the signal ground as shown in
Figure 5. The output voltage is set by a resistive divider
according to the following formula:

R

2

VV

≈+

OUT



08 1

.





Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.

To improve the frequency response, a feed-forward ca­pacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.

Shutdown and Soft-Start

The SHDN/RT pin is a dual purpose pin that sets the
oscillator frequency and provides a means to shut down
the LTC3411. This pin can be interfaced with control logic
in several ways, as shown in Figure 3(a) and Figure 3(b).

The ITH pin is primarily for loop compensation, but it can
also be used to increase the soft-start time. Soft start
reduces surge currents from VIN by gradually increasing






R

1

the internal peak inductor current. Power supply sequenc­ing can also be accomplished using this pin. The LTC3411
has an internal digital soft-start which steps up a clamp on
ITH over 1024 clock cycles, as can be seen in Figure 4.

The soft-start time can be increased by ramping the
voltage on ITH during start-up as shown in Figure 3(c). As
the voltage on ITH ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.

Mode Selection and Frequency Synchronization

The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect­ing this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected to
ground, pulse skipping operation is selected which pro­vides the lowest output voltage and current ripple at the
cost of low current efficiency. Applying a voltage within 1V
of the supplies, results in forced continuous mode, which
creates a fixed output ripple and is capable of sinking some
current (about 1/2∆IL). Since the switching noise is con­stant in this mode, it is also the easiest to filter out. In many
cases, the output voltage can be simply connected to the
SYNC/MODE pin, giving the forced continuous mode,
except at startup.

SHDN/R

T

R

T

RUN

3411 F03a

RUN OR V

Figure 3. SHDN/RT Pin Interfacing and External Soft-Start

INITH

R1

D1

C1 C

(3c)

RUN

R

C

C

3411 F03c

SHDN/R

(3b)(3a)

SV

T

IN

R

1M

T

3411 F03b

V

2V/DIV

V

OUT

2V/DIV

500mA/DIV

IN

I

L

= 3.3V 200µs/DIV 3411 F04.eps

V

IN

V

= 2.5V

OUT

= 1.4Ω

R

L

Figure 4. Digital Soft-Start

3411f

11

LTC3411

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APPLICATIO S I FOR ATIO

The LTC3411 can also be synchronized to an external
clock signal by the SYNC/MODE pin. The internal oscillator
frequency should be set to 20% lower than the external
clock frequency to ensure adequate slope compensation,
since slope compensation is derived from the internal
oscillator. During synchronization, the mode is set to
pulse skipping and the top switch turn on is synchronized
to the rising edge of the external clock.

Checking Transient Response

The OPTI-LOOP compensation allows the transient re­sponse to be optimized for a wide range of loads and
output capacitors. The availability of the ITH pin not only
allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed loop re­sponse test point. The DC step, rise time and settling at this
test point truly reflects the closed loop response. Assum­ing a predominantly second order system, phase margin
and/or damping factor can be estimated using the percent­age of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin.

The ITH external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica­tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected

because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1µs
to 10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.

Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
immediately shifts by an amount equal to ∆I

LOAD

where ESR is the effective series resistance of C
∆I

also begins to charge or discharge C

LOAD

OUT

OUT

• ESR,

OUT

generat-

.

ing a feedback error signal used by the regulator to return
V

to its steady-state value. During this recovery time,

OUT

V

can be monitored for overshoot or ringing that would

OUT

indicate a stability problem.
The initial output voltage step may not be within the

bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C. If
R is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor CF can
be added to improve the high frequency response, as
shown in Figure 5. Capacitor CF provides phase lead by
creating a high frequency zero with R2 which improves the
phase margin.

12

V

2.5V

TO 5.5V

IN

SGND

PGND

+

C6

PGND

C

ITH

SGND SGND SGND SGNDGND

R6

C

IN

C8

SGND

R

C

C

C

SV

PV

IN

LTC3411

SYNC/MODE
I

TH

SGND PGND

IN

PGOOD

SW

V

SHDN/R

R5

PGOOD

V

L1

D1
OPTIONAL

FB

T

R

T

C

F

R2

R1

+

C

OUT

PGND PGND

OUT

C5

3411 F05

Figure 5. LTC3411 General Schematic

3411f

LTC3411

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The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Linear
Technology Application Note 76.

Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward V
bility does decrease due to the decreasing voltage across
the inductor. Applications that require large load step
capability near dropout should use a different topology
such as SEPIC, Zeta or single inductor, positive buck/
boost.

In some applications, a more severe transient can be
caused by switching in loads with large (>1uF) input
capacitors. The discharged input capacitors are effectively
put in parallel with C
regulator can deliver enough current to prevent this prob­lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A hot swap controller is
designed specifically for this purpose and usually incorpo­rates current limiting, short-circuit protection, and soft­starting.

, causing a rapid drop in V

OUT

, the load step capa-

OUT

OUT

. No

1) The VIN current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. VIN current results in a small (<0.1%)
loss that increases with VIN, even at no load.

2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continu­ous mode, I
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
and thus their effects will be more pronounced at higher
supply voltages.

3) I2R Losses are calculated from the DC resistances of the
internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current flowing
through inductor L but is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
follows:

RSW = (R

GATECHG

DS(ON)

= fO(QT + QB), where QT and QB are

and the duty cycle (DC) as

DS(ON)

TOP)(DC) + (R

BOT)(1 – DC)

DS(ON)

IN

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage

of input power.
Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the
losses in LTC3411 circuits: 1) LTC3411 VIN current,

2)␣ switching losses, 3) I2R losses, 4) other losses.

The R
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:

I2R losses = I

4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching fre­quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac­count for less than 2% total additional loss.

for both the top and bottom MOSFETs can be

DS(ON)

2(RSW + RL)

OUT

3411f

13

LTC3411

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APPLICATIO S I FOR ATIO

Thermal Considerations

In a majority of applications, the LTC3411 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3411 is running at high ambi­ent temperature with low supply voltage and high duty
cycles, such as in dropout, the heat dissipated may exceed
the maximum junction temperature of the part. If the
junction temperature reaches approximately 150°C, both
power switches will be turned off and the SW node will
become high impedance.

To avoid the LTC3411 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera­ture rise is given by:

T

= PD • θ

RISE

JA

assume that the actual junction temperature will not
exceed the absolute maximum junction temperature of
125°C.

Design Example

As a design example, consider using the LTC3411 in a
portable application with a Li-Ion battery. The battery
provides a VIN = 2.5V to 4.2V. The load requires a maxi­mum of 1A in active mode and 10mA in standby mode. The
output voltage is V

= 2.5V. Since the load still needs

OUT

power in standby, Burst Mode operation is selected for
good low load efficiency.

First, calculate the timing resistor:

108

−

R MHz k

=

9 78 10 1 323 8

.• .

T

11

()

.

=

Use a standard value of 324k. Next, calculate the inductor
value for about 30% ripple current at maximum VIN:

where PD is the power dissipated by the regulator and θ

JA

is the thermal resistance from the junction of the die to the
ambient temperature.

The junction temperature, TJ, is given by:

TJ = T

RISE

+ T

AMBIENT

As an example, consider the case when the LTC3411 is in
dropout at an input voltage of 3.3V with a load current of
1A. From the Typical Performance Characteristics graph
of Switch Resistance, the R

resistance of the

DS(ON)

P-channel switch is 0.11Ω. Therefore, power dissipated
by the part is:

PD = I2 • R

DS(ON)

= 110mW

The MS10 package junction-to-ambient thermal resis­tance, θJA, will be in the range of 100°C/W to 120°C/W.
Therefore, the junction temperature of the regulator oper­ating in a 70°C ambient temperature is approximately:

TJ = 0.11 • 120 + 70 = 83.2°C

Remembering that the above junction temperature is
obtained from an R
the junction temperature based on a higher R

at 25°C, we might recalculate

DS(ON)

DS(ON)

since

it increases with temperature. However, we can safely

L

MHz mA

1 510

25

.

•

V



1

•





25

.

42

.

V
V



=µ





H=−

2

Choosing the closest inductor from a vendor of 2.2µH,
results in a maximum ripple current of:

∆=

L

MHz

122

.

•.



1

•





µ

V

25

For cost reasons, a ceramic capacitor will be used. C

−

25

.

42

.

V



=I

mA

460





V

OUT

selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:

A

C

OUT

≈=µ25

MHz V

1525

1

•( %• . )

F

20.

The closest standard value is 22µF. Since the output
impedance of a Li-Ion battery is very low, CIN is typically
10µF. In noisy environments, decoupling SVIN from PV

IN

with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.

The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the

14

3411f

LTC3411

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APPLICATIO S I FOR ATIO

current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.

The compensation should be optimized for these compo­nents by examining the load step response but a good
place to start for the LTC3411 is with a 13kΩ and 1000pF
filter. The output capacitor may need to be increased
depending on the actual undershoot during a load step.

The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate
speed.

Figure 1 shows the complete schematic for this design
example.

Board Layout Considerations

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3411. These items are also illustrated graphically in
the layout diagram of Figure 6. Check the following in your
layout:

1. Does the capacitor CIN connect to the power VIN (Pin 6)
and power GND (Pin 5) as close as possible? This

capacitor provides the AC current to the internal power
MOSFETs and their drivers.

2. Are the C
C

returns current to PGND and the (–) plate of CIN.

OUT

and L1 closely connected? The (–) plate of

OUT

3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C

and a ground line terminated

OUT

near SGND (Pin 3). The feedback signal VFB should be
routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.

4. Keep sensitive components away from the SW pin. The
input capacitor CIN, the compensation capacitor CC and
C

and all the resistors R1, R2, RT, and RC should be

ITH

routed away from the SW trace and the inductor L1.

5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the SGND pin at one point which
is then connected to the PGND pin.

6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con­nected to one of the input supplies: PVIN, PGND, SVIN or
SGND.

C

IN

V

IN

C

PV

IN

SV

R5

C4

R3R1R2

BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 6. LTC3411 Layout Diagram (See Board Layout Checklist)

IN

LTC3411
PGOODPGOOD
V

FB

I

TH

C3

PGND

SW

SGND

SYNC/MODE

SHDN/R

L1

V

IN

T

BMPS

R

T

OUT

V

OUT

3411 F06

3411f

15

LTC3411

U

TYPICAL APPLICATIO S

V

IN

2.63V TO

5.5V

C1

22µF

PGND

RS1
1M

BM

FC

PS

RS2

1M

R3

13k

SGND SGND

NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)

SGND

PV

IN

SV

IN

SYNC/MODE V
I

TH

C3
1000pF

PGOOD PGOOD

LTC3411

SHDN/R

PGNDSGND

GND

SW

R5
100k

FB

T

3.3V 2.5V 1.8V

R4

R1A

324k

280k

R1B
412k

R1C
698k

L1

2.2µH

R2 887K

C4 22pF

PGND

V

OUT

1.8V/2.5V/3.3V
AT 1.25A

C2
22µF

3411 F07a

Figure 7. General Purpose Buck Regulator Using Ceramic Capacitors

Efficiency vs Load Current

100

Burst Mode

OPERATION (BM)

95

90

PULSE SKIP

85

(PS)

80

75

EFFICIENCY (%)

70

65

60

1 100 1000 10000

FORCED
CONTINUOUS (FC)

10

LOAD CURRENT (mA)

VIN = 3.3V

= 2.5V

V

OUT

= 1MHz

f

O

3411 F07b

16

3411f

U

TYPICAL APPLICATIO S

V

IN

2.63V

TO 5V

PV

100k

R1

280k

R2

887k

10pF

C1, C2: TAIYO YUDEN JMK325BJ226MM
C4: SANYO POSCAP 6TPA47M
D1: ON MBRM120L

R3

13k

C7

SV

PGOODPGOOD
V
I

TH

C3
1000pF

Single Inductor, Positive, Buck-Boost Converter

C1

22µF

IN
IN

LTC3411

FB

PGND

SW

SGND

SYNC/MODE

SHDN/R

V

T

R4
324k

L1: TOKO A915AY-3R3M (D53LC SERIES)
M1: SILICONIX Si2302DS

L1

3.3µH

IN

D1

M1

3411 TA02

C2
22µF
×2

LTC3411

V

OUT

3.3V/

C4
47µF

400mA

+

Efficiency vs Load Current

85

fO = 1MHz

80

75

70

EFFICIENCY (%)

65

60

55

10

VIN = 4V

VIN = 2.5V

VIN = 3V

VIN = 3.5V

100k 1000

LOAD CURRENT (mA)

3411 TA03

3411f

17

LTC3411

U

TYPICAL APPLICATIO S

= 2V TO 3V

V

IN

+

2
CELLS

C1

10µF

LTC3402

V

IN

SHDN

MODE/SYNC

PGOOD

R

T

49.9k

L1

4.7µH

V

GND

SW

OUT

V

D1

FB

C

All Ceramic 2-Cell to 3.3V and 1.8V Converters

V

OUT

3.3V
120mA/1A

1000pF
10pF

47k

1M

604k

C2
44µF
(2 × 22µF)

1000pF

13k

324k

SV

IN

SYNC/MODE
PGOOD

LTC3411

I

TH

SHDN/R

T

C5
22µF

PV

IN

L2

2.2µH

SW

V

PGNDSGND

887k

FB

412k

C6
22µF

V

OUT

1.8V/1.2A

0 = FIXED FREQ

1 = Burst Mode OPERATION

C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM

C5, C6: TAIYO YUDEN JMK325BJ226MM

Efficiency vs Load Current

100

95

3.3V

90

85

80

75

EFFICIENCY (%)

70

65

V

= 2.4V

IN

Burst Mode OPERATION

60

10

LOAD CURRENT (mA)

D1: ON SEMICONDUCTOR MBRM120LT3
L1: TOKO A916CY-4R7M
L2: TOKO A914BYW-2R2M (D52LC SERIES)

1.8V

100 1000 10000

3211 TA07

3411 TA06

18

3411f

PACKAGE DESCRIPTIO

U

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

0.675 ±0.05

LTC3411

R = 0.115

TYP

106

0.38 ± 0.10

3.50 ±0.05

1.65 ±0.05
(2 SIDES)2.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

0.50
BSC

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

PIN 1

TOP MARK

(SEE NOTE 5)

0.200 REF

MS10 Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

0.889

± 0.127

(.035 ± .005)

5.23

(.206)

MIN

0.305 ± 0.038

(.0120 ± .0015)

TYP

RECOMMENDED SOLDER PAD LAYOUT

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3.2 – 3.45

(.126 – .136)

0.50

(.0197)

BSC

0.254

(.010)

GAUGE PLANE

0.18

(.007)

3.00 ±0.10

(4 SIDES)

0.75 ±0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

DETAIL “A”

0° – 6° TYP

0.53 ± 0.01

(.021 ± .006)

DETAIL “A”

SEATING

PLANE

1.65 ± 0.10

(2 SIDES)

0.00 – 0.05

3.00 ± 0.102
(.118 ± .004)

(NOTE 3)

4.88 ± 0.10

(.192 ± .004)

(.043)

0.17 – 0.27

(.007 – .011)

BOTTOM VIEW—EXPOSED PAD

8910

7

45

12

3

1.10

MAX

0.50

(.0197)

TYP

2.38 ±0.10

(2 SIDES)

6

15

0.25 ± 0.05

0.50 BSC

0.497 ± 0.076
(.0196 ± .003)

REF

3.00 ± 0.102
(.118 ± .004)

NOTE 4

0.86

(.034)

REF

0.13 ± 0.05

(.005 ± .002)

MSOP (MS) 0402

(DD10) DFN 0403

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3411f

19

LTC3411

TYPICAL APPLICATIO

V

IN

2.63V

TO 4.2V

C6
1µF

47pF

C7

U

2mm Height, 2MHz, Li-Ion to 1.8V Converter

SW

V

R5
100k

L1

C4 22pF

1µH

FB

T

R4
154k

R1
698k

R2

887k

+

C2
33µF

C5
1µF

V

OUT

1.8V
AT 1.25A

+

C1
33µF

470pF

PV

IN

SV

IN

SYNC/MODE
I

TH

R3

SGND PGND

15k

C3

PGOOD PGOOD

LTC3411

SHDN/R

C1, C2: AVX TPSB336K006R0600
C4, C5: TAIYO YUDEN LMK212BJ105MG
L1: COILCRAFT DO1606T-102

Efficiency vs Load Current

100

95

V

OUT

= 2MHz

f

O

= 1.8V

10

2.5V

3.6V

4.2V

LOAD CURRENT (mA)

3411 TA05

90
85
80
75
70

EFFICIENCY (%)

65
60
55
50

1 100 1000 10000

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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LT1776 500mA (I

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LTC3405/LTC3405A 300mA (I

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LTC3412 2.5A (I

LTC3413 3A (I

for DDR/QDR Memory Termination IQ: 280µA, ISD: <1µA, TSSOP16E

LTC3430 60V, 2.75A (I

LTC3440 600mA (I

ThinSOT is a trademark of Linear Technology Corporation.

Linear Technology Corporation

20

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

) 1.4MHz High Efficiency Step-Down DC/DC Converter 90% Efficiency, VIN: 3.6V to 25V, V

OUT

) 200kHz High Efficiency Step-Down DC/DC Converter 90% Efficiency, VIN: 7.4V to 40V, V

OUT

) 550kHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.7V to 10V, V

OUT

) 1.5MHz Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.7V to 6V, V

OUT

) 1.5MHz Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, V

OUT

: 1.9mA, ISD: <1µA, ThinSOT

I

Q

: 3.2mA, ISD: 30µA, N8, S8

I

Q

: 15µA, ISD: <1µA, TSSOP16

I

Q

: 20µA, ISD: <1µA, ThinSOT

I

Q

IQ: 20µA, ISD: <1µA, ThinSOT

) 4MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, V

OUT

Sink/Source) 2MHz Monolithic Synchronous Regulator 90% Efficiency, VIN: 2.25V to 5.5V, V

OUT

) 200kHz High Efficiency Step-Down DC/DC Converter 90% Efficiency, VIN: 5.5V to 60V, V

OUT

) 2MHz Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, V

OUT

●

www.linear.com

: 60µA, ISD: <1µA, TSSOP16E

I

Q

: 2.5mA, ISD: 25µA, TSSOP16E

I

Q

: 25µA, ISD: <1µA, 10-Lead MS

I

Q

3411 TA04

: 1.25V,

OUT(MIN)

: 1.24V,

OUT(MIN)

: 0.8V,

OUT(MIN)

: 0.8V,

OUT(MIN)

: 0.6V,

OUT(MIN)

: 0.8V,

OUT(MIN)

: V

OUT(MIN)

OUT(MIN)

OUT(MIN)

LT/TP 0403 2K • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORA TION 2002

REF

: 1.20V,

: 2.5V,

/2,

3411f