ANALOG DEVICES LTC3407EMSEPBF Datasheet

LTC3407

Dual Synchronous, 600mA,

1.5MHz Step-Down
DC/DC Regulator

FEATURES

n

High Effi ciency: Up to 96%

n

Very Low Quiescent Current: Only 40μA

n

1.5MHz Constant Frequency Operation

n

High Switch Current: 1A on Each Channel

n

No Schottky Diodes Required

n

Low R

n

Current Mode Operation for Excellent Line

Internal Switches: 0.35Ω

DS(ON)

and Load Transient Response

n

Short-Circuit Protected

n

Low Dropout Operation: 100% Duty Cycle

n

Ultralow Shutdown Current: IQ < 1μA

n

Output Voltages from 5V down to 0.6V

n

Power-On Reset Output

n

Externally Synchronizable Oscillator

n

Small Thermally Enhanced MSOP and 3mm × 3mm

DFN Packages

APPLICATIONS

n

PDAs/Palmtop PCs

n

Digital Cameras

n

Cellular Phones

n

Portable Media Players

n

PC Cards

n

Wireless and DSL Modems

DESCRIPTION

The LTC®3407 is a dual, constant frequency, synchronous
step down DC/DC converter. Intended for low power ap­plications, it operates from 2.5V to 5.5V input voltage
range and has a constant 1.5MHz switching frequency,
allowing the use of tiny, low cost capacitors and inductors
2mm or less in height. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 1A power
switches provide high effi ciency without the need for
external Schottky diodes.

A user selectable mode input is provided to allow the user
to trade-off ripple noise for low power effi ciency. Burst

®

Mode
while pulse-skipping mode provides low ripple noise at
light loads.

To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40μA. In shutdown, the device draws <1μA.

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.

operation provides high effi ciency at light loads,

TYPICAL APPLICATION

VIN= 2.5V

V

OUT2

AT 600mA

TO 5.5V

= 2.5V

C3

10μF

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: MURATA LQH32CN2R2M33

Figure 1. 2.5V/1.8V at 600mA Step-Down Regulators

R4

887k

C1
10μF

2.2μH

R3

280k

RUN2 V

MODE/SYNC

SW2

V

FB2

LTC3407

GND

L2

LTC3407 Effi ciency Curve

R5

L1

2.2μH

100k

R1
442k

RESET

C4, 22pFC5, 22pF

887k

V

= 1.8V

OUT1

AT 600mA

R2

C2
10μF

3407 TA01

RUN1

IN

POR

SW1

V

FB1

100

95

90

85

80

75

EFFICIENCY (%)

70

VIN = 3.3V

65

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

60

1

LOAD CURRENT (mA)

2.5V

1.8V

10 100 1000

3407 TA02

3407fa

1

LTC3407

ABSOLUTE MAXIMUM RATINGS

(Note 1)

VIN Voltages ................................................. –0.3V to 6V

, V

V

FB1

RUN1, RUN2 Voltages .................................–0.3V to V

Voltages .......................... –0.3V to VIN + 0.3V

FB2

IN

MODE/SYNC Voltage ........................ –0.3V to VIN + 0.3V

SW1, SW2 Voltage ........................... –0.3V to V

+ 0.3V

IN

POR Voltage ................................................. –0.3V to 6V

Ambient Operating Temperature

Range (Note 2) ....................................–40°C to 85°C

PIN CONFIGURATION

TOP VIEW

10

9

8

7

6

V

FB2

RUN2

POR

SW2

MODE/
SYNC

V

1

FB1

RUN1

2

V

IN

SW1

GND

10-LEAD (3mm × 3mm) PLASTIC DFN

T

= 125°C, θJA = 45°C/W, θJC = 10°C/W

EXPOSED PAD IS PGND (PIN 11) MUST BE CONNECTED TO GND

JMAX

3

4

5

DD PACKAGE

11

Junction Temperature (Note 5) ............................. 125°C

Storage Temperature Range

LTC3407EMSE ...................................– 65°C to 150°C

LTC3407EDD ...................................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

LTC3407EMSE only ........................................... 300°C

TOP VIEW

10

1

V

FB1

RUN1

2
3
4
5

MSE PACKAGE

11

V

IN

SW1
GND

10-LEAD PLASTIC MSOP

T

= 125°C, θJA = 45°C/W, θJC = 10°C/W

EXPOSED PAD IS PGND (PIN 11) MUST BE CONNECTED TO GND

JMAX

V

FB2

RUN2

9

POR

8

SW2

7

MODE/

6

SYNC

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3407EDD#PBF LTC3407EDD#TRPBF LAGK 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC3407EMSE#PBF LTC3407EMSE#TRPBF LTABA 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 85°C

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.

For more information on lead free part marking, go to:
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifi cations are at TA = 25°C. VIN = 3.6V, unless otherwise specifi ed. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

FB

V

FB

ΔV

LINE REG

ΔV

LOAD REG

Operating Voltage Range

Feedback Pin Input Current

Feedback Voltage (Note 3) 0°C ≤ TA ≤ 85°C

Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.3 0.5 %/V

Output Voltage Load Regulation (Note 3) 0.5 %

http://www.linear.com/leadfree/

The l denotes the specifi cations which apply over the full operating

–40°C ≤ T

≤ 85°C ●

A

2.5 5.5 V

●

●

0.588

0.585

0.6

0.6

30 nA

0.612

0.612

3407fa

V
V

2

LTC3407

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifi cations are at T

The l denotes the specifi cations which apply over the full operating

= 25°C. VIN = 3.6V, unless otherwise specifi ed. (Note 2)

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

S

f

OSC

f

SYNC

I

LIM

R

DS(ON)

I

SW(LKG)

POR Power-On Reset Threshold V

Input DC Supply Current
Active Mode
Sleep Mode
Shutdown

Oscillator Frequency V

V

= V

FB1

FB2

V

= V

FB1

FB2

RUN = 0V, V

= 0.6V

FBX

= 0.5V
= 0.63V, MODE/SYNC = 3.6V

= 5.5V, MODE/SYNC = 0V

IN

600

40

0.1

1.2 1.5 1.8 MHz

●

800

60

1

μA
μA
μA

Synchronization Frequency 1.5 MHz

Peak Switch Current Limit VIN = 3V, VFB = 0.5V, Duty Cycle <35% 0.75 1 1.25 A

Top Switch On-Resistance
Bottom Switch On-Resistance

Switch Leakage Current VIN = 5V, V

(Note 6)
(Note 6)

= 0V, V

RUN

Ramping Up, MODE/SYNC = 0V

FBX

V

Ramping Down, MODE/SYNC = 0V

FBX

= 0V 0.01 1 μA

FBX

0.35

0.30

8.5

–8.5

0.45

0.45

Power-On Reset On-Resistance 100 200 Ω

Power-On Reset Delay 262,144 Cycles

V

RUN

I

RUN

V

MODE

RUN Threshold

RUN Leakage Current

Mode Threshold Low
Mode Threshold High

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTC3407E is guaranteed to meet specifi ed performance
from 0°C to 70°C. Specifi cations over the – 40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: The LTC3407 is tested in a proprietary test mode that connects VFB
to the output of the error amplifi er.

Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.

Note 5: T

is calculated from the ambient TA and power dissipation P

J

according to the following formula: TJ = TA + (PD • θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to

wafer level measurements.

0.3 1 1.5 V

●

●

0.01 1 μA

0

V

– 0.5

IN

0.5
V

IN

D

Ω
Ω

%
%

V
V

TYPICAL PERFORMANCE CHARACTERISTICS

Pulse-Skipping Mode Load Step

SW

5V/DIV

V

OUT

I

L

VIN = 3.6V

= 1.8V

V

OUT

= 50mA

I

LOAD

CIRCUIT OF FIGURE 1

1μs/DIV

SW

5V/DIV

V

OUT

100mV/DIV

200mA/DIV

Burst Mode Operation

I

L

VIN = 3.6V

= 1.8V

V

OUT

= 50mA

I

LOAD

CIRCUIT OF FIGURE 1

4μs/DIV

10mV/DIV

200mA/DIV

3407 G01

3407 G02

V

OUT

200mV/DIV

500mA/DIV

I

LOAD

500mA/DIV

I

L

VIN = 3.6V

= 1.8V

V

OUT

= 50mA TO 600mA

I

LOAD

CIRCUIT OF FIGURE 1

20μs/DIV

3407 G03

3407fa

3

LTC3407

TYPICAL PERFORMANCE CHARACTERISTICS

Effi ciency vs Input Voltage

100

TA = 25°C

95

90

1mA

85

600mA

80

75

EFFICIENCY (%)

70

65

V

= 1.8V

OUT

CIRCUIT OF FIGURE 1

60

2

3

INPUT VOLTAGE (V)

100mA

10mA

456

3407 G04

Reference Voltage vs
Temperature R

0.615
VIN = 3.6V

0.610

0.605

0.600

0.595

REFERENCE VOLTAGE (V)

0.590

0.585

–50 25 75

–25 0

TEMPERATURE (°C)

50 100 125

3407 G07

Oscillator Frequency vs
Temperature

1.70

1.65

1.60

1.55

1.50

1.45

FREQUENCY (MHz)

1.40

1.35

1.30
–50 25 75

–25 0

TEMPERATURE (°C)

vs Input Voltage R

DS(ON)

500

TA = 25°C

450

400

(mΩ)

350

DS(ON)

R

300

250

200

SYNCHRONOUS

1

SWITCH

2

MAIN
SWITCH

3

VIN (V)

50 100 125

3407 G05

57

46

3407 G08

Oscillator Frequency vs Supply
Voltage

1.8
TA = 25°C

1.7

1.6

1.5

1.4

OSCILLATOR FREQUENCY (MHz)

1.3

1.2

550

500

450

400

350

(mΩ)

300

DS(ON)

R

250

200

150

100

2

–50

3

vs Temperature

DS(ON)

VIN = 4.2V

MAIN SWITCH
SYNCHRONOUS SWITCH

–25 0

456

SUPPLY VOLTAGE (V)

VIN = 2.7V

VIN = 3.6V

50 100 150125

25 75

TEMPERATURE (°C)

3407 G06

3407 G09

Effi ciency vs Load Current Effi ciency vs Load Current Load Regulation

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

1

3.3V

4.2V

V

= 2.5V Burst Mode OPERATION

OUT

CIRCUIT OF FIGURE 1

10 100 1000

LOAD CURRENT (mA)

2.7V

3407 G10

100

95

Burst Mode OPERATION

90

85

80

75

EFFICIENCY (%)

70

65

60

1

PULSE-SKIPPING
MODE

VIN = 3.6V, V
NO LOAD ON OTHER CHANNEL

10 100 1000

LOAD CURRENT (mA)

OUT

= 1.8V

3407 G11

4

3

2

1

0

ERROR (%)

–1

OUT

V

–2

–3

–4

1

4

Burst Mode OPERATION

PULSE-SKIPPING

MODE

VIN = 3.6V, V
NO LOAD ON OTHER CHANNEL

10 100 1000

LOAD CURRENT (mA)

OUT

= 1.8V

3407 G12

3407fa

TYPICAL PERFORMANCE CHARACTERISTICS

Effi ciency vs Load Current Effi ciency vs Load Current Line Regulation

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

1

3.3V

4.2V

V

= 1.2V Burst Mode OPERATION

OUT

CIRCUIT OF FIGURE 1

10 100 1000

LOAD CURRENT (mA)

2.7V

3407 G13

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

1

3.3V

4.2V

V

= 1.5V Burst Mode OPERATION

OUT

CIRCUIT OF FIGURE 1

10 100 1000

LOAD CURRENT (mA)

2.7V

3407 G14

0.5

0.4

0.3

0.2

0.1

0

ERROR (%)

–0.1

OUT

V

–0.2

–0.3

–0.4

–0.5

2

LTC3407

V

= 1.8V

OUT

= 200mA

I

OUT

= 25°C

T

A

35

4

VIN (V)

6

3407 G15

PIN FUNCTIONS

V

(Pin 1): Output Feedback. Receives the feedback volt-

FB1

age from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.

RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to V
enables regulator 1, while forcing it to GND causes regulator
1 to shut down. This pin must be driven; do not fl oat.

(Pin 3): Main Power Supply. Must be closely decoupled

V

IN

to GND.

SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from V

to GND.

IN

GND (Pin 5): Ground. This pin is not connected internally.
Connect to PCB ground for shielding.

MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the opera­tion of the device. When tied to V

or GND, Burst Mode

IN

operation or pulse-skipping mode is selected, respectively.
Do not fl oat this pin. The oscillation frequency can be

IN

synchronized to an external oscillator applied to this pin
and pulse-skipping mode is automatically selected.

SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from V

to GND.

IN

POR (Pin 8): Power-On Reset . This common-drain logic
output is pulled to GND when the output voltage is not
within ±8.5% of regulation and goes high after 175ms
when both channels are within regulation.

RUN2 (Pin 9): Regulator 2 Enable. Forcing this pin to V

IN

enables regulator 2, while forcing it to GND causes regulator
2 to shut down. This pin must be driven; do not fl oat.

(Pin 10): Output Feedback. Receives the feedback

V

FB2

voltage from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.

Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the (–) terminal of C

, and (–) terminal of CIN. Must be

OUT

soldered to electrical ground on PCB.

3407fa

5

LTC3407

BLOCK DIAGRAM

MODE/SYNC

V

FB1

RUN1

RUN2

V

FB2

REGULATOR 1

6

+

0.6V

EA

1

0.55V

–

–

UVDET

+

+

OVDET

0.65V

–

SHUTDOWN

2

0.6V REF OSC

9

REGULATOR 2 (IDENTICAL TO REGULATOR 1)

10

BURST

CLAMP

SLOPE

COMP

EN

I

–

TH

0.35V

+

SRQ

RS

LATCH

UV

OV

BURST

Q

SLEEP

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

–

I

COMP

ANTI

SHOOT-

THRU

+

V

IN

5Ω

SW1

4

+

I

RCMP

OSC

POR

COUNTER

–

PGOOD1

PGOOD2

GND

11

V

IN

3

V

IN

POR

8

5

GND

7

SW2

OPERATION

The LTC3407 uses a constant frequency, current mode
architecture. The operating frequency is set at 1.5MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable Mode pin allows
the user to trade-off noise for effi ciency.

The output voltage is set by an external divider returned
to the V
output voltage with a reference voltage of 0.6V and adjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the POR output low if
the output voltage is not within ±8.5%. The POR output
will go high after 262,144 clock cycles (about 175ms) of
achieving regulation.

pins. An error amplifi er compares the divided

FB

3407 BD

Main Control Loop

During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V

voltage is below the the reference voltage.

FB

The current into the inductor and the load increases until
the current limit is reached. The switch turns off and
energy stored in the inductor fl ows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.

The peak inductor current is controlled by the internally
compensated I
ror amplifi er. This amplifi er compares the V

voltage, which is the output of the er-

TH

pin to the

FB

0.6V reference. When the load current increases, the
VFB voltage decreases slightly below the reference. This

3407fa

6

OPERATION

ΔIL=

V

OUT

fO•L

•1−

V

OUT

V

IN

⎛

⎝

⎜

⎞

⎠

⎟

L ≥

V

OUT

fO• ΔI

L

•1–

V

OUT

V

IN(MAX)

⎛

⎝

⎜
⎜

⎞

⎠

⎟
⎟

LTC3407

decrease causes the error amplifi er to increase the ITH
voltage until the average inductor current matches the
new load current.

The main control loop is shut down by pulling the RUN
pin to ground.

Low Current Operation

Two modes are available to control the operation of the
LTC3407 at low currents. Both modes automatically switch
from continuous operation to to the selected mode when
the load current is low.

To optimize effi ciency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407
automatically switches into Burst Mode operation in which
the PMOS switch operates intermittently based on load
demand with a fi xed peak inductor current. By running
cycles periodically, the switching losses which are domi­nated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value.
A hysteretic voltage comparator trips when I

is below

TH

0.35V, shutting off the switch and reducing the power. The
output capacitor and the inductor supply the power to the
load until I

exceeds 0.65V, turning on the switch and the

TH

main control loop which starts another cycle.

For lower ripple noise at low currents, the pulse-skipping
mode can be used. In this mode, the LTC3407 continues to
switch at a constant frequency down to very low currents,
where it will begin skipping pulses.

Dropout Operation

When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being equal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.

An important design consideration is that the R

DS(ON)

of the P-channel switch increases with decreasing input
supply voltage (See Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407 is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applica­tions Information Section).

Low Supply Operation

The LTC3407 incorporates an Under-Voltage Lockout circuit
which shuts down the part when the input voltage drops
below about 1.65V to prevent unstable operation.

APPLICATIONS INFORMATION

A general LTC3407 application circuit is shown in Figure 2.
External component selection is driven by the load require­ment, and begins with the selection of the inductor L. Once
the inductor is chosen, C

and C

IN

Inductor Selection

Although the inductor does not infl uence the operat­ing frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current ΔI
with higher inductance and increases with higher V

:

V

OUT

Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple,

can be selected.

OUT

decreases

L

IN

or

greater core losses, and lower output current capability. A
reasonable starting point for setting ripple current is ΔI

0.3 • I

, where I

LIM

largest ripple current ΔI

is the peak switch current limit. The

LIM

occurs at the maximum input

L

=

L

voltage. To guarantee that the ripple current stays below a
specifi ed maximum, the inductor value should be chosen
according to the following equation:

The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower

3407fa

7

LTC3407

I

RMS≈IMAX

V

OUT(VIN–VOUT

)

V

IN

V

OUT

ILESR+

1

8f

OCOUT













APPLICATIONS INFORMATION

load currents. This causes a dip in effi ciency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.

Inductor Core Selection

Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style in­ductor to use often depends more on the price vs size
requirements and any radiated fi eld/EMI requirements
than on what the LTC3407 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3407 applications.

Input Capacitor (C

) Selection

IN

In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately V

OUT/VIN

.
To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:

where the maximum average output current I

MAX

equals

the peak current minus half the peak-to-peak ripple cur-

= I

rent, I

MAX

This formula has a maximum at V

/2. This simple worst-case is commonly used to

= I

OUT

– ΔIL/2.

LIM

= 2V

IN

, where I

OUT

RMS

design because even signifi cant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur­rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
the size or height requirements of the design. An additional

0.1μF to 1μF ceramic capacitor is also recommended on

for high frequency decoupling, when not using an all

V

IN

ceramic capacitor solution.

Table 1. Representative Surface Mount Inductors

PART
NUMBER

Sumida
CDRH3D16

Sumida
CMD4D06

Panasonic
ELT5KT

Murata
LQH32CN

Output Capacitor (C

The selection of C

VALUE

(μH)

1.5

2.2

3.3

4.7

2.2

3.3

4.7

3.3

4.7

1.0

2.2

4.7

DCR

(Ω MAX)

0.043

0.075

0.110

0.162

0.116

0.174

0.216

0.17

0.20

0.060

0.097

0.150

OUT

is driven by the required ESR to

OUT

MAX DC

CURRENT (A)

1.55

1.20

1.10

0.90

0.950

0.770

0.750

1.00

0.95

1.00

0.79

0.65

) Selection

SIZE

W × L × H (mm

3.8 × 3.8 × 1.8

3.5 × 4.3 × 0.8

4.5 × 5.4 × 1.2

2.5 × 3.2 × 2.0

3

)

minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfi ed, the capacitance
is adequate for fi ltering. The output ripple (ΔV

OUT

) is

determined by:

where f = operating frequency, C
and ΔI

= ripple current in the inductor. The output ripple

L

is highest at maximum input voltage since ΔI
with input voltage. With ΔI

= 0.3 • I

L

will be less than 100mV at maximum V

= output capacitance

OUT

increases

L

the output ripple

LIM

and fO = 1.5MHz

IN

with:

ESR

Once the ESR requirements for C
RMS current rating generally far exceeds the I

COUT

< 150mΩ

have been met, the

OUT

RIPPLE(P-P)

requirement, except for an all ceramic solution.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirement of the application. Aluminum
electrolytic, special polymer, ceramic and dry tantulum
capacitors are all available in surface mount packages. The
OS-CON semiconductor dielectric capacitor available from
Sanyo has the lowest ESR(size) product of any aluminum
electrolytic at a somewhat higher price. Special polymer

8

3407fa

APPLICATIONS INFORMATION

LTC3407

capacitors, such as Sanyo POSCAP, offer very low ESR,
but have a lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density,
but it has a larger ESR and it is critical that the capacitors
are surge tested for use in switching power supplies.
An excellent choice is the AVX TPS series of surface
mount tantalums, available in case heights ranging from
2mm to 4mm. Aluminum electrolytic capacitors have a
signifi cantly larger ESR, and are often used in extremely
cost-sensitive applications provided that consideration
is given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost, but also
have the lowest capacitance density, a high voltage and
temperature coeffi cient, and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to signifi cant ringing. Other
capacitor types include the Panasonic special polymer
(SP) capacitors.

In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3407 in parallel with the
main capacitors for high frequency decoupling.

VIN= 2.5V

TO 5.5V

C

IN

BURST*

PULSESKIP*

V

OUT2

R4 R2

C

OUT2

RUN2 V

IN

MODE/SYNC

L2

R3

LTC3407

SW2

V

FB2

GND

*MODE/SYNC = 0V: PULSE-SKIPPING
MODE/SYNC = V

IN

RUN1

POR

SW1

V

: Burst Mode OPERATION

R5

POWER-ON

RESET

L1

C4C5

FB1

R1

C

V

OUT1

OUT1

3407 F02

Figure 2. LTC3407 General Schematic

Ceramic Input and Output Capacitors

Higher value, lower cost ceramic capacitors are now be­coming available in smaller case sizes. These are tempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR gener­ates a loop “zero” at 5kHz to 50kHz that is instrumental in
giving acceptable loop phase margin. Ceramic capacitors
remain capacitive to beyond 300kHz and usually resonate
with their ESL before ESR becomes effective. Also, ceramic

caps are prone to temperature effects which requires the
designer to check loop stability over the operating tem­perature range. To minimize their large temperature and
voltage coeffi cients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK, and Murata.

Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the V

pin. At best, this ringing can

IN

couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.

Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfi ll a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, 3-4 cycles are required
to respond to a load step, but only in the fi rst cycle does
the output drop linearly. The output droop, V

DROOP

, is
usually about 3 times the linear drop of the fi rst cycle.
Thus, a good place to start is with the output capacitor
size of approximately:

ΔI

C

≈ 3

OUT

fO•V

OUT

DROOP

More capacitance may be required depending on the duty
cycle and load step requirements.

In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.

Setting the Output Voltage

The LTC3407 develops a 0.6V reference voltage between
the feedback pin, V

, and the ground as shown in Figure 2.

FB

The output voltage is set by a resistive divider according
to the following formula:

3407fa

9

LTC3407

APPLICATIONS INFORMATION

= 0.6V 1+

OUT

⎜
⎝

V

⎛

R2
R1

⎞
⎟

⎠

Keeping the current small (<5μA) in these resistors maxi­mizes effi ciency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.

To improve the frequency response, a feed-for ward capaci­tor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.

Power-On Reset

The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output volt­ages are within ±8.5% of regulation, a timer is started which
releases POR after 2

18

clock cycles (about 175ms). This
delay can be signifi cantly longer in Burst Mode operation
with low load currents, since the clock cycles only occur
during a burst and there could be milliseconds of time
between bursts. This can be bypassed by tying the POR
output to the MODE/SYNC input, to force pulse-skipping
mode during a reset. In addition, if the output voltage
faults during Burst Mode sleep, POR could have a slight
delay for an undervoltage output condition and may not
respond to an overvoltage output. This can be avoided by
using pulse-skipping mode instead. When either channel
is shut down, the POR output is pulled low, since one or
both of the channels are not in regulation.

Mode Selection & Frequency Synchronization

The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect­ing this pin to VIN enables Burst Mode operation, which
provides the best low current effi ciency at the cost of a
higher output voltage ripple. When this pin is connected
to ground, pulse-skipping operation is selected which
provides the lowest output ripple, at the cost of low cur­rent effi ciency.

The LTC3407 can also be synchronized to another LTC3407
by the MODE/SYNC pin. During synchronization, the mode
is set to pulse-skipping and the top switch turn-on is syn­chronized to the rising edge of the external clock.

Checking Transient Response

The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ΔI
resistance of C
charge C

OUT

• ESR, where ESR is the effective series

LOAD

OUT

generating a feedback error signal used by the
regulator to return V
this recovery time, V

immediately shifts by an amount

OUT

. ΔI

also begins to charge or dis-

LOAD

to its steady-state value. During

OUT

can be monitored for overshoot

OUT

or ringing that would indicate a stability problem.

The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second­order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor, C

,

F

can be added to improve the high frequency response, as
shown in Figure 2. Capacitor C

provides phase lead by

F

creating a high frequency zero with R2 which improves
the phase margin.

The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re­view of control loop theory, refer to Application Note 76.

In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in paral­lel with C

, causing a rapid drop in V

OUT

. No regulator

OUT

can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifi cally for this purpose and usually incorporates cur­rent limiting, short-circuit protection, and soft-starting.

Effi ciency Considerations

The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would

Hot Swap is a trademark of Linear Technology Corporation.

10

3407fa

APPLICATIONS INFORMATION

LTC3407

produce the most improvement. Percent effi ciency can
be expressed as:

%Effi ciency = 100% - (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent­age of input power.

Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407 circuits: 1)V

2

switching losses, 3) I

1) The V

current is the DC supply current given in the

IN

R losses, 4) other losses.

quiescent current, 2)

IN

Electrical Characteristics which excludes MOSFET driver
and control currents. V
loss that increases with V

current results in a small (< 0.1%)

IN

, even at no load.

IN

2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from V
ground. The resulting dQ/dt is a current out of V

IN

that is

IN

to

typically much larger than the DC bias current. In continu­ous mode, I

GATECHG

= fO(QT + QB), where QT and QB are
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V

IN

and thus their effects will be more pronounced at higher
supply voltages.

2

R losses are calculated from the DC resistances of the

3) I
internal switches, R

, and external inductor, RL. In con-

SW

tinuous mode, the average output current fl owing through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R

R

The R

and the duty cycle (DC) as follows:

DS(ON)

= (R

SW

DS(ON)

DS(ON)TOP

for both the top and bottom MOSFETs can

)(DC) + (R

DS(ON)BOT

)(1 – DC)

be obtained from the Typical Performance Characteristics

2

curves. Thus, to obtain I

2

R losses = (I

I

OUT

R losses:

)2 (RSW + RL)

4) Other ‘hidden’ losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. It is very important

to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C

has adequate

IN

charge storage and very low ESR at the switching frequency.
Other losses including diode conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.

Thermal Considerations

In a majority of applications, the LTC3407 does not dis­sipate much heat due to its high effi ciency. However, in
applications where the LTC3407 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.

To prevent the LTC3407 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:

RISE

= PD • θ

JA

T

where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.

The junction temperature, T

T

J

= T

RISE

+ T

AMBIENT

, is given by:

J

As an example, consider the case when the LTC3407 is
in dropout on both channels at an input voltage of 2.7V
with a load current of 600mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the R

resistance of

DS(ON)

the main switch is 0.425Ω. Therefore, power dissipated
by each channel is:

P

D

= I

OUT

2

• R

DS(ON)

= 153mW

The MS package junction-to-ambient thermal resistance,

, is 45°C/W. Therefore, the junction temperature of

θ

JA

3407fa

11

LTC3407

C

OUT

≈ 3

600mA

1.5MHz •(5% • 2.5V)

= 9.6μF

APPLICATIONS INFORMATION

the regulator operating in a 70°C ambient temperature is
approximately:

TJ = 2 • 0.153 • 45 + 70 = 84°C

which is below the absolute maximum junction tempera­ture of 125°C.

Design Example

As a design example, consider using the LTC3407 in an
portable application with a Li-Ion battery. The battery pro­vides a V

= 2.8V to 4.2V. The load requires a maximum

IN

of 600mA in active mode and 2mA in standby mode. The
output voltage is V

= 2.5V. Since the load still needs

OUT

power in standby, Burst Mode operation is selected for
good low load effi ciency.

First, calculate the inductor value for about 30% ripple
current at maximum VIN:

L ≥

1.5MHz • 300mA

2.5V

⎛

•1–

⎜
⎝

2.5V

4.2V

⎞

= 2.25μH

⎟
⎠

Choosing the closest inductor from a vendor of 2.2μH
inductor, results in a maximum ripple current of:

⎛

•1−

⎜
⎝

ΔIL=

1.5MHz • 2.2μH

2.5V

For cost reasons, a ceramic capacitor will be used. C

2.5V

4.2V

⎞

= 307mA

⎟
⎠

OUT

selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:

The closest standard value is 10μF. Since the output imped­ance of a Li-Ion battery is very low, CIN is typically 10μF.

The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high effi ciency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A close
standard 1% resistor is 280k, and R2 is then 887k.

The POR pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.

Figure 1 shows the complete schematic for this design
example.

Board Layout Considerations

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3407. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout:

1. Does the capacitor CIN connect to the power VIN (Pin

3) and GND (exposed pad) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.

2. Are the C
C

returns current to GND and the (–) plate of CIN.

OUT

and L1 closely connected? The (–) plate of

OUT

3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C

and a ground sense line

OUT

terminated near GND (Exposed Pad). The feedback signals
VFB should be routed away from noisy components and
traces, such as the SW line (Pins 4 and 7), and its trace
should be minimized.

4. Keep sensitive components away from the SW pins. The
input capacitor CIN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.

5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the GND pin at one point and
should not share the high current path of CIN or C

OUT

.

6. Flood all unused areas on all layers with copper. Flood­ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
V

or GND.

IN

V

IN

C

IN

V

OUT2

R4 R2

C

OUT2

BOLD LINES INDICATE HIGH CURRENT PATHS

L2

R3

RUN2 V

MODE/SYNC

SW2

V

FB2

IN

LTC3407

GND

RUN1

SW1

POR

V

L1

C4C5

FB1

R1

3407 F03

V

OUT1

C

OUT1

12

Figure 3. LTC3407 Layout Diagram (See Board Layout Checklist)

3407fa

TYPICAL APPLICATIONS

Low Ripple Buck Regulators Using Ceramic Capacitors

VIN= 2.5V

TO 5.5V

= 1.8V

V

OUT2

AT 600mA

C1
10μF

4.7μH

LTC3407

R5

L1

4.7μH

100k

POWER-ON
RESET

C4, 22pFC5, 22pF

V

= 1.2V

OUT1

AT 600mA

RUN2 V

L2

SW2

IN

LTC3407

RUN1

POR

SW1

GND

V

FB1

R1
604k

V

C3

10μF

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML L1, L2: MURATA LQH32CN4R7M11

R4

887k

R3

442k

FB2

MODE/SYNC

Effi ciency

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

1

V

= 1.8V

OUT

V

= 1.2V

OUT

VIN = 3.3V Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

10 100 1000

LOAD CURRENT (mA)

3407 TA03b

R2

604k

C2
10μF

3407 TA03

3407fa

13

LTC3407

TYPICAL APPLICATIONS

VIN= 3.6V

TO 5.5V

= 3.3V

V

OUT2

AT 600mA

2mm Height Core Supply

C1
10μF

L2

4.7μH

RUN2 V

MODE/SYNC

LTC3407

SW2

R5

L1

2.2μH

100k

POWER-ON
RESET

C4, 22pFC5, 22pF

V

= 1.8V

OUT1

AT 600mA

RUN1

IN

POR

SW1

C3

10μF

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
L1: MURATA LQH32CN2R2M33
L2: MURATA LQH32CN4R7M11

R4

R3

887k

196k

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

1

GND

V

FB1

V

FB2

Effi ciency vs Load Current

VIN = 5V Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

10 100 1000

LOAD CURRENT (mA)

R1
301k

3.3V

1.8V

3407 TA08

R2

604k

C2
10μF

3407 TA07

14

3407fa

PACKAGE DESCRIPTION

LTC3407

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev B)

3.55 ±0.05

0.70 ±0.05

1.65 ±0.05
(2 SIDES)2.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

2.38 ±0.05
(2 SIDES)

0.50
BSC

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev C)

3.00 ±0.10
(4 SIDES)

0.75 ±0.05

0.00 – 0.05

1.65 ± 0.10
(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

R = 0.125

TYP

2.38 ±0.10
(2 SIDES)

106

15

0.50 BSC

0.40 ± 0.10

(DD) DFN REV B 0309

0.25 ± 0.05

5.23

(.206)

MIN

0.305 ± 0.038

(.0120 ± .0015)

TYP

2.794 ± 0.102
(.110 ± .004)

2.083 ± 0.102
(.082 ± .004)

0.50

(.0197)

RECOMMENDED SOLDER PAD LAYOUT

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

BSC

0.889

± 0.127

(.035 ± .005)

3.20 – 3.45

(.126 – .136)

GAUGE PLANE

0.18

(.007)

0.254

(.010)

DETAIL “A”

DETAIL “A”

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

° – 6° TYP

0

0.53

± 0.152

(.021 ± .006)

SEATING

PLANE

3.00 ± 0.102
(.118 ± .004)

(NOTE 3)

4.90

± 0.152

(.193 ± .006)

0.17 – 0.27

(.007 – .011)

TYP

1.10

(.043)

MAX

12

0.50

(.0197)

BSC

BOTTOM VIEW OF

0.497 ± 0.076

(.0196 ± .003)

8910

7

6

45

3

REF

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.86

(.034)

REF

0.1016 ± 0.0508
(.004 ± .002)

EXPOSED PAD OPTION

1

10

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

DETAIL “B”

MSOP (MSE) 0908 REV C

2.06 ± 0.102
(.081 ± .004)

1.83 ± 0.102
(.072 ± .004)

DETAIL “B”

0.29
REF

3407fa

15

LTC3407

TYPICAL APPLICATION

2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator

= 3.3V

V

OUT2

AT 200mA

+

C6
47μF

C3
10μF

D1

VIN= 2.8V

TO 4.2V

M1

10μH

R4

887k

C1
10μF

RUN2 V

IN

MODE/SYNC

SW2

V

LTC3407

FB2

GND

L2

R3

196k

RUN1

POR

SW1

R5
100k

POWER-ON
RESET

L1

2.2μH

C4, 22pF

V

FB1

R1
442k

R2

887k

V

OUT1

AT 600mA

C2
10μF

= 1.8V

C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
C6: SANYO 6TPB47M
D1: PHILIPS PMEG2010

L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-100M (D52LC SERIES)
M1: SILICONIX Si2302

Effi ciency vs Load Current Effi ciency vs Load Current

90

80

70

60

EFFICIENCY (%)

50

V

= 3.3V

40

OUT

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

30

1

LOAD CURRENT (mA)

10 100 1000

2.8V

4.2V

3.6V

3407 TA05

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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), 1.4MHz,

OUT

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LT1940 Dual Output 1.4A(I

, Constant 1.1MHz,

OUT)

High Effi ciency Step-Down DC/DC Converter

LTC3252 Dual 250mA (I

), 1MHz, Spread Spectrum

OUT

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LTC3405/LTC3405A 300mA (I

), 1.5MHz,

OUT

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LTC3406/LTC3406B 600mA (I

), 1.5MHz,

OUT

Synchronous Step-Down DC/DC Converters

LTC3407 600mA (I

), 1.5MHz,

OUT

Dual Synchronous DC/DC Converter

LTC3411 1.25A (I

OUT

), 4MHz,

Synchronous Step Down DC/DC Converter

LTC3412 2.5A (I

), 4MHz,

OUT

Synchronous Step Down DC/DC Converter

LTC3414 4A (I

), 4MHz,

OUT

Synchronous Step Down DC/DC Converter

LTC3440/LTC3441 600mA/1.2A (I

), 2MHz/1MHz,

OUT

Synchronous Buck-Boost DC/DC Converter

ThinSOT is a trademark of Linear Technology Corporation.

Linear Technology Corporation

16

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

90% Effi ciency, VIN: 3.6V to 25V, V

<1μA, ThinSOT™ Package

I

SD

VIN: 3V to 25V, V
TSSOP-16E Package

88% Effi ciency, VIN: 2.7V to 5.5V, V

< 1μA, DFN-12 Package

I

SD

96% Effi ciency, VIN: 2.5V to 5.5V, V

<1μA, ThinSOT Package

I

SD

96% Effi ciency, VIN: 2.5V to 5.5V, V

<1μA, ThinSOT Package

I

SD

96% Effi ciency, VIN: 2.5V to 5.5V, V

<1μA, MS10E Package, DFN Package

I

SD

95% Effi ciency, VIN: 2.5V to 5.5V, V

<1μA, MSOP-10 Package

I

SD

95% Effi ciency, VIN: 2.5V to 5.5V, V

<1μA, TSSOP-16E Package

I

SD

95% Effi ciency, VIN: 2.25V to 5.5V, V

<1μA, TSSOP-28E Package

I

SD

95% Effi ciency, VIN: 2.5V to 5.5V, V

<1μA, MSOP-10 Package/DFN Package

I

SD

100

95

90

85

80

75

EFFICIENCY (%)

70

V

OUT

65

Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL

60

1

OUT(MIN)

4.2V

= 1.8V

10 100 1000

LOAD CURRENT (mA)

OUT(MIN)

= 1.2V IQ = 2.5mA, ISD <1μA,

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

OUT(MIN)

© LINEAR TECHNOLOGY CORPORATION 2003

3407 TA04

2.8V

3.6V

3407 TA06

= 1.25V IQ = 1.9mA,

: 0.9V to 1.6V, IQ = 60μA

= 0.8V IQ = 20μA,

= 0.6V IQ = 20μA,

= 0.6V IQ = 40μA,

= 0.8V IQ = 60μA,

= 0.8V IQ = 60μA,

= 0.8V IQ = 64μA,

OUT(MIN)

= 2.5V IQ = 25μA,

LT 0809 REV A • PRINTED IN USA

3407fa