Very Low Quiescent Current: 38μA (Burst Mode
Operation)
■
2.6V to 5.5V Adjustable Output Voltage
■
0.85V (Typ) Start-Up Voltage
■
No External Schottky Diode Required (V
■
Synchronizable Switching Frequency
■
Burst Mode Enable Control
■
Antiringing Control Reduces Switching Noise
■
PGOOD Output
■
OPTI-LOOP® Compensation
■
Very Low Shutdown Current: <1μA
■
Small 10-Pin MSOP Package
OUT
< 4.3V)
U
APPLICATIO S
■
Cellular Telephones
■
Handheld Computers
■
MP3 Players
■
2-Way Pagers
■
GPS Receivers
■
Battery Backup Supplies
■
CCFL Backlights
LTC3402
2A, 3MHz Micropower
Synchronous Boost Converter
U
DESCRIPTIO
The LTC®3402 is a high efficiency, fixed frequency, stepup DC/DC converter that operates from an input voltage
below 1V. The device includes a 0.16Ω N-channel MOSFET
®
switch and a 0.18Ω P-channel synchronous rectifier.
Switching frequencies up to 3MHz are programmed with
an external timing resistor and the oscillator can be
synchronized to an external clock. An external Schottky
diode is optional but will slightly improve efficiency.
Quiescent current is only 38μA in Burst Mode operation,
maximizing battery life in portable applications. Burst
Mode operation is user controlled and can be enabled by
driving the MODE/SYNC pin high. If the MODE/SYNC pin
has either a clock or is driven low, then fixed frequency
switching is enabled.
Other features include a 1μA shutdown, antiringing con-
trol, open-drain power good output, thermal shutdown
and current limit. The LTC3402 is available in the 10-lead
thermally enhanced MSOP package. Lower current applications should use the 1A rated LTC3401 synchronous
boost converter. Applications that require V
OUT
< 2.6V
should use the LTC3424.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
All Ceramic Capacitor 2-Cell to 3.3V at 1A Step-Up Converter
MODE/SYNC Input CurrentV
Error Amp TransconductanceΔI = – 5μA to 5μA, VC = V
PGOOD ThresholdReferenced to Feedback Voltage– 6–9– 12%
= 3.3V unless otherwise noted.
OUT
= <1mA0.851.0V
LOAD
MODE/SYNC
= 5.5V0.011μA
FB
85μmhos
2
3402fb
Page 3
LTC3402
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V
= 1.2V, V
IN
PARAMETERCONDITIONSMINTYPMAXUNITS
PGOOD Low VoltageI
PGOOD LeakageV
SHDN Input HighVIN = V
SHDN Input Low0.4V
SHDN Input CurrentV
= 3.3V unless otherwise noted.
OUT
= 1mA0.10.2V
PGOOD
= 1V, I
V
OUT
= 5.5V0.011μA
PGOOD
SHDN
= 5.5V0.011μA
SHDN
= 20μA0.10.4V
PGOOD
1V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime..
Note 2: The LTC3402E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
with statistical process controls.
Note 3: Current is measured into the V
bootstrapped to the output pin and in the application will reflect to the
input supply by (V
Note 4: Once the output is started, the IC is not dependent upon the V
supply.
temperature range are assured by design, characterization and correlation
UW
TYPICAL PERFOR A CE CHARACTERISTICS
SW Pin and Inductor Current (IC)
in Discontinuous Mode. Ringing
Control Circuitry Eliminates High
Switching Waveform on SW Pin
SW
1V/DIV
50ns/DIV
50mA/DIV
3402 G01
Frequency RingingTransient Response 5mA to 50mA
I
L
0A
SW
1V/DIV
0V
200ns/DIV
pin since the supply current is
OUT
) • I/Efficiency. The outputs are not switching.
OUT/VIN
(TA = 25°C unless otherwise noted)
V
OUT
100mV/DIV
50mA
I
OUT
5mA
3402 G02
C
= 22μF200μs/DIV3402 G03
OUT
L = 3.3μH
= 1MHz
f
OSC
IN
V
OUT
200mV/DIV
550mA
50mA
Transient Response 50mA to 500mABurst Mode Operation
V
OUT
AC
100mV/DIV
SW
1V/DIV
= 22μF200μs/DIV3402 G04
C
OUT
L = 3.3μH
f
= 1MHz
OSC
V
= 1.2V5ms/DIV3402 G05
IN
V
= 3.3V
OUT
C
= 100μF
OUT
= 250μA
I
OUT
MODE/SYNC PIN = HIGH
V
OUT
100mV/DIV
SW
1V/DIV
Burst Mode Operation
AC
V
= 1.2V200μs/DIV3402 G06
IN
V
= 3.3V
OUT
C
= 100μF
OUT
= 20mA
I
OUT
MODE/SYNC PIN = HIGH
3402fb
3
Page 4
LTC3402
UW
TYPICAL PERFOR A CE CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Converter Efficiency 1.2V to 3.3V
100
90
Burst Mode
80
OPERATION
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.1101001000
300kHz
3MHz
1MHz
1
OUTPUT CURRENT (mA)
Start-Up Voltage
vs I
OUT
500
TA = 25°C
400
300
3402 G07
Converter Efficiency 2.4V to 3.3V
100
Burst Mode
90
OPERATION
80
70
300kHz
60
50
40
EFFICIENCY (%)
30
20
10
0
0.1101001000
1
OUTPUT CURRENT (mA)
3MHz
1MHz
Efficiency Loss Without Schottky
vs Frequency
14
TA = 25°C
12
10
8
3402 G08
Converter Efficiency 3.6V to 5V
100
Burst Mode OPERATION
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
VIN = 3.6V
0
0.1
1MHz
FIXED
FREQUENCY
110
LOAD CURRENT (mA)
Current Limit
3.4
3.2
3.0
2.8
100
1000
3402 G10
200
OUTPUT CURRENT (mA)
100
0
0.8
0.9
EA FB Voltage
1.28
1.27
1.26
1.25
VOLTAGE (V)
1.24
1.23
1.22
–1525105
–55
TEMPERATURE (°C)
1
1.11.2
VIN (V)
6
4
EFFICIENCY LOSS (%)
2
1.3
1.4
3402 G09
0
0.2
0.61.0
1.82.63.0
1.42.2
FREQUENCY (MHz)
3402 G11
Oscillator Frequency Accuracy
2.10
= 15k
R
t
2.05
2.00
FREQUENCY (MHz)
1.95
65
125
3402 G13
1.90
–1525105
–55
TEMPERATURE (°C)
65
125
3402 G14
2.6
CURRENT (A)
2.4
2.2
2.0
–55
NMOS R
0.30
V
OUT
0.25
0.20
0.15
RESISTANCE (Ω)
0.10
0.05
–55
–1525105
TEMPERATURE (°C)
65
DS(ON)
= 3.3V
–1525105
TEMPERATURE (°C)
65
125
3402 G12
125
3402 G22
4
3402fb
Page 5
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC3402
(TA = 25°C unless otherwise noted)
PMOS R
0.30
V
= 3.3V
OUT
0.25
0.20
0.15
RESISTANCE (Ω)
0.10
0.05
–55
PGOOD Threshold
–7.0
–7.5
–8.0
–8.5
(%)
FB
–9.0
–9.5
–10.0
–10.5
PERCENT FROM V
–11.0
–11.5
–12.0
–55
DS(ON)
–1525105
TEMPERATURE (°C)
–1525105
TEMPERATURE (°C)
65
65
3402 G16
3402 G19
125
125
Start-Up Voltage
1.1
1.0
0.9
0.8
VOLTAGE (V)
0.7
0.6
–1525105
–55
TEMPERATURE (°C)
Burst Mode Operation Current
44
42
40
38
36
CURRENT (μA)
34
32
30
–1525105
–55
TEMPERATURE (°C)
Shutdown Threshold
1.10
1.05
1.00
0.95
0.90
0.85
0.80
VOLTAGE (V)
0.75
0.70
0.65
65
65
125
3402 G17
125
3402 G20
0.60
2.50
2.45
2.40
2.35
2.30
2.25
2.20
VOLTAGE (V)
2.15
2.10
2.05
2.00
–1525105
–55
TEMPERATURE (°C)
V
Turn-Off Voltage
OUT
–1525105
–55
TEMPERATURE (°C)
65
65
125
3402 G18
125
3402 G21
3402fb
5
Page 6
LTC3402
U
UU
PI FU CTIO S
Rt (Pin 1): Timing Resistor to Program the Oscillator
Frequency.
10
•
OSC
310
=
Hz
R
t
f
MODE/SYNC (Pin 2): Burst Mode Select and Oscillator
Synchronization.
MODE/SYNC = High. Enable Burst Mode operation. The
inductor peak inductor current will be 1/3 the current
limit value and return to zero current on each cycle.
During Burst Mode operation the operation is variable
frequency, providing a significant efficiency improvement at light loads. It is recommended the Burst Mode
operation only be entered once the part has started up.
MODE/SYNC = Low. Disable Burst Mode operation and
maintain low noise, constant frequency operation.
MODE/SYNC = External CLK. Synchronization of the
internal oscillator and Burst Mode operation disable. A
clock pulse width of 100ns to 2μs is required to
synchronize.
VIN (Pin 3): Input Supply Pin.
SW (Pin 4): Switch Pin. Connect inductor and Schottky
diode here. For applications with output voltages over
4.3V, a Schottky diode is required to ensure that the SW
pin voltage does not exceed its absolute maximum
rating. Minimize trace length to keep EMI and high
ringing down. For discontinuous inductor current, a
controlled impedance is placed from SW to VIN from the
IC to eliminate high frequency ringing due to the resonant
tank of the inductor and SW node capacitance, therefore
reducing EMI radiation.
GND (Pin 5): Signal and Power Ground for the IC.
PGOOD (Pin 6): Power Good Comparator Output. This
open-drain output is low when VFB < –9% from its
regulation voltage.
V
(Pin 7): Output of the Synchronous Rectifier and
OUT
Bootstrapped Power Source for the IC. A ceramic capacitor of at least 1μF is required and should be located as
close to the V
FB (Pin 8): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.6V to 5V.
The feedback reference voltage is typically 1.25V.
VC (Pin 9): Error Amp Output. A frequency compensation
network is connected to this pin to compensate the loop.
See the section “Compensating the Feedback Loop” for
guidelines.
SHDN (Pin 10): Shutdown. Grounding this pin shuts down
the IC. Tie to >1V to enable (VIN or digital gate output). To
operate with input voltages below 1V once the converter
has started, a 1M resistor from SHDN to VIN and a 5M
resistor from SHDN to V
esis. During shutdown, the output voltage will hold up to
VIN minus a diode drop due to the body diode of the PMOS
synchronous switch. If the application requires a complete disconnect during shutdown, refer to the section
“Output Disconnect Circuits.”
and GND pins as possible (Pins 7 and 5).
OUT
will provide sufficient hyster-
OUT
6
3402fb
Page 7
BLOCK DIAGRA
W
LTC3402
+
1V TO
+ 0.3V
V
OUT
V
IN
3
SHDNSHUTDOWN
10
GND
5
ANTIRING
ANTICROSS
COND
CURRENT
LIMIT
PWM
LOGIC
SLEEP
SW
4
N
+
–
CURRENT
COMP
+
I
SENSE
AMP
–
2.8A TYP
–
+
+–
Σ
10mV
P
V
OUT
7
V
OUT
2.6V TO 5.5V
+
+
–
I
ZERO
AMP
+
1.25V
ERROR
AMP
–
FB
8
V
9
R1
C
POK
Burst Mode
CONTROL
R
t
1
6
N
OSC
SLOPE COMP
–
+
1.25V – 9%
MODE/SYNC
2
3402 BD
R2
3402fb
7
Page 8
LTC3402
WUUU
APPLICATIO S I FOR ATIO
DETAILED DESCRIPTION
The LTC3402 provides high efficiency, low noise power
for applications such as portable instrumentation. The
current mode architecture with adaptive slope compensation provides ease of loop compensation with excellent
transient load response. The low R
synchronous switches provide the pulse width modulation control at high efficiency.
The Schottky diode across the synchronous PMOS switch
provides a lower drop during the break-before-make time
(typically 20ns) of the NMOS to PMOS transition. The
addition of the Schottky diode will improve efficiency (see
graph “Efficiency Loss Without Schottky vs Frequency”).
While the IC’s quiescent current is a low 38μA, high
efficiency is achieved at light loads when Burst Mode
operation is entered.
Low Voltage Start-Up
The LTC3402 is designed to start up at input voltages of
typically 0.85V. The device can start up under some load,
(see graph Start-Up vs Input Voltage). Once the output
voltage exceeds a threshold of 2.3V, then the IC powers
itself from V
circuitry has no dependency on the input voltage, eliminating the requirement for a large input capacitor. The input
voltage can drop below 0.5V without affecting the operation, but the limiting factor for the application becomes the
availability of the power source to supply sufficient energy
to the output at the low voltages.
Low Noise Fixed Frequency Operation
Oscillator. The frequency of operation is set through a
resistor from the Rt pin to ground where f = 3 • 1010/Rt. An
internally trimmed timing capacitor resides inside the IC.
The oscillator can be synchronized with an external clock
inserted on the MODE/SYNC pin. When synchronizing the
oscillator, the free running frequency must be set to
approximately 30% lower than the desired synchronized
frequency. Keeping the sync pulse width below 2μs will
ensure that Burst Mode operation is disabled.
Current Sensing. Lossless current sensing converts the
peak current signal to a voltage to sum in with the internal
slope compensation. This summed signal is compared to
instead of VIN. At this point, the internal
OUT
, low gate charge
DS(ON)
the error amplifier output to provide a peak current control
command for the PWM. The slope compensation in the IC
is adaptive to the input and output voltage. Therefore, the
converter provides the proper amount of slope compensation to ensure stability and not an excess causing a loss of
phase margin in the converter.
Error Amp. The error amplifier is a transconductance
amplifier with gm = 0.1ms. A simple compensation network is placed from the V
Current Limit. The current limit amplifier will shut the
NMOS switch off once the current exceeds its threshold.
The current amplifier delay to output is typically 50ns.
Zero Current Amp. The zero current amplifier monitors the
inductor current to the output and shuts off the synchronous rectifier once the current is below 50mA, preventing
negative inductor current.
Antiringing Control. The anitringing control will place an
impedance across the inductor to damp the ringing on the
SW pin during discontinuous mode operation. The LC
ringing (L = inductor, CSW = capacitance on the switch pin)
is low energy, but can cause EMI radiation.
Burst Mode Operation
Burst Mode operation is when the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
38μA. In this mode, the output ripple has a variable
frequency component with load current and the steady
state ripple will be typically below 3%.
During the period where the device is delivering energy to
the output, the peak current will be equal to 1/6 the current
limit value and the inductor current will terminate at zero
current for each cycle. In this mode the maximum output
current is given by:
I
OUT MAXBURST
()
Burst Mode operation is user controlled by driving the
MODE/SYNC pin high to enable and low to disable. It is
recommended that Burst Mode operation be entered after
the part has started up.
pin to ground.
C
V
IN
Amps
V
•≈6
OUT
SW
3402fb
8
Page 9
WUUU
APPLICATIO S I FOR ATIO
LTC3402
COMPONENT SELECTION
Inductor Selection
The high frequency operation of the LTC3402 allows the
use of small surface mount inductors. The minimum
inductance value is proportional to the operating frequency and is limited by the following constraints:
3
L
H and L
>μ>
f
VVV
IN MINOUT MAXIN MIN
•–
()( )()
f Ripple V
••
OUT MAX
()
H
where
f = Operating Frequency (Hz)
Ripple = Allowable Inductor Current Ripple (A)
V
V
= Minimum Input Voltage (V)
IN(MIN)
OUT(MAX)
= Maximum Output Voltage (V)
The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.
The output voltage ripple has several components. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The max ripple due
to charge is given by:
IV
•
VR
BULK
=
PIN
CVf
••
OUTOUT
V
where
IP = Peak Inductor Current
The ESR can be a significant factor for ripple in most
power converters. The ripple due to capacitor ESR is
simply given by:
V
OUT
3402 F01
Figure 1. Recommended Component Placement. Traces
Carrying High Current Are Direct. Trace Area FB and VC Pins
Are Kept Low. Lead Length to Battery Should be Kept Short
For high efficiency, choose an inductor with a high frequency core material, such as ferrite, to reduce core
losses. The inductor should have low ESR (equivalent
series resistance) to reduce the I2R losses and must be
able to handle the peak inductor current without saturating. Molded chokes or chip inductors usually do not have
enough core to support the peak inductor currents in the
1A to 2A region. To minimize radiated noise, use a toroid,
pot core or shielded bobbin inductor. See Table 1 for
suggested components and Table 1 for a list of component
suppliers.
VR
CESR
= IP • R
ESR
V
where
R
= Capacitor Series Resistance
ESR
Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
series tantalum capacitors and Sanyo POSCAP or TaiyoYuden ceramic X5R or X7R type capacitors are recommended. For through-hole applications Sanyo OS-CON
capacitors offer low ESR in a small package size. See Table
2 for a list of component suppliers. In some layouts it may
be required to place a 1μF low ESR capacitor as close to the
V
The input filter capacitor reduces peak currents drawn from
the input source and reduces input switching noise. Since
the IC can operate at voltages below 0.5V once the output
is regulated, then demand on the input capacitor is much
less and in most applications a 4.7μF is recommended.
Output Diode
For applications with output voltages over 4.3V, a Schottky
diode is required to ensure that the SW pin voltage does
not exceed its absolute maximum rating. The Schottky
diode across the synchronous PMOS switch provides a
lower drop during the break-before-make time (typically
20ns) of the NMOS to PMOS transition. The Schottky
diode improves peak efficiency (see graph “Efficiency
Loss Without Schottky vs Frequency). Use of a Schottky
diode such as a MBR0520L, 1N5817 or equivalent. Since
slow recovery times will compromise efficiency, do not
use ordinary rectifier diodes.
Operating Frequency Selection
applications where physical size is the main criterion then
running the converter in this mode is acceptable. In
applications where it is preferred not to enter this mode,
then the maximum operating frequency is given by:
–
VV
OUTIN
f
MAX NOSKIP
where t
ON(MIN)
EFFICIENCY (%)
=
•
Vt
OUTON MIN_()
Hz
= minimum on time = 120ns.
100
Burst Mode
90
OPERATION
80
70
300kHz
60
50
40
30
20
10
0
0.1101001000
1
OUTPUT CURRENT (mA)
3MHz
1MHz
3402 G08
There are several considerations in selecting the operating
frequency of the converter. The first is determining the
sensitive frequency bands that cannot tolerate any spectral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz. In this
case, a 2MHz converter frequency may be employed.
The second consideration is the physical size of the
converter. As the operating frequency goes up, the inductor and filter caps go down in value and size. The trade off
is in efficiency since the switching losses due to gate
charge are going up proportional with frequency. For
example in Figure 2, for a 2.4V to 3.3V converter, the
efficiency at 100mA is 5% less at 2MHz compared to
300kHz.
Another operating frequency consideration is whether the
application can allow “pulse skipping.” In this mode, the
minimum on time of the converter cannot support the duty
cycle, so the converter ripple will go up and there will be
a low frequency component of the output ripple. In many
Figure 2. Converter Efficiency 2.4V to 3.3V
Reducing Output Capacitance with a Load Feed
Forward Signal
In many applications the output filter capacitance can be
reduced for the desired transient response by having the
device commanding the change in load current, (i.e.
system microcontroller), inform the power converter of
the changes as they occur. Specifically, a “load feed
forward” signal coupled into the VC pin gives the inner
current loop a head start in providing the change in output
current. The transconductance of the LTC3402 converter
at the VC pin with respect to the inductor current is typically
170mA/100mV, so the amount of signal injected is proportional to the anticipated change of inductor current
with load. The outer voltage loop performs the remainder
of the correction, but because of the load feed forward
signal, the range over which it must slew is greatly
reduced. This results in an improved transient response.
A logic level feed forward signal, VFF, is coupled through
components C5 and R6. The amount of feed forward
10
3402fb
Page 11
WUUU
APPLICATIO S I FOR ATIO
LTC3402
signal is attenuated with resistor R6 and is given by the
following relationship:
R
6
where ΔI
V
IN
⎛
VRV
515
•• •.
FFIN
⎜
⎝
VI
•–Δ
OUTOUT
= load current change.
OUT
LTC3402
3
V
IN
10
SHDN
2
MODE/SYNC
6
PGOOD
1
R
LOAD FEED
FORWARD
SIGNAL
t
V
GND
SW
OUT
V
V
FB
C
FF
⎞
⎟
⎠
4
7
8
9
5
3.3nF
R6
Figure 3
R
5≈
V
OUT
C3
R5
C5
3402 F03
Closing the Feedback Loop
The LTC3402 used current mode control with internal
adaptive slope compensation. Current mode control eliminates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, and simplifies it to a single-pole filter response. The product of the
modulator control to output DC gain plus the error amp
open-loop gain equals the DC gain of the system.
GDC = G
G
CONTROL
CONTROLOUTPUT
2•
=
I
OUT
• G
V
IN
, GEA ≈ 2000
EA
The output filter pole is given by:
I
f
FILTERPOLE
=
OUT
VC
π ••
OUTOUT
Hz
The output filter zero is given by:
f
FILTERZERO
where R
=
2• ••π
is the capacitor equivalent series resistance.
ESR
1
RC
ESROUT
Hz
A troublesome feature of the boost regulator topology is
the right half plane zero (RHP) and is given by:
2
VR
=
INO
2π
LV
Hz
2
O
f
RHPZ
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
The typical error amp compensation is shown in Figure 4.
The equations for the loop dynamics are as follows:
f
POLE
≈
1
22010
•• ••
1
π
6
Hz
C
C
1
whichis extremely closeto DC
f
ZERO
f
POLE
=
1
2
≈
2
2
1
RC
•• •
π
ZC
1
RC
•• •
π
ZC
Hz
1
Hz
2
Refer to AN76 for more closed-loop examples.
V
OUT
R1
R2
C
C2
3402 F04
ERROR
AMP
+
–
1.25V
FB
8
V
C
9
Figure 4
C
C1
R
Z
where C
is the output filter capacitor.
OUT
3402fb
11
Page 12
LTC3402
UU
OUTPUT DISCO ECT CIRCUITS
Single Cell Output Disconnect
VIN = 0.9V TO 1.5V
3
V
IN
10
SHDN
2
MODE/SYNC
6
PGOOD
1
R
t
*SET RB TO FORCE BETA OF ≤100; RB =
0 = FIXED FREQUENCY
1 = Burst Mode OPERATION
Dual Cell Output Disconnect Allowing Full Load Start-Up
LTC3402
V
GND
SW
OUT
V
ZETEX
FMMT717
4
7
8
FB
9
C
5
– V
(V
OUT
– 0.7V) • 100
INMIN
I
OUTMAX
RB*
3402 TA03
V
C5
1μF
OUT
VIN = 1.8V TO 3V
R7
1M
0 = FIXED FREQUENCY
1 = Burst Mode OPERATION
3
V
IN
10
SHDN
2
MODE/SYNC
6
PGOOD
1
R
t
LTC3402
SW
V
OUT
GND
IRLML6401
4
7
8
FB
9
V
C
5
RG
1M
2N2222
3402 TA04
V
C5
1μF
OUT
3402fb
12
Page 13
TYPICAL APPLICATIO S
LTC3402
U
Single Cell to 3V at 500mA, All Ceramic Capacitor, 3MHz Step-Up Converter
*LOCATE COMPONENTS AS CLOSE TO
IC AS POSSIBLE
C1: TAIYO YUDEN JMK212BJ475MG
C2: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120T3
L1: SUMIDA CDH53-100
D1*
4
7
8
FB
9
V
C
C3
470pF
5
R5
82k
1.65M
C4
4.7pF
Efficiency
100
V
OUT
5V
600mA
R2
C2*
R1
549k
22μF
3402 TA07a
EFFICIENCY (%)
Burst Mode OPERATION
90
80
70
60
50
40
30
20
10
VIN = 3.6V
0
0.1
1MHz
FIXED
FREQUENCY
110
LOAD CURRENT (mA)
100
1000
3402 G10
3402fb
13
Page 14
LTC3402
TYPICAL APPLICATIO S
High Efficiency, Compact CCFL Supply with Remote Dimming
CCFL BACKLIGHT APPLICATION CIRCUITS
CONTAINED IN THIS DATA SHEET ARE
COVERED BY U.S. PATENT NUMBER 5408162
AND OTHER PATENTS PENDING
R3
1k
DIMMING
INPUT
0V TO 2.5V
3402 TA06
14
3402fb
Page 15
PACKAGE DESCRIPTION
U
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
LTC3402
5.23
(.206)
MIN
0.305 ± 0.038
(.0120 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
GAUGE PLANE
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3.20 – 3.45
(.126 – .136)
DETAIL “A”
DETAIL “A”
0.50
(.0197)
BSC
° – 6° TYP
0
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
4.90 ± 0.152
(.193 ± .006)
0.17 – 0.27
(.007 – .011)
TYP
1.10
(.043)
MAX
12
0.50
(.0197)
BSC
0.497 ± 0.076
7
6
45
(.0196 ± .003)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
8910
3
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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