The LTC®2051/LTC2052 are dual/quad zero-drift operational amplifiers available in the MS8 and SO-8/GN16 and
S14 packages. For space limited applications, the LTC2051
is available in a 3mm × 3mm × 0.8mm dual fine pitch
leadless package (DFN). They operate from a single 2.7V
supply and support ±5V applications. The current consumption is 750μA per op amp.
The LTC2051/LTC2052, despite their miniature size, feature uncompromising DC performance. The typical input
offset voltage and offset drift are 0.5μV and 10nV/°C. The
almost zero DC offset and drift are supported with a power
supply rejection ratio (PSRR) and common mode rejection ratio (CMRR) of more than 130dB.
The input common mode voltage ranges from the negative
supply up to typically 1V from the positive supply. The
LTC2051/LTC2052 also have an enhanced output stage
capable of driving loads as low as 2kΩ to both supply rails.
The open-loop gain is typically 140dB. The LTC2051/
LTC2052 also feature a 1.5μV
3MHz gain-bandwidth product.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
DC to 10Hz noise and a
P-P
U
TYPICAL APPLICATIO
High Performance Low Cost Instrumentation Amplifier
PART NUMBERAMPS/PACKAGESPECIFIED TEMP RANGESPECIFIED VOLTAGEPACKAGE
LTC2051CDD20°C to 70°C3V, 5V DD
LTC2051CS820°C to 70°C3V, 5VSO-8
LTC2051CMS820°C to 70°C3V, 5V8-Lead MSOP
LTC2051CMS1020°C to 70°C3V, 5V10-Lead MSOP
LTC2051HVCDD20°C to 70°C3V, 5V, ±5VDD
LTC2051HVCS820°C to 70°C3V, 5V, ±5VSO-8
LTC2051HVCMS820°C to 70°C3V, 5V, ±5V8-Lead MSOP
LTC2051HVCMS1020°C to 70°C3V, 5V, ±5V10-Lead MSOP
LTC2051IDD2–40°C to 85°C3V, 5V DD
LTC2051IS82–40°C to 85°C3V, 5VSO-8
LTC2051IMS82–40°C to 85°C3V, 5V8-Lead MSOP
LTC2051IMS102–40°C to 85°C3V, 5V10-Lead MSOP
LTC2051HVIDD2–40°C to 85°C3V, 5V, ±5VDD
LTC2051HVIS82–40°C to 85°C3V, 5V, ±5VSO-8
LTC2051HVIMS82–40°C to 85°C3V, 5V, ±5V8-Lead MSOP
LTC2051HVIMS102–40°C to 85°C3V, 5V, ±5V10-Lead MSOP
LTC2051HS82–40°C to 125°C3V, 5VSO-8
LTC2051HMS82–40°C to 125°C3V, 5V8-Lead MSOP
LTC2051HVHS82–40°C to 125°C3V, 5V, ±5VSO-8
LTC2051HVHMS82–40°C to 125°C3V, 5V, ±5V8-Lead MSOP
LTC2052CS40°C to 70°C3V, 5V14-Lead SO
LTC2052CGN40°C to 70°C3V, 5V16-Lead SSOP
LTC2052HVCS40°C to 70°C3V, 5V, ±5V14-Lead SO
LTC2052HVCGN40°C to 70°C3V, 5V, ±5V16-Lead SSOP
20512fd
3
LTC2051/LTC2052
U
AVAILABLE OPTIO S
PART NUMBERAMPS/PACKAGESPECIFIED TEMP RANGESPECIFIED VOLTAGEPACKAGE
LTC2052IS4–40°C to 85°C3V, 5V14-Lead SO
LTC2052IGN4–40°C to 85°C3V, 5V16-Lead SSOP
LTC2052HVIS4–40°C to 85°C3V, 5V, ±5V14-Lead SO
LTC2052HVIGN4–40°C to 85°C3V, 5V, ±5V16-Lead SSOP
LTC2052HS4–40°C to 125°C3V, 5V14-Lead SO
LTC2052HGN4–40°C to 125°C3V, 5V16-Lead SSOP
LTC2052HVHS4–40°C to 125°C3V, 5V, ±5V14-Lead SO
LTC2052HVHGN4–40°C to 125°C3V, 5V, ±5V16-Lead SSOP
ELECTRICAL CHARACTERISTICS
(LTC2051/LTC2052, LTC2051HV/LTC2052HV) The ● denotes the
specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 3V, 5V
unless otherwise noted. (Note 3)
LTC2051C/LTC2052C
PARAMETERCONDITIONSMINTYPMAXMINTYPMAXUNITS
Input Offset Voltage(Note 2)±0.5±3±0.5±3μV
Average Input Offset Drift(Note 2)●0.01±0.030.01±0.05μV/°C
Long-Term Offset Drift5050nV/√mo
Input Bias Current (Note 4)VS = 3V±8±50±8±50pA
Input Offset Current (Note 4)VS = 3V±100±100pA
Input Noise VoltageRS = 100Ω, DC to 10Hz1.51.5μV
Common Mode Rejection RatioVCM = GND to V+ – 1.3,115130115130dB
Power Supply Rejection Ratio120130120130dB
Large-Signal Voltage GainRL = 10k, VS = 3V120140120140dB
Output Voltage Swing HighRL = 2k to GND●V+ – 0.15 V+ – 0.06V+ – 0.15 V+ – 0.06V
Output Voltage Swing LowRL = 2k to GND●215215 mV
Slew Rate22V/μs
Gain Bandwidth Product33MHz
Supply Current (Per Amplifier)No Load, VS = 3V, V
Supply Current, ShutdownV
= 3V●±100±3000pA
V
S
VS = 5V±25±75±25±75pA
VS = 5V●±150±3000pA
= 3V●±150±700pA
V
S
VS = 5V±150±150pA
= 5V●±200±700pA
V
S
VS = 3V●110130110130dB
VCM = GND to V+ – 1.3,120130120130dB
specifications which apply over the full operating temperature range, otherwise specifications are at T
(LTC2051/LTC2052, LTC2051HV/LTC2052HV) The ● denotes the
= 25°C. VS = 3V, 5V
A
unless otherwise noted. (Note 3)
LTC2051C/LTC2052C
LTC2051I/LTC2052ILTC2051H/LTC2052H
PARAMETERCONDITIONSMINTYPMAXMINTYPMAXUNITS
Shutdown Pin Input Low Voltage (VIL)●V– + 0.5V– + 0.5V
Shutdown Pin Input High Voltage (V
Shutdown Pin Input CurrentV
Internal Sampling Frequency7.57.5kHz
)●V+ – 0.5V+ – 0.5V
IH
= VIL, VS = 3V●–1–3–1–3μA
SHDN
= VIL, VS = 5V●–2–5–2–5μA
V
SHDN
(LTC2051HV/LTC2052HV) The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
PARAMETERCONDITIONSMINTYPMAXMINTYPMAXUNITS
Input Offset Voltage(Note 2)±1±3±1±3μV
Average Input Offset Drift(Note 2)●0.01±0.030.01±0.05μV/°C
Long-Term Offset Drift5050nV/√mo
Input Bias Current (Note 4)±90±150±90±150pA
Input Offset Current (Note 4)±300±300pA
Input Noise VoltageRS = 100Ω, DC to 10Hz1.51.5μV
Common Mode Rejection RatioVCM = V– to V+ – 1.3125130125130dB
Power Supply Rejection Ratio120130120130dB
Large-Signal Voltage GainRL = 10k125140125140dB
Maximum Output Voltage SwingRL = 2k to GND●±4.75±4.92±4.50±4.92V
Slew Rate22V/μs
Gain Bandwidth Product33MHz
Supply Current (Per Amplifier)No Load, V
Supply Current, ShutdownV
Shutdown Pin Input Low Voltage (VIL)●V– + 0.5V– + 0.5V
Shutdown Pin Input High Voltage (VIH)●V+ – 0.5V+ – 0.5V
Shutdown Pin Input CurrentV
Internal Sampling Frequency7.57.5kHz
= 25°C. VS = ±5V unless otherwise noted. (Note 3)
A
●±300±3000pA
●±500±700pA
●120130120130dB
●115130115130dB
●120140120140dB
= 10k to GND●±4.90±4.98±4.85±4.98V
R
L
SHDN
SHDN
= V
= V
SHDN
IL
IL
= V
IH
●11.511.5mA
●15301530μA
●–7–15–7–15μA
LTC2051C/LTC2052C
LTC2051I/LTC2052ILTC2051H/LTC2052H
P-P
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: These parameters are guaranteed by design. Thermocouple effects
preclude measurements of these voltage levels during automated testing.
Note 3: All versions of the LTC2051/LTC2052 are designed, characterized
and expected to meet the extended temperature limits of –40°C and 125°C.
The LTC2051C/LTC2052C/LTC2051HVC/LTC2052HVC are guaranteed to
meet the temperature limits of 0°C and 70°C. The LTC2051I/LTC2052I/
LTC2051HVI/LTC2052HVI are guaranteed to meet temperature limits of –
40°C and 85°C. The LTC2051H/LTC2051HVH and LTC2052H/LTC2052HVH
are guaranteed to meet the temperature limits of –40°C and 125°C.Note 4: The bias current measurement accuracy depends on the proximity of
the negative supply bypass capacitors to the device under test. Because of
this, only the bias current of channel B (LTC2051) and channels A and B
(LTC2052) are 100% tested to the data sheet specifications. The bias
currents of the remaining channels are 100% tested to relaxed limits,
however, their values are guaranteed by design to meet the data sheet limits.
Note 5: This parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.
Note 6: The θ
spreading metal. Using expanded metal area on all layers of a board
reduces this value.
specified for the DD package is with minimal PCB heat
JA
20512fd
5
LTC2051/LTC2052
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Common Mode Rejection Ratio
vs Frequency
140
120
100
80
60
CMRR (dB)
40
20
0
11001k100k
1010k
FREQUENCY (Hz)
VS = 3V OR ±5V
= 0.5V
V
CM
Output Voltage Swing
vs Load Resistance
6
RL TO GND
5
4
3
2
OUTPUT SWING (V)
1
0
0
246
LOAD RESISTANCE (kΩ)
= 5V
V
S
= 3V
V
S
DC CMRR
vs Common Mode Input RangePSRR vs Frequency
120
100
–PSRR
80
60
PSRR (dB)
40
20
0
101k10k1M
+PSRR
100
FREQUENCY (Hz)
100k
20512 G03
P-P
20512 G01
140
120
100
80
60
CMRR (dB)
40
20
0
0
VS = 10V
VS = 3V
2410
VS = 5V
68
VCM (V)
20512 G02
Output Swing
Output Swing vs Output Current
6
5
4
3
2
OUTPUT VOLTAGE (V)
1
0
10
8
20512 G04
0.01
VS = 5V
VS = 3V
0.1110
OUTPUT CURRENT (mA)
20512 G05
vs Load Resistance ±5V
5
4
RL TO GND
3
2
1
0
–1
–2
OUTPUT VOLTAGE (V)
–3
–4
–5
2
0
LOAD RESISTANCE (kΩ)
6
8
4
10
20512 G06
Output Swing
vs Output Current, ±5V Supply
5
4
R
TO GND
L
3
2
1
0
–1
OUTPUT SWING (V)
–2
–3
–4
–5
0.01
0.1
OUTPUT CURRENT (mA)
6
Gain/Phase vs Frequency
100
80
60
40
20
GAIN (dB)
0
VS = 3V OR ±5V
–20
= 50pF
C
L
= 100k
R
L
1
20512 G07
–40
10
1k1M
10010k100k10M
FREQUENCY (Hz)
PHASE
GAIN
20512 G08
80
100
PHASE (DEG)
120
140
160
180
200
Bias Current vs Temperature
10k
1k
100
BIAS CURRENT (pA)
10
1
–5050100 125
VS = ±5V
VS = 5V
VS = 3V
0
TEMPERATURE (°C)
20512 G09
20512fd
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current
vs Input Common Mode Voltage
250
200
Transient Response
LTC2051/LTC2052
Input Overload Recovery
0
–0.1
INPUT (V)
150
100
INPUT BIAS CURRENT (pA)
50
0
–3
–5
–10
INPUT COMMON MODE VOLTAGE (V)
SAMPLING FREQUENCY (kHz)
VS = ±5V
= 5V
V
S
V
= 3V
S
1
3
20512 G10
Sampling Frequency
vs Supply Voltage
10
9
8
7
6
5
3
5
SUPPLY VOLTAGE (V)
2V/DIV
AV = 1
= 10k
R
L
C
= 100pF
L
= ±5V
V
5
S
1μs/DIV
20512 G11
1.5
OUTPUT (V)
0
AV = –100
R
L
C
L
V
S
= 100k
= 10pF
= 3V
500μs/DIV
2050 G12
Sampling Frequency
vs Temperature
10
9
8
7
SAMPLING FREQUENCY (kHz)
6
7
9
11
20512 G13
5
–50
VS = ±5V
V
= 3V
S
0
TEMPERATURE (°C)
50
100
20512 G14
125
Supply Current (Per Amplifier)
vs Supply Voltage
1.2
1.0
0.8
0.6
0.4
SUPPLY CURRENT (mA)
0.2
0
2.5
4.56.58.510.5
SUPPLY VOLTAGE (V)
20512 G15
Supply Current (Per Amplifier)
vs Temperature
1.2
1.0
0.8
0.6
0.4
SUPPLY CURRENT (mA)
0.2
0
–50
0
TEMPERATURE (°C)
50
VS = ±5V
VS = 5V
VS = 3V
100
20512 G16
125
20512fd
7
LTC2051/LTC2052
WUUU
APPLICATIO S I FOR ATIO
Shutdown
The LTC2051 includes a shutdown pin in the 10-lead
MSOP. When this active low pin is high or allowed to float,
the device operates normally. When the shutdown pin is
pulled low, the device enters shutdown mode; supply
current drops to 3μA, all clocking stops and the output
assumes a high impedance state.
Clock Feedthrough, Input Bias Current
The LTC2051/LTC2052 use autozeroing circuitry to achieve
an almost zero DC offset over temperature, common
mode voltage and power supply voltage. The frequency of
the clock used for autozeroing is typically 7.5kHz. The
term clock feedthrough is broadly used to indicate visibility of this clock frequency in the op amp output spectrum.
There are typically two types of clock feedthrough in
autozeroed op amps like the LTC2051/LTC2052.
The first form of clock feedthough is caused by the settling
of the internal sampling capacitor and is input referred;
that is, it is multiplied by the closed-loop gain of the op
amp. This form of clock feedthrough is independent of the
magnitude of the input source resistance or the magnitude
of the gain setting resistors. The LTC2051/LTC2052 have
a residue clock feedthrough of less than 1μV
referred at 7.5kHz.
RMS
input
To reduce this form of clock feedthrough, use smaller
valued gain setting resistors and minimize the source
resistance at the input. If the resistance seen at the inputs
is less than 10k, this form of clock feedthrough is less
than 1μV
amount of residue clock feedthrough from the first form
previously described.
Placing a capacitor across the feedback resistor reduces
either form of clock feedthrough by limiting the bandwidth
of the closed-loop gain.
Input bias current is defined as the DC current into the
input pins of the op amp. The same current spikes that
cause the second form of clock feedthrough
described
current of the op amp below 70°C.
At temperatures above 70°C, the leakage of the ESD
protection diodes on the inputs increase the input bias
currents of both inputs in the positive direction, while the
current caused by the charge injection stays relatively
constant. At elevated temperatures (above 85°C) the
leakage current begins to dominate and both the negative
and positive pin’s input bias currents are in the positive
direction (into the pins).
Input Pins, ESD Sensitivity
input referred at 7.5kHz, or less than the
RMS
previously
, when averaged, dominate the DC input bias
The second form of clock feedthrough is caused by the
small amount of charge injection occurring during the
sampling and holding of the op amps input offset voltage.
The current spikes are multiplied by the impedance seen
at the input terminals of the op amp, appearing at the
output multiplied by the closed-loop gain of the op amp.
U
TYPICAL APPLICATIO
The dual chopper op amp buffers the inputs of A1 and
corrects its offset voltage and offset voltage drift. With the
RC values shown, the power-up warm-up time is typically
20 seconds. The step response of the composite amplifier
does not present settling tails. The LT®1677 should be
used when extremely low noise, VOS and VOS drift are
8
ESD voltages above 700V on the input pins of the op amp
will cause the input bias currents to increase (more DC
current into the pins). At these voltages, it is possible to
damage the device to a point where the input bias current
exceeds the maximums specified in this data sheet.
needed and the input source resistance is low. (For instance a 350Ω strain gauge bridge.) The LT1012 or
equivalent should be used when low bias current (100pA)
is also required in conjunction with DC to 10Hz low noise,
low VOS and VOS drift. The measured typical input offset
voltages are less than 1μV.
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
(4 SIDES)
0.75 ±0.05
TYP
2.38 ±0.10
(2 SIDES)
85
14
0.50 BSC
0.38 ± 0.10
3.5 ±0.05
0.675 ±0.05
1.65 ±0.05
(2 SIDES)2.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.38 ±0.05
(2 SIDES)
0.50
BSC
(DD) DFN 1203
0.2μV
0.4μV
P-P
P-P
20512fd
9
LTC2051/LTC2052
U
PACKAGE DESCRIPTIO
(Reference LTC DWG # 05-08-1660)
DETAIL “A”
0.254
(.010)
GAUGE PLANE
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
° – 6° TYP
0
DETAIL “A”
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
(.043)
0.22 – 0.38
(.009 – .015)
TYP
1.10
MAX
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
3.00 ± 0.102
(.118 ± .004)
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
(NOTE 3)
4.90
± 0.152
(.193 ± .006)
8
7
12
0.52
(.0205)
6
5
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4
3
5.23
(.206)
MIN
0.42 ± 0.038
(.0165 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.889
(.035 ± .005)
3.20 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
MSOP (MS8) 0204
± 0.127
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
SEATING
PLANE
4.90 ± 0.152
(.193 ± .006)
0.17 – 0.27
(.007 – .011)
TYP
1.10
(.043)
MAX
DETAIL “A”
0.254
(.010)
GAUGE PLANE
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0
DETAIL “A”
° – 6° TYP
0.53 ± 0.152
(.021 ± .006)
12
0.50
(.0197)
BSC
8910
7
6
45
3
0.497 ± 0.076
(.0196 ± .003)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
5.23
(.206)
MIN
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.889 ± 0.127
(.035 ± .005)
3.20 – 3.45
(.126 – .136)
0.50
(.0197)
RECOMMENDED SOLDER PAD LAYOUT
BSC
MSOP (MS) 0603
10
20512fd
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.010 – .020
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.007 – .0098
(0.178 – 0.249)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
.016 – .050
(0.406 – 1.270)
INCHES
(MILLIMETERS)
.016 – .050
(0.406 – 1.270)
INCHES
(MILLIMETERS)
0°– 8° TYP
.015 ± .004
(0.38 ± 0.10)
0° – 8° TYP
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
× 45°
.008 – .012
(0.203 – 0.305)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.0532 – .0688
(1.35 – 1.75)
(0.102 – 0.249)
.0250
(0.635)
BSC
.004 – .0098
.228 – .244
(5.791 – 6.197)
.229 – .244
(5.817 – 6.198)
(4.801 – 5.004)
8
1
16
12
.189 – .197
NOTE 3
7
2
.189 – .196*
(4.801 – 4.978)
15
14
3
LTC2051/LTC2052
5
6
3
13
4
12 11 10
5
678
4
9
.150 – .157
(3.810 – 3.988)
NOTE 3
.030 ±.005
.009
(0.229)
REF
.150 – .157**
(3.810 – 3.988)
.050 BSC
.245
MIN
TYP
RECOMMENDED SOLDER PAD LAYOUT
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.160 ±.005
SO8 0303
.045 ±.005
.150 – .165
.0250 BSC.0165 ±.0015
GN16 (SSOP) 0204
14-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.050 BSC
N
.245
MIN
123N/2
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
× 45°
.016 – .050
(0.406 – 1.270)
INCHES
(MILLIMETERS)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
.045 ±.005
.160 ±.005
(5.791 – 6.197)
0° – 8° TYP
S Package
.228 – .244
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.337 – .344
(8.560 – 8.738)
13
14
N
1
NOTE 3
12
11
10
3
2
4
.050
(1.270)
BSC
5
8
9
.150 – .157
(3.810 – 3.988)
NOTE 3
N/2
7
6
.004 – .010
(0.101 – 0.254)
S14 0502
20512fd
11
LTC2051/LTC2052
TYPICAL APPLICATIO
U
Paralleling Amplifiers to Improve Noise
R2
R1
2
–
1/4 LTC2052
3
+
R
1
R
R2
R1
V
IN
V
OUT
V
IN
6
–
1/4 LTC2052
5
+
R2
R1
9
–
1/4 LTC2052
10
+
R2
= 3; INPUT DC – 10Hz NOISE ≅ 0.8μV
R1
R
7
R
8
P-P
=
5V
0.1μF
13
12
NOISE OF EACH PARALLEL OP AMP
4
–
1/4 LTC2052
+
11
–5V
14
0.1μF
√3
20512 F02
V
OUT
RELATED PARTS
PART NUMBERDESCRIPTIONCOMMENTS
LTC1051/LTC1053 Precision Zero-Drift Op AmpDual/Quad
LTC1151±15V Zero-Drift Op AmpDual High Voltage Operation ±18V
LTC1152Rail-to-Rail Input and Output Zero-Drift Op AmpSingle Zero-Drift Op Amp with Rail-to-Rail Input and Output and Shutdown
LTC2050Zero-Drift Op Amp in SOT-23Single Supply Operation 2.7V to ±5V, Shutdown
LTC2053Zero-Drift Precision Instrumentation AmpMS8, 116dB CMRR, Two External Resistors Set Gain
LTC6800Rail-to-Rail Input and Output Instrumentation AmpLow Cost, MS8, Two External Resistors Set Gain