Page 1
FEATURES
LTC1661
Micropower Dual
10-Bit DAC in MSOP
U
DESCRIPTIO
■
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Board Space of an SO-8
■
Micropower: 60µA per DAC
Sleep Mode: 1µA for Extended Battery Life
■
Rail-to-Rail Voltage Outputs Drive 1000pF
■
Wide 2.7V to 5.5V Supply Range
■
Double Buffered for Independent or Simultaneous
DAC Updates
■
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
■
Reference Input Has Constant Impedance over All
Codes (260kΩ Typ)—Eliminates External Buffers
■
3-Wire Serial Interface with
Schmitt Trigger Inputs
■
Differential Nonlinearity: ≤±0.75LSB Max
U
APPLICATIO S
■
Mobile Communications
■
Digitally Controlled Amplifiers and Attenuators
■
Portable Battery-Powered Instruments
■
Automatic Calibration for Manufacturing
■
Remote Industrial Devices
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC®1661 integrates two accurate, serially addressable, 10-bit digital-to-analog converters (DACs) in a
single tiny MS8 package. Each buffered DAC draws just
60µA total supply current, yet is capable of supplying DC
output currents in excess of 5mA and reliably driving
capacitive loads up to 1000pF. Sleep mode further reduces total supply current to a negligible 1µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external
form factor. The double-buffered input logic provides
simultaneous update capability and can be used to write to
either DAC without interrupting Sleep mode.
Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1661 ideal for
battery-powered applications, while its straightforward
usability, high performance and wide supply range make
it an excellent choice as a general purpose converter.
For additional outputs and even greater board density,
please refer to the LTC1660 micropower octal DAC for
10-bit applications. For 8-bit applications, please consult
the LTC1665 micropower octal DAC.
W
BLOCK DIAGRA
V
OUT A
GND
8 5
7
10-BIT
DAC A
1 4
CS/LD
LATCH
CONTROL
LOGIC
2
SCK
LATCH
SHIFT REGISTER
LATCH
ADDRESS
DECODER
LATCH
V
10-BIT
DAC B
D
V
CC
6
3
OUT B
REF
IN
1661 BD
Differential Nonlinearity (DNL)
0.75
0.60
0.40
0.20
0
LSB
–0.20
–0.40
–0.60
–0.75
0 256 512 768 1023
CODE
1661 G02
1
Page 2
LTC1661
1
2
3
4
8
7
6
5
TOP VIEW
CS/LD
SCK
D
IN
REF
V
OUT A
GND
V
CC
V
OUT B
N8 PACKAGE
8-LEAD PLASTIC DIP
A
W
O
LUTEXI TIS
S
A
WUW
U
ARB
G
(Note 1)
VCC to GND.............................................. –0.3V to 7.5V
Logic Inputs to GND ................................ –0.3V to 7.5V
V
OUT A
, V
, REF to GND............–0.3V to VCC + 0.3V
OUT B
Maximum Junction Temperature......................... 125°C
Storage Temperature Range................ –65°C to 150°C
WU
/
PACKAGE
CS/LD
SCK
D
IN
REF
8-LEAD PLASTIC MSOP
T
JMAX
Consult factory for Military grade parts.
O
RDER I FOR ATIO
TOP VIEW
1
2
3
4
MS8 PACKAGE
= 125°C, θJA = 150°C/W
ORDER PART
NUMBER
8
V
OUT A
7
GND
6
V
CC
V
5
OUT B
LTC1661CMS8
LTC1661IMS8
MS8 PART MARKING
LTDV
LTDW
Operating Temperature Range
LTC1661C ............................................. 0°C to 70°C
LTC1661I........................................... –40°C to 85°C
Lead Temperature (Soldering, 10 sec)................ 300°C
U
ORDER PART
NUMBER
LTC1661CN8
LTC1661IN8
T
= 125°C, θJA = 100°C/W
JMAX
LECTRICAL C CHARA TERIST
E
ICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Accuracy
Resolution ● 10 Bits
Monotonicity 1V ≤ V
DNL Differential Nonlinearity 1V ≤ V
INL Integral Nonlinearity 1V ≤ V
V
OS
FSE Full-Scale Error VCC = 5V, V
PSR Power Supply Rejection V
Reference Input
I
REF
Power Supply
V
CC
I
CC
2
Offset Error Measured at Code 20 ● ±5 ±30 mV
VOS Temperature Coefficient ±15 µV/°C
Full-Scale Error Temperature Coefficient ±30 µV/°C
Input Voltage Range ● 0V
Resistance Active Mode ● 140 260 kΩ
Capacitance ● 15 pF
Reference Current Sleep Mode ● 0.001 1 µA
Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current VCC = 5V (Note 3) ● 120 195 µA
The ● denotes the specifications which apply over the full operating
≤ VCC, V
REF
≤ VCC – 0.1V (Note 2) ● 10 Bits
REF
≤ VCC – 0.1V (Note 2) ● ±0.1 ±0.75 LSB
REF
≤ VCC – 0.1V (Note 2) ● ±0.4 ±2 LSB
REF
= 4.096V ● ±1 ±12 LSB
REF
= 2.5V 0.18 LSB/V
REF
= 3V (Note 3) ● 95 154 µA
V
CC
Sleep Mode (Note 3)
Unloaded unless otherwise noted.
OUT
CC
● 13µA
V
Page 3
LTC1661
LECTRICAL C CHARA TERIST
E
ICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Performance
Short-Circuit Current Low V
Short-Circuit Current High V
AC Performance
Voltage Output Slew Rate Rising (Notes 4, 5) 0.60 V/µs
Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 µs
Capacitive Load Driving 1000 pF
Digital I/O
V
IH
V
IL
I
LK
C
IN
Digital Input High Voltage VCC = 2.7V to 5.5V ● 2.4 V
Digital Input Low Voltage VCC = 4.5V to 5.5V ● 0.8 V
Digital Input Leakage VIN = GND to V
Digital Input Capacitance (Note 6) ● 10 pF
The ● denotes the specifications which apply over the full operating
≤ VCC, V
REF
= 0V, VCC = V
OUT
= VCC = V
OUT
Falling (Notes 4, 5) 0.25 V/µs
= 2.7V to 3.6V ● 2.0 V
V
CC
= 2.7V to 5.5V ● 0.6 V
V
CC
= 5V, Code = 1023 ● 10 25 100 mA
REF
= 5V, Code = 0 ● 7 19 120 mA
REF
CC
Unloaded unless otherwise noted.
OUT
● ±10 µA
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 4.5V to 5.5V
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
9
t
11
VCC = 2.7V to 5.5V
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
9
t
11
DIN Valid to SCK Setup ● 40 15 ns
DIN Valid to SCK Hold ● 0–10 ns
SCK High Time (Note 6) ● 30 14 ns
SCK Low Time (Note 6) ● 30 14 ns
CS/LD Pulse Width (Note 6) ● 80 27 ns
LSB SCK High to CS/LD High (Note 6) ● 30 2 ns
CS/LD Low to SCK High (Note 6) ● 20 –21 ns
SCK Low to CS/LD Low (Note 6) ● 0–5 ns
CS/LD High to SCK Positive Edge (Note 6) ● 20 0 ns
SCK Frequency Square Wave (Note 6) ● 16.7 MHz
DIN Valid to SCK Setup (Note 6) ● 60 20 ns
DIN Valid to SCK Hold (Note 6) ● 0–10 ns
SCK High Time (Note 6) ● 50 15 ns
SCK Low Time (Note 6) ● 50 15 ns
CS/LD Pulse Width (Note 6) ● 100 30 ns
LSB SCK High to CS/LD High (Note 6) ● 50 3 ns
CS/LD Low to SCK High (Note 6) ● 30 –14 ns
SCK Low to CS/LD Low (Note 6) ● 0–5 ns
CS/LD High to SCK Positive Edge (Note 6) ● 30 0 ns
SCK Frequency Square Wave (Note 6) ● 10 MHz
The ● denotes the specifications which apply over the full operating temperature
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1023 (full scale). See Applications Information.
3
Page 4
LTC1661
UW
TI I G CHARACTERISTICS
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = V
i.e., codes k = 102 and k = 922.
Note 6: Guaranteed by design and not subject to test.
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
2.0
1.5
1.0
0.5
0
LSB
–0.5
–1.0
–1.5
–2.0
0 256 512 768 1023
CODE
1661 G01
0.75
0.60
0.40
0.20
0
LSB
–0.20
–0.40
–0.60
–0.75
0 256 512 768 1023
CODE
= 5V. DAC switched between 0.1VFS and 0.9VFS,
REF
Minimum Supply Headroom vs
Load Current (Output Sourcing)
1400
V
= 4.096V
REF
1661 G02
1200
1000
(mV)
OUT
– V
CC
V
800
600
400
200
0
< 1LSB
∆V
OUT
CODE = 1023
0246810
|
I
|
(mA) (Sourcing)
OUT
125°C
25°C
–55°C
1661 G03
Minimum V
OUT
vs
Load Current (Output Sinking)
1400
VCC = 5V
1200
CODE = 0
1000
800
(mV)
OUT
600
V
400
200
0
0246810
|
I
|
(mA) (Sinking)
OUT
125°C
25°C
–55°C
1661 G04
Midscale Output Voltage vs
Load Current
3
V
= V
REF
2.9
2.8
2.7
2.6
(V)
2.5
OUT
V
2.4
2.3
2.2
2.1
2
–30 –20 –10 0 10 20 30
CC
CODE = 512
VCC = 5.5V
VCC = 5V
VCC = 4.5V
I
(mA)
OUT
SINKSOURCE
1661 G05
Midscale Output Voltage vs
Load Current
2
V
= V
REF
1.9
1.8
1.7
1.6
(V)
1.5
OUT
V
1.4
1.3
1.2
1.1
1
–15 –4–8–12 0 4 8 12 15
CC
CODE = 512
VCC = 3.6V
VCC = 3V
VCC = 2.7V
I
OUT
SINKSOURCE
(mA)
1661 G06
4
Page 5
UW
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
SUPPLY CURRENT (µA)
1661 G11
150
140
130
120
110
100
90
80
70
60
50
VCC = 5.5V
V
REF
= V
CC
CODE = 1023
VCC = 4.5V
VCC = 3.6V
VCC = 2.7V
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1661
Load Regulation vs
Output Current
2
VCC = V
CODE = 512
1.5
1
0.5
(LSB)
0
OUT
–0.5
∆V
–1
–1.5
–2
–2 –1 0 1 2
REF
= 5V
I
OUT
SINKSOURCE
(mA)
Supply Current vs
Logic Input Voltage Supply Current vs Temperature
1.0
0.8
0.6
1661 G07
ALL DIGITAL INPUTS
SHORTED TOGETHER
Load Regulation vs
Output Current
2
VCC = V
CODE = 512
1.5
1
0.5
(LSB)
0
OUT
–0.5
∆V
–1
–1.5
–2
–500 0 500
REF
= 3V
I
OUT
SINKSOURCE
(µA)
1661 G08
Large-Signal Step Response
5
4
3
(V)
OUT
V
2
1
CODE = 102
0
0 20406080100
CODE = 922
TIME (µs)
VCC= V
= 5V
REF
10% TO
90% STEP
1661 G09
0.4
SUPPLY CURRENT (mA)
0.2
0
012345
UWW
TI I G DIAGRA
SCK
D
IN
CS/LD
LOGIC INPUT VOLTAGE (V)
t
9
t
5
t
1
t
2
A3 A2
t
7
1661 G10
t
t
3
4
A1 X1
t
6
t
11
X0
1661 TD
5
Page 6
LTC1661
PIN FUNCTIONS
UUU
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D
into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the Control
code, A3-A0, is (are) performed. CMOS and TTL compatible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 3): Serial Interface Data Input. Input word data on
the DIN pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
IN
UU
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆V
Where ∆V
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is
as follows:
OUT
– LSB)/LSB
OUT
is the measured voltage difference between
calculated
REF (Pin 4): Reference Voltage Input. 0V ≤ V
V
, V
OUT A
The output range is
0
≤≤
VV V
VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND (Pin 7): System Ground.
INL = [V
Where V
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
(Pins 8,5): DAC Analog Voltage Outputs.
OUT B
1023
,
OUTA OUTB REF
– VOS – (VFS – VOS)(code/1023)]/LSB
OUT
is the output voltage of the DAC measured at
OUT
/1024
REF
1024
REF
≤ VCC.
6
Page 7
OPERATIO
LTC1661
U
Transfer Function
The transfer function for the LTC1661 is:
V
OUT IDEAL REF()
where k is the decimal equivalent of the binary DAC input
code D9-D0 and V
Power-On Reset
The LTC1661 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) must not ever exceed the voltage
at VCC (Pin 6) by more than 0.3V. Particular care should be
taken in the power supply turn-on and turn-off sequences
to assure that this limit is observed. See Absolute Maximum Ratings.
=
k
V
1024
is the voltage at REF (Pin 6).
REF
By selecting the appropriate 4-bit Control code (see Table 2)
it is possible to perform single operations, such as loading
one DAC or changing Power-Down status (Sleep/Wake).
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the DIN input
is shifted into the 16-bit Shift Register on the positive edge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
is pulled high, causing the system to respond according to
Table 2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Table 1. LTC1661 Input Word
Input Word
A3 A2 A1
Control Code
After the Input word is loaded into the register (see Figure 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
The first of these, the Input Register, is used for loading new
input codes. The second buffer, the DAC Register, is used
for updating the DAC outputs. Each DAC has its own 10-bit
Input Register and 10-bit DAC Register.
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 X1 X0D0
Input Code
Don’t
Care
DAC control code 1110b is reserved for the special Sleep
instruction (see Table 2). In this mode, the digital parts of
the circuit stay active while the analog sections are disabled; static power consumption is greatly reduced. The
reference input and analog outputs are set in a high
impedance state and all DAC settings are retained in
memory so that when Sleep mode is exited, the outputs of
DACs not updated by the Wake command are restored to
their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared with
new input codes during Sleep (control codes 0001b and
0010b); then, a single command (1000b) can be used both
to wake the part and to update the output values.
7
Page 8
LTC1661
U
OPERATIO
Table 2. DAC Control Functions
CONTROL
A3 A2 A1 A0 STATUS STATUS (SLEEP/WAKE) COMMENTS
0000 No Change No Update No Change No Operation. Power-Down Status Unchanged
0001 Load DAC A No Update No Change Load Input Register A with Data. DAC Outputs
0010 Load DAC B No Update No Change Load Input Register B with Data. DAC Outputs
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 No Change Update Outputs Wake Load Both DAC Regs with Existing Contents of Input
1001 Load DAC A Update Outputs Wake Load Input Reg A. Load DAC Regs with New Contents
1010 Load DAC B Update Outputs Wake Load Input Reg B. Load DAC Regs with Existing Contents
1011 Reserved
1100 Reserved
1101 No Change No Update Wake Part Wakes Up. Input and DAC Regs Unchanged. DAC
1110 No Change No Update Sleep Part Goes to Sleep. Input and DAC Regs Unchanged. DAC
1111 Load DACs A, B Update Outputs Wake Load Both Input Regs. Load Both DAC Regs with New
INPUT REGISTER DAC REGISTER POWER-DOWN STATUS
(Part Stays In Wake or Sleep Mode)
Unchanged. Power-Down Status Unchanged
Unchanged. Power-Down Status Unchanged
Regs. Outputs Update. Part Wakes Up
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
of Input Reg A and New Contents of Reg B. Outputs
Update. Part Wakes Up
Outputs Reflect Existing Contents of DAC Regs
Outputs Set to High Impedance State
with Same Contents of Input Regs. Outputs Update. Part Wakes Up
10-Bit Code
CS/LD
8
SCK
D
16151413121110987654321
IN
A3 A2
CONTROL CODE
(SCK ENABLED)
A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
INPUT CODE DON’T CARE
INPUT WORD W
0
X1 X0
(LTC1661
RESPONDS)
1661 F01
Figure 1. Register Loading Sequence
Page 9
OPERATIO
LTC1661
U
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in the
LTC1661 can typically source or sink up to 5mA
(VCC= 5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 85Ω (typical) when driving a load to
the rails. The output amplifiers are stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1µF
load can be successfully driven by inserting a 20Ω resistor
in series with the V
pin. A 2.2µF load needs only a 10Ω
OUT
resistor, and a 10µF electrolytic capacitor can be used
without any resistor (the equivalent series resistance of
the capacitor itself provides the required small resistance). In any of these cases, larger values of resistance,
capacitance or both may be substituted for the values
given.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If V
= VCC and the DAC full-scale error
REF
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 2c. No full-scale limiting can occur
if V
is less than VCC – FSE.
REF
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
V
= V
REF
CC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
= V
REF
CC
OUTPUT
VOLTAGE
5120 1023
INPUT CODE
(a)
OUTPUT
VOLTAGE
OFFSET
0V
INPUT CODE
(b)
REF
1661 F02
= V
CC
NEGATIVE
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
9
Page 10
LTC1661
TYPICAL APPLICATIO S
0.1µF
5V
4 6
DAC A
CS/LD
D
SCK
IN
1
3
2
1
3
2
LTC1661
U1
DAC B
5V
4 6
DAC B
LTC1661
U2
DAC A
7
0.1µF
U
V
(FROM MAIN
INPUT DAC)
R2
50k
8
= 2.5V
V
A1
R3
50k
5
V
B1
R5
50k
5
V
B2
R7
50k
8
VA2 = 2.5V
V
(FROM MAIN
INPUT DAC)
= 7.5V
H
= –2.5V
L
FOR EACH U1 AND U2
CODE A CODE B ∆V
R1
5k
10V
0.1µF
8
3
+
U3A
LT1368
2
–
6
–
5
+
4
–5V
U3B
LT1368
0.1µF
R4
5k
R6
5k
1
7
′ = VH + ∆V
V
H
VL′ = VL + ∆V
0.1µF
0.1µF
512 1023 –250mV
512 512 0
512 0 250mV
H
V
H
PIN
V
L
DRIVER
(1 0F N)
L
LOGIC
DRIVE
–2.5V ±250mV
, ∆V
H
V
OUT
7.5V ±250mV
L
VA2 = 2.5VVA1 =
R1
+(VA1 – VB1)VH′ =
R8
5k
V
H
R2
R1
VL +(VA2 – VB2)VL′ =
R2
10
FOR VALUES SHOWN,
, ∆VL ADJUSTMENT RANGE = ±250mV
∆V
H
, ∆VL STEP SIZE = 500µV
∆V
H
Figure 3. Pin Driver VH and VL Adjustment in ATE Applications
≥ 4.3V
V
IN
0.1µF
2
LTC1258-4.1
4
1
4.096V
4
3
2
1
REF
D
IN
SCK
CS/LD
LTC1661
Figure 4. Using the LTC1258 and the LTC1661 In a Single Li-Ion Battery Application
6
V
GND
0.1µF
CC
8
V
OUTA
V
OUTB
7
0V TO 4.096V
(4mV/BIT)
T
5
0V TO 4.096V
(4mV/BIT)
1661 F04
1661 F03
Page 11
PACKAGE DESCRIPTION
0.007
(0.18)
0.021
± 0.006
(0.53 ± 0.015)
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
° – 6° TYP
0
U
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
SEATING
PLANE
0.040
± 0.006
(1.02 ± 0.15)
0.012
(0.30)
0.0256
REF
0.034 ± 0.004
(0.86 ± 0.102)
0.006 ± 0.004
(0.15 ± 0.102)
(0.65)
BSC
8
7
12
LTC1661
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
MSOP (MS8) 1098
4
3
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
876
0.255 ± 0.015*
(6.477 ± 0.381)
12
0.300 – 0.325
(7.620 – 8.255)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.100
(2.54)
BSC
0.400*
(10.160)
MAX
3
5
4
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.020
(0.508)
MIN
N8 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
Page 12
LTC1661
TYPICAL APPLICATIO
5V
4 6
DAC A
CS/LD
D
SCK
IN
1
3
2
1
3
2
LTC1661
U1
DAC B
5V
4 6
DAC B
LTC1661
U2
DAC A
7
0.1µF
0.1µF
U
(FROM MAIN
INPUT DAC)
R2
50k
8
= 2.5V
V
A1
R3
50k
5
V
B1
R5
50k
5
V
B2
R7
50k
8
VA2 = 2.5V
V
(FROM MAIN
INPUT DAC)
= 7.5V
V
H
= –2.5V
L
FOR EACH U1 AND U2
CODE A CODE B ∆V
R1
5k
10V
0.1µF
8
3
+
U3A
LT1368
2
–
4
–5V
R6
5k
6
–
U3B
LT1368
5
+
0.1µF
R4
5k
1
7
V
′ = VH + ∆V
H
VL′ = VL + ∆V
0.1µF
0.1µF
512 1023 –250mV
512 512 0
512 0 250mV
H
V
H
PIN
V
L
DRIVER
(1 0F N)
L
LOGIC
DRIVE
–2.5V ±250mV
, ∆V
H
V
OUT
7.5V ±250mV
L
VA2 = 2.5VVA1 =
R1
+(VA1 – VB1)VH′ =
R8
5k
V
H
R2
R1
VL +(VA2 – VB2)VL′ =
R2
FOR VALUES SHOWN,
, ∆VL ADJUSTMENT RANGE = ±250mV
∆V
H
, ∆VL STEP SIZE = 500µV
∆V
H
Pin Driver VH and VL Adjustment in ATE Applications
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1446/LTC1446L Dual 12-Bit V
LTC1448 Dual 12-Bit V
LTC1454/LTC1454L Dual 12-Bit V
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V
LTC1659 Single Rail-to-Rail 12-Bit V
: 2.7V to 5.5V GND to REF. REF Input Can Be Tied to V
V
CC
LTC1663 Single 10-Bit V
LTC1665/LTC1660 Octal 8/10-Bit V
Linear Technology Corporation
12
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, V
OUT
LTC1446L: V
DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to V
OUT
DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, V
OUT
LTC1454L: V
LTC1458L: V
DAC in 8-Lead MSOP Package Low Power Multiplying V
OUT
DAC in SOT-23 Package VCC = 2.7V to 5.5V, Internal Reference, 60µA
OUT
DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
●
www.linear-tech.com
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
OUT
1661f LT/TP 0100 4K • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 1999
DAC. Output Swings from
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
= 0V to 4.095V
OUT
= 0V to 2.5V
OUT
CC
1661 F03
CC
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