ANALOG DEVICES LT 3757 EMSE Datasheet

LT3757/LT3757A

Boost, Flyback, SEPIC and

Inverting Controller

FeaTures

n

Wide Input Voltage Range: 2.9V to 40V

n

Positive or Negative Output Voltage Programming

with a Single Feedback Pin

n

Current Mode Control Provides Excellent Transient

Response

n

Programmable Operating Frequency (100kHz to

1MHz) with One External Resistor

n

Synchronizable to an External Clock

n

Low Shutdown Current < 1µA

n

Internal 7.2V Low Dropout Voltage Regulator

n

Programmable Input Undervoltage Lockout with

Hysteresis

n

Programmable Soft-Start

n

Small 10-Lead DFN (3mm × 3mm) and Thermally

Enhanced 10-Pin MSOP Packages

applicaTions

n

Automotive and Industrial Boost, Flyback, SEPIC and

Inverting Converters

n

Telecom Power Supplies

n

Portable Electronic Equipment

DescripTion

The LT®3757/LT3757A are wide input range, current
mode, DC/DC controllers which are capable of generating
either positive or negative output voltages. They can be
configured as either a boost, flyback, SEPIC or inverting
converter. The LT3757/LT3757A drive a low side external
N-channel power MOSFET from an internal regulated 7.2V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.

The operating frequency of LT3757/LT3757A can be set
with an external resistor over a 100kHz to 1MHz range,
and can be synchronized to an external clock using the
SYNC pin. A low minimum operating supply voltage of

2.9V, and a low shutdown quiescent current of less than
1µA, make the LT3757/LT3757A ideally suited for battery­operated systems.

The LT3757/LT3757A feature soft-start and frequency
foldback functions to limit inductor current during start-up
and output short-circuit. The LT3757A has improved load
transient performance compared to the LT3757.

L, LT , LTC , LTM , Linear Technology, the Linear logo and Burst Mode are registered trademarks
and No R
trademarks are the property of their respective owners.

and ThinSOT are trademarks of Linear Technology Corporation. All other

SENSE

Typical applicaTion

High Efficiency Boost Converter

V

IN

8V TO 16V

300kHz

41.2k

10µF
25V
X5R

200k

43.2k

0.1µF

SHDN/UVLO

LT3757

SYNC

RT
SS

V

C

22k

6.8nF

V

IN

GND

GATE

SENSE

FBX

INTV

CC

4.7µF
10V
X5R

10µH

0.01Ω

226k

16.2k

Efficiency

100

90

0.001

VIN = 8V

VIN = 16V

0.01

0.1 1

OUTPUT CURRENT (A)

10

3757 TA01b

3757afd

V

OUT

24V
2A

+

47µF
35V
×2

10µF
25V
X5R

3757 TA01a

80

70

60

EFFICIENCY (%)

50

40

30

1

LT3757/LT3757A

TOP VIEW

absoluTe MaxiMuM raTings

(Note 1)

VIN, SHDN/UVLO (Note 6) .........................................40V

INTV

GATE ........................................................ INTV

....................................................VIN + 0.3V, 20V

CC

+ 0.3V

CC

SYNC ..........................................................................8V

, SS .........................................................................3V

V

C

RT ............................................................................ 1.5V

SENSE ....................................................................±0.3V

FBX ................................................................. –6V to 6V

pin conFiguraTion

10

V

1

C

FBX

2

11

3

SS

4

RT

5

SYNC

10-LEAD (3mm × 3mm) PLASTIC DFN

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

DD PACKAGE

= 125°C, θJA = 43°C/W

T

JMAX

V

IN

9

SHDN/UVLO
INTV

8
7

GATE

6

SENSE

CC

Operating Temperature Range (Notes 2, 8)

LT3757E/LT3757AE............................–40°C to 125°C

LT3757I/LT3757AI ............................. –40°C to 125°C

LT3757H/LT3757AH ........................... –40°C to 150°C

LT3757MP/LT3757AMP ..................... –55°C to 150°C

Storage Temperature Range

DFN .................................................... –65°C to 125°C

MSOP ................................................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MSOP ............................................................... 300°C

TOP VIEW

10

1

V

C

FBX

2
SS
RT

SYNC

10-LEAD PLASTIC MSOP

T

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

JMAX

11

3

4

5

MSE PACKAGE

= 150°C, θJA = 40°C/W

V
SHDN/UVLO

9

INTV

8

GATE

7

SENSE

6

IN

CC

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3757EDD#PBF LT3757EDD#TRPBF LDYW

LT3757IDD#PBF LT3757IDD#TRPBF LDYW

LT3757EMSE#PBF LT3757EMSE#TRPBF LTDYX

LT3757IMSE#PBF LT3757IMSE#TRPBF LTDYX

LT3757HMSE#PBF LT3757HMSE#TRPBF LTDYX

LT3757MPMSE#PBF LT3757MPMSE#TRPBF LTDYX

LT3757AEDD#PBF LT3757AEDD#TRPBF LGGR

LT3757AIDD#PBF LT3757AIDD#TRPBF LGGR

LT3757AEMSE#PBF LT3757AEMSE#TRPBF LTGGM

LT3757AIMSE#PBF LT3757AIMSE#TRPBF LTGGM

LT3757AHMSE#PBF LT3757AHMSE#TRPBF LTGGM

LT3757AMPMSE#PBF LT3757AMPMSE#TRPBF LTGGM

10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is

identified by

–40°C to 125°C

–40°C to 125°C

–40°C to 125°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

–40°C to 125°C

–40°C to 125°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

2

3757afd

LT3757/LT3757A

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating temp­erature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Operating Range 2.9 40 V

V

IN

Shutdown I

V

IN

Operating I

V

IN

Operating IQ with Internal LDO Disabled VC = 0.3V, RT = 41.2k, INTVCC = 7.5V 280 400 µA

V

IN

Q

Q

SENSE Current Limit Threshold

SENSE Input Bias Current Current Out of Pin –65 µA

Error Amplifier

FBX Regulation Voltage (V

) V

FBX(REG)

FBX Overvoltage Lockout V

FBX Pin Input Current V

Transconductance g

Output Impedance (Note 3) 5 MΩ

V

C

Line Regulation [∆V

V

FBX

Current Mode Gain (∆VVC/∆V

V

C

Source Current V

V

C

Sink Current V

V

C

(∆IVC/∆V

m

FBX

) (Note 3) 230 µS

FBX

/(∆VIN • V

FBX(REG)

) 5.5 V/V

SENSE

Oscillator

Switching Frequency R

RT Voltage V

Minimum Off-Time 220 ns

Minimum On-Time 220 ns

SYNC Input Low 0.4 V

SYNC Input High 1.5 V

SS Pull-Up Current SS = 0V, Current Out of Pin –10 µA

Low Dropout Regulator

Regulation Voltage

INTV

CC

Undervoltage Lockout Threshold Falling INTVCC

INTV

CC

Overvoltage Lockout Threshold 16 17.5 V

INTV

CC

Current Limit V

INTV

CC

Load Regulation (∆V

INTV

CC

Line Regulation ∆V

INTV

CC

Dropout Voltage (V

Current in Shutdown SHDN/UVLO = 0V, INTVCC = 8V 16 µA

INTV

CC

– V

IN

INTVCC

/ V

INTVCC

INTVCC

/(V

) 0 < I

INTVCC

• ∆VIN) 8V < VIN < 40V 0.008 0.03 %/V

INTVCC

) V

SHDN/UVLO = 0V

0.1 1

SHDN/UVLO = 1.15V

VC = 0.3V, RT = 41.2k 1.6 2.2 mA

)] V

l

> 0V (Note 3)

FBX

V

< 0V (Note 3)

FBX

> 0V (Note 4)

FBX

V

< 0V (Note 4)

FBX

= 1.6V (Note 3)

FBX

V

= –0.8V (Note 3)

FBX

> 0V, 2.9V < VIN < 40V (Notes 3, 7)

FBX

V

< 0V, 2.9V < VIN < 40V (Notes 3, 7)

FBX

= 0V, VC = 1.5V –15 µA

FBX

= 1.7V

FBX

V

= –0.85V

FBX

= 41.2k to GND, V

T

R

= 140k to GND, V

T

R

= 10.5k to GND, V

T

= 1.6V 1.2 V

FBX

FBX

FBX

FBX

= 1.6V

= 1.6V

= 1.6V

l
l

l

100 110 120 mV

1.569

–0.816

6
7

1.6

–0.80

8

11

70 100

–10

0.002

0.0025

12
11

270 300

100

1000

7 7.2 7.4 V

2.6 2.7

UVLO Hysteresis

= 40V

IN

V

= 15V

IN

< 20mA, V

INTVCC

= 6V, I

IN

INTVCC

30 40

= 8V –0.9 –0.5 %

IN

= 20mA 400 mV

0.1

95

6

1.631

–0.784

10
14

10

0.056

0.05

330 kHz

2.8 V

55 mA

µA
µA

V
V

%
%

nA
nA

%/V
%/V

µA
µA

kHz
kHz

V

mA

3757afd

3

LT3757/LT3757A

REGULATED FEEDBACK VOLTAGE (mV)

1605

REGULATED FEEDBACK VOLTAGE (mV)

–788

QUIESCENT CURRENT (mA)

1.8

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating temp­erature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Voltage to Bypass Internal LDO 7.5 V

INTV

CC

Logic Inputs

SHDN/UVLO Threshold Voltage Falling V
SHDN/UVLO Input Low Voltage I(V

= INTVCC = 8V

IN

) Drops Below 1µA 0.4 V

IN

SHDN/UVLO Pin Bias Current Low SHDN/UVLO = 1.15V 1.7 2 2.5 µA
SHDN/UVLO Pin Bias Current High SHDN/UVLO = 1.30V 10 100 nA

Gate Driver

Gate Driver Output Rise Time CL = 3300pF (Note 5), INTVCC = 7.5V 22 ns

t

r

Gate Driver Output Fall Time CL = 3300pF (Note 5), INTVCC = 7.5V 20 ns

t

f

Gate V

OL

Gate V

OH

l

1.17 1.22 1.27 V

0.05 V

INTVCC –0.05 V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LT3757E/LT3757AE are guaranteed to meet performance
specifications from the 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LT3757I/LT3757AI are guaranteed over the full –40°C to
125°C operating junction temperature range. The LT3757H/LT3757AH are
guaranteed over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes.
lifetime is

derated at junction temperatures greater than 125°C. The
LT3757MP/LT3757AMP are 100% tested and guaranteed over the full
–55°C to 150°C operating junction temperature range.

Typical perForMance characTerisTics

Positive Feedback Voltage
vs Temperature, V

1600

1595

1590

1585

1580

VIN = 8V

–75 –50

–25 25 100 150125

4

IN

VIN = 40V

VIN = 24V

VIN = INTVCC = 2.9V
SHDN/UVLO = 1.33V

0 50 75

TEMPERATURE (°C)

3757 G01

Note 3: The LT3757/LT3757A are tested in a feedback loop which servos
V

to the reference voltages (1.6V and –0.8V) with the VC pin forced

FBX

to 1.3V.
Note 4: FBX overvoltage lockout is measured at V

to regulated V

Note 5: Rise and fall times are measured at 10% and 90% levels.
Note 6: For V
Note 7: SHDN/UVLO = 1.33V when V
Note 8: The LT3757/LT3757A include overtemperature protection that

is intended to protect the device during momentary overload conditions.

Operating

Junction temperature will exceed the maximum operating junction
temperature when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.

Negative Feedback Voltage
vs Temperature, VIN

–790

–792

–794

–796

–798

–800

–802

–804

VIN = INTVCC = 2.9V
SHDN/UVLO = 1.33V

VIN = 8V

VIN = 24V

–75 –50 0 50 75–25 25 100 150125

TEMPERATURE (°C)

.

FBX(REG)

below 6V, the SHDN/UVLO pin must not exceed VIN.

IN

= 2.9V.

IN

FBX(OVERVOLTAGE)

TA = 25°C, unless otherwise noted.

Quiescent Current
vs Temperature, V

VIN = 40V

3757 G02

1.7

1.6

1.5

1.4
–75 –50 0 50 75–25 25 100 150125

VIN = 40V

VIN = INTVCC = 2.9V

TEMPERATURE (°C)

relative

IN

VIN = 24V

3757 G03

3757afd

Typical perForMance characTerisTics

SENSE THRESHOLD (mV)

120

I

(µA)

330

LT3757/LT3757A

= 25°C, unless otherwise noted.

T

A

Dynamic Quiescent Current
vs Switching Frequency R

35

CL = 3300pF

30

25

20

(mA)

Q

I

15

10

5

0

0

300

100 200

SWITCHING FREQUENCY (KHz)

400

500 600

700

900800

3757 G04

1000

Switching Frequency
vs Temperature

RT = 41.2K

320

310

vs Switching Frequency

T

1000

(kΩ)

100

T

R

10

0

100 200

SWITCHING FREQUENCY (KHz)

300

400

500 600

700

SENSE Current Limit Threshold
vs Temperature

115

900800

3757 G05

1000

Normalized Switching Frequency
vs FBX

120

100

80

60

40

NORMALIZED FREQUENCY (%)

20

0

–0.8

–0.4

0 0.4 0.8
FBX VOLTAGE (V)

SENSE Current Limit Threshold
vs Duty Cycle

115

110

1.2 1.6

3757 G06

300

290

SWITCHING FREQUENCY (kHz)

280

270

–75 –50 0 50 75–25 25 100 150125

1.28

1.26

1.24

1.22

SHDN/UVLO VOLTAGE (V)

1.20

1.18
–75 –50 0 50 75–25 25 100 150125

110

105

100

TEMPERATURE (°C)

3757 G07

–75 –50 0 50 75–25 25 100 150125

TEMPERATURE (°C)

SHDN/UVLO Threshold
vs Temperature SHDN/UVLO Current vs Voltage

40

30

SHDN/UVLO RISING

20

SHDN/UVLO FALLING

10

SHDN/UVLO CURRENT (µA)

0

TEMPERATURE (°C)

0

3757 G10

10 20 30
SHDN/UVLO VOLTAGE (V)

3757 G08

3757 G11

105

100

SENSE THRESHOLD (mV)

SHDN/ UVLO

40

95

0

20 40 8060

DUTY CYCLE (%)

SHDN/UVLO Hysteresis Current
vs Temperature

2.4

2.2

2.0

1.8

1.6
–75 –50 0 50 75–25 25 100 150125

TEMPERATURE (°C)

100

3757 G09

3757 G12

3757afd

5

LT3757/LT3757A

INTV

(V)

7.4

DROPOUT VOLTAGE (mV)

700

90

Typical perForMance characTerisTics

INTVCC Minimum Output Current

vs Temperature

INTV

CC

7.3

CC

7.2

7.1

7.0
–75 –50 0 50 75–25 25 100 150125

TEMPERATURE (°C)

3757 G13

vs V

IN

TJ = 150°C

80

70

60

50

40

CURRENT (mA)

CC

30

INTV

20

10

0

0

INTVCC = 6V

INTVCC = 4.5V

10 20 305 15 25 35

VIN (V)

= 25°C, unless otherwise noted.

T

A

INTVCC Load Regulation

7.3
VIN = 8V

7.2

7.1

VOLTAGE (V)

CC

7

INTV

6.9

40

3757 G14

6.8

0

20

10

INTVCC LOAD (mA)

40 50

30

60

70

3757 G15

INTVCC Line Regulation

7.30

7.25

7.20

VOLTAGE (V)

CC

INTV

7.15

7.10
5

0

10

Gate Drive Rise
and Fall Time vs INTV

30

CL = 3300pF

25

20

FALL TIME

15

TIME (ns)

10

5

0

3

6

15

VIN (V)

RISE TIME

INTVCC (V)

25 30 40

20

CC

9

35

3757 G16

12 15

3757 G19

I

L1A

INTVCC Dropout Voltage
vs Current, Temperature

VIN = 6V

600

500

400

300

200

100

0

0

5

INTVCC LOAD (mA)

Typical Start-Up Waveforms

V

= 12V

IN

V

OUT

5V/DIV

+ I

L1B

5A/DIV

2ms/DIV

PAGE 31 CIRCUIT

125°C

10

150°C

75°C

25°C

0°C

–55°C

15 20

3757 G17

3757 G20

10V/DIV

20V/DIV

I

L1A

Gate Drive Rise
and Fall Time vs C

90

INTVCC = 7.2V

80

70

60

50

40

TIME (ns)

30

20

10

0

0

5 1510 20 25 30

RISE TIME

L

CL (nF)

FBX Frequency Foldback
Waveforms During Overcurrent

V

OUT

V

SW

+ I

L1B

5A/DIV

50µs/DIV

PAGE 31 CIRCUIT

FALL TIME

3757 G18

V

= 12V

IN

3757 G21

3757afd

6

pin FuncTions

LT3757/LT3757A

VC (Pin 1): Error Amplifier Compensation Pin. Used to
stabilize the voltage loop with an external RC network.

FBX (Pin 2): Positive and Negative Feedback Pin. Receives
the feedback voltage from the external resistor divider
across the output. Also modulates the frequency during
start-up and fault conditions when FBX is close to GND.

SS (Pin 3): Soft-Start Pin. This pin modulates compensation
pin voltage (V

) clamp. The soft-start interval is set with

C

an external capacitor. The pin has a 10µA (typical) pull-up
current source to an internal 2.5V rail. The soft-start pin
is reset to GND by an undervoltage condition at SHDN/
UVLO, an INTV

undervoltage or overvoltage condition

CC

or an internal thermal lockout.

RT (Pin 4): Switching Frequency Adjustment Pin. Set the
frequency using a resistor to GND. Do not leave this pin
open.

SYNC (Pin 5): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an R

resistor should be chosen to

T

program a switching frequency 20% slower than the SYNC
pulse frequency. Tie the SYNC pin to GND if this feature
is not used. SYNC is ignored when FBX is close to GND

.

SENSE (Pin 6): The Current Sense Input for the Control
Loop. Kelvin connect this pin to the positive terminal of
the switch current sense resistor in the source of the
N-channel MOSFET. The negative terminal of the current
sense resistor should be connected to GND plane close
to the IC.

GATE (Pin 7): N-Channel MOSFET Gate Driver Output.
Switches between INTV
IC is shut down, during thermal lockout or when INTV

and GND. Driven to GND when

CC

CC

is above or below the OV or UV thresholds, respectively.

INTV

Gate Driver. Supplied from V
cal). INTV
capacitor placed close to pin. INTV
directly to V

(Pin 8): Regulated Supply for Internal Loads and

CC

and regulated to 7.2V (typi-

IN

must be bypassed with a minimum of 4.7µF

CC

can be connected

CC

, if VIN is less than 17.5V. INTVCC can also

IN

be connected to a power supply whose voltage is higher
than 7.5V, and lower than V

, provided that supply does

IN

not exceed 17.5V.
SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect

Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
is okay to enable switching. Rising hysteresis is generated
by the external resistor

divider and an accurate internal
2µA pull-down current. An undervoltage condition resets
sort-start. Tie to 0.4V, or less, to disable the device and
reduce V

(Pin 10): Input Supply Pin. Must be locally bypassed

V

IN

quiescent current below 1µA.

IN

with a 0.22µF, or larger, capacitor placed close to the pin.

Exposed Pad (Pin 11): Ground. This pin also serves as the
negative terminal of the current sense resistor. The Exposed
Pad must be soldered directly to the local ground plane.

3757afd

7

LT3757/LT3757A

block DiagraM

L1

G2

–
+

+
–

10

V

108mV

•

IN

INTV

GATE

SENSE

GND

CC

11

V

IN

I

2.5V

I

S3

V

C

1

C

R

C2

C

C

C1

1.72V

A11

–

2µA

2.5V

S1

INTERNAL

REGULATOR

I

S2

10µA

Q3

AND UVLO

UVLO

G4 G3

+

G6

FBX

A12

–

–0.88V

+

+

1.6V

FBX

2

–0.8V

A1

–

+

A2

–

1.25V

Q2

–

A3

+

VC

PWM
COMPARATOR

A10

TSD

165˚C

–

A7

+

G1

9

SHDN/UVLO

–

1.22V

+

A9

A8

G5

SLOPE

RAMP

GENERATOR

100kHz-1MHz

OSCILLATOR

R3R4

RAMP

17.5V

+
–

+

2.7V UP

–

2.6V DOWN

V

ISENSE

+

CURRENT

LIMIT

7.2V LDO

SR1

R O

C

IN

DRIVER

S

A6

A5

C

DC

D1

V

OUT

L2

•

FBX

C

VCC

8

7

6

M1

R

SENSE

C

OUT2

R2

+

C

OUT1

R1

8

R5
8k

FREQUENCY

FOLDBACK

D2

FREQ
FOLDBACK

D3

SS

3 5 4

C

SS

1.25V

SYNC

+
+

A4

–

FREQ
PROG

Q1

RT

R

T

Figure 1. LT3757 Block Diagram Working as a SEPIC Converter

3757 F01

3757afd

applicaTions inForMaTion

(R3 + R4)

LT3757/LT3757A

Main Control Loop

The LT3757 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation. Op­eration can be best understood by referring to the Block
Diagram in Figure 1.

The start of each oscillator cycle sets the SR latch (SR1) and
turns on the external power MOSFET switch M1 through
driver G2. The switch current flows through the external
current sensing resistor R

and generates a voltage

SENSE

proportional to the switch current. This current sense
voltage V

(amplified by A5) is added to a stabilizing

ISENSE

slope compensation ramp and the resulting sum (SLOPE)
is fed into the positive terminal of the PWM comparator A7.
When SLOPE exceeds the level at the negative input of A7

pin), SR1 is reset, turning off the power switch. The

(V

C

level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.

The LT3757 has a switch

current limit

function. The current
sense voltage is input to the current limit comparator A6.
If the SENSE pin voltage is higher than the sense current
limit threshold V

SENSE(MAX)

(110mV, typical), A6 will reset

SR1 and turn off M1 immediately.

The LT3757 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost, flyback or SEPIC converter to gen­erate positive output voltage, or as an inverting converter
to generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt­age divider (R1 and R2) connected from V

to GND.

OUT

Comparator A2 becomes inactive and comparator A1
performs the inverting amplification from FBX to V

. When

C

the LT3757 is in an inverting configuration, the FBX pin
is pulled down to –0.8V by a voltage divider connected
from V

to GND. Comparator A1 becomes inactive and

OUT

comparator A2 performs the noninverting amplification
from FBX to V

.

C

The LT3757 has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or

recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.

Programming Turn-On and Turn-Off Thresholds with
the SHDN/UVLO Pin

The SHDN/UVLO pin controls whether the LT3757 is
enabled or is in shutdown state. A micropower 1.22V
reference, a comparator A10 and a controllable current
source I

allow the user to accurately program the supply

S1

voltage at which the IC turns on and off. The falling value
can be accurately set by the resistor dividers R3 and R4.
When SHDN/UVLO is above 0.7V, and below the 1.22V
threshold, the small pull-down current source I

(typical

S1

2µA) is active.

The purpose of this current is to allow the user to program
the rising hysteresis.

The Block Diagram of the comparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:

V

V

VIN,FALLING

VIN,RISING

= 1.22 •

= 2µA • R3+ V

R4

IN,FALLING

For applications where the SHDN/UVLO pin is only used
as a logic input, the SHDN/UVLO pin can be connected
directly to the input voltage V

for always-on operation.

IN

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INTVCC Regulator Bypassing and Operation

An internal, low dropout (LDO) voltage regulator produces
the 7.2V INTV

supply which powers the gate driver,

CC

as shown in Figure 1. If a low input voltage operation is
expected (e.g., supplying power from a lithium-ion battery
or a 3.3V logic supply), low threshold MOSFETs should
be used. The LT3757 contains an undervoltage lockout
comparator A8 and an overvoltage lockout comparator
A9 for the INTV

supply. The INTVCC undervoltage (UV)

CC

threshold is 2.7V (typical), with 100mV hysteresis, to
ensure that the MOSFETs have sufficient gate drive voltage
before turning on. The logic circuitry within the LT3757 is
also powered from the internal INTV

The INTV

overvoltage (OV) threshold is set to be 17.5V

CC

supply.

CC

(typical) to protect the gate of the power MOSFET. When
INTV

is below the UV threshold, or above the OV thresh-

CC

old, the GATE pin will be forced to GND and the soft-start
operation will be triggered.

The INTV

regulator must be bypassed to ground imme-

CC

diately adjacent to the IC pins with a minimum of 4.7µF cera­mic capacitor. Good bypassing is necessary to supply the
high transient currents required

by the MOSFET gate driver.

In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
The on-chip power dissipation can be a significant concern
when a large power MOSFET is being driven at a high fre­quency and the V

voltage is high. It is important to limit

IN

the power dissipation through selection of MOSFET and/
or operating frequency so the LT3757 does not exceed its
maximum junction temperature rating. The junction tem­perature T

T

J

can be estimated using the following equations:

J

= TA + PIC • θ

JA

TA = ambient temperature

= junction-to-ambient thermal resistance

θ

JA

= IC power consumption

P

IC

= V

= VIN operation IQ = 1.6mA

I

Q

I

DRIVE

• (IQ + I

IN

= average gate drive current = f • Q

DRIVE

)

G

f = switching frequency

= power MOSFET total gate charge

Q

G

The LT3757 uses packages with an Exposed Pad for en­hanced thermal conduction. With proper soldering to the
Exposed Pad on the underside of the package and a full
copper plane underneath the device, thermal resistance

) will be about 43°C/W for the DD package and 40°C/W

(θ

JA

for the MSE package. For an ambient board temperature of

= 70°C and maximum junction temperature of 125°C,

T

A

the maximum I

DRIVE

(I

DRIVE(MAX)

) of the DD package can

be calculated as:

TA)

(T

I

DRIVE(MAX )

J

=

(θ

JA

− IQ=

• VIN)

The LT3757 has an internal INTVCC I

1.28W
V

IN

DRIVE

− 1.6mA

current limit
function to protect the IC from excessive on-chip power
dissipation. The I
increases (see the INTV

current limit decreases as the VIN

DRIVE

Minimum Output Current vs VIN

CC

graph in the Typical Performance Characteristics section).
If I

reaches the current limit, INTVCC voltage will fall

DRIVE

and may trigger the soft-start.

Based on the preceding equation and the INTV
Output Current vs V

graph, the user can calculate the

IN

Minimum

CC

maximum MOSFET gate charge the LT3757 can drive at
a given V

vs VIN at different frequencies to guarantee a minimum

Q

G

4.5V INTV

and switch frequency. A plot of the maximum

IN

is shown in Figure 2.

CC

As illustrated in Figure 2, a trade-off between the operating
frequency and the size of the power MOSFET may be needed
in order to maintain a reliable IC junction temperature.

300

250

300kHz

200

150

(nC)

G

Q

100

50

0

5

0

Figure 2. Recommended Maximum QG vs VIN at Different
Frequencies to Ensure INTVCC Higher Than 4.5V

1MHz

10 20

15 30 4025 35

VIN (V)

3757 F02

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LT3757/LT3757A

Prior to lowering the operating frequency, however, be
sure to check with power MOSFET manufacturers for their
most recent low QG, low R

devices. Power MOSFET

DS(ON)

manufacturing technologies are continually improving, with
newer and better performance devices being introduced
almost yearly.

An effective approach to reduce the power consumption
of the internal LDO for gate drive is to tie the INTVCC pin
to an external voltage source high enough to turn off the
internal LDO regulator.

If the input voltage VIN does not exceed the absolute
maximum rating of both the power MOSFET gate-source
voltage (VGS) and the INTVCC overvoltage lockout threshold
voltage (17.5V), the INTVCC pin can be shorted directly
to the VIN pin. In this condition, the internal LDO will be
turned off and the gate driver will be powered directly
from the input voltage, VIN. With the INTVCC pin shorted to
VIN, however, a small current (around 16µA) will load the
INTVCC in shutdown mode. For applications that require
the lowest shutdown mode input supply current, do not
connect the INTVCC pin to VIN.

In SEPIC or flyback applications, the INTVCC pin can be
connected to the output voltage V
diode, as shown in Figure 3, if V

through a blocking

OUT

meets the following

OUT

conditions:

1. V

2. V

3. V

A resistor R
limit the inrush current from V

< VIN (pin voltage)

OUT

< 17.5V

OUT

< maximum VGS rating of power MOSFET

OUT

can be connected, as shown in Figure 3, to

VCC

. Regardless of whether

OUT

or not the INTVCC pin is connected to an external voltage
source, it is always necessary to have the driver circuitry
bypassed with a 4.7µF low ESR ceramic capacitor to
ground immediately adjacent to the INTVCC and GND pins.

LT3757

INTV

CC

GND

C

4.7µF

3757 F03

D

VCC

VCC

R

VCC

V

OUT

Operating Frequency and Synchronization

The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
operation improves efficiency by reducing gate drive cur­rent and MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications for
loop compensation. The LT3757 uses a constant-frequency
architecture that can be programmed over a 100kHz to
1000kHz range with a single external resistor from the
RT pin to ground, as shown in Figure 1. The RT pin must
have an external resistor to GND for proper operation of
the LT3757. A table for selecting the value of R

for a given

T

operating frequency is shown in Table 1.

Table 1. Timing Resistor (RT) Value

OSCILLATOR FREQUENCY (kHz) RT (kΩ)

100 140

200 63.4

300 41.2

400 30.9

500 24.3

600 19.6

700 16.5

800 14

900 12.1

1000 10.5

The operating frequency of the LT3757 can be synchronized
to an external clock source. By providing a digital clock
signal into the SYNC pin, the LT3757 will operate at the
SYNC clock frequency. If this feature is used, an R

resistor

T

should be chosen to program a switching frequency 20%
slower than SYNC pulse frequency. The SYNC pulse should
have a minimum pulse width of 200ns. Tie the SYNC pin
to GND if this feature is not used.

Figure 3. Connecting INTVCC to V

OUT

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Duty Cycle Consideration

Switching duty cycle is a key variable defining converter
operation. As such, its limits must be considered. Minimum
on-time is the smallest time duration that the LT3757 is
capable of turning on the power MOSFET. This time is
generally about 220ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3757 keeps the power switch off for at least
220ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).

The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:

Minimum duty cycle = minimum on-time • frequency

Maximum duty cycle = 1 – (minimum off-time • frequency)

Programming the Output Voltage

The output voltage (V
shown in Figure 1. The positive and negative V

) is set by a resistor divider, as

OUT

OUT

are set

by the following equations:

V

OUT, POSITIVE

V

OUT, NEGATIVE

= 1.6V • 1+






= –0.8V • 1+






R1

R2






R1






R2

The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).

In the applications where V

is pulled up by an external

OUT

positive power supply, the FBX pin is also pulled up through
the R2 and R1 network. Make sure the FBX does not exceed
its absolute maximum rating (6V). The R5, D2, and D3 in
Figure 1 provide a resistive clamp in the positive direction.
To ensure FBX is lower than 6V, choose sufficiently large
R1 and R2 to meet the following condition:

Soft-Start

The LT3757 contains several features to limit peak switch
currents and output voltage (V

) overshoot during

OUT

start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.

High peak switch currents during start-up may occur in
switching regulators. Since V

is far from its final value,

OUT

the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.

The LT3757 addresses this mechanism with the SS pin. As
shown in Figure 1, the SS pin reduces the power MOSFET
current by pulling down the V

pin through Q2. In this

C

way the SS allows the output capacitor to charge gradu­ally toward its final value while limiting the start-up peak
currents. The typical start-up waveforms are shown in the
Typical Performance Characteristics section. The inductor
current I

slewing rate is limited by the soft-start function.

L

Besides start-up, soft-start can also be triggered by the
following faults:

1. INTV

2. INTV

> 17.5V

CC

< 2.6V

CC

3. Thermal lockout

Any of these three faults will cause the LT3757 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10µA current source I

starts

S2

charging the SS pin, initiating a soft-start operation.

The soft-start interval is set by the soft-start capacitor
selection according to the equation:

TSS= CSS•

1.25V
10µA

6V • 1+

where V

R2






R1

OUT(MAX)



+ 3.5V •





is the maximum V

R2

8kΩ

> V

OUT(MAX)

that is pulled up

OUT

by an external power supply.

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FBX Frequency Foldback

When V

is very low during start-up or a short-circuit

OUT

fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor current
decay rate is very low during switch off time. The minimum
on-time limitation may prevent the switcher from attaining
a sufficiently low duty cycle at the programmed switching
frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3757 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normal­ized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).

The typical frequency foldback waveforms are shown
in the Typical Performance Characteristics section. The
frequency foldback function prevents I

from exceeding

L

the programmed limits because of the minimum on-time.

The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3757/LT3757A, a series resistor­capacitor network is usually connected from the V
GND. Figure 1 shows the typical V

compensation network.

C

pin to

C

For most applications, the capacitor should be in the range
of 470pF to 22nF, and the resistor should be in the range
of 5k to 50k. A small capacitor is often connected in par­allel with the RC compensation network to attenuate the

voltage ripple induced from the output voltage ripple

V

C

through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.

SENSE Pin Programming

During frequency foldback, external clock synchroniza­tion is disabled to prevent interference with frequency
reducing operation.

Thermal Lockout

If LT3757 die temperature reaches 165°C (typical), the
part will go into thermal lockout. The power

turned off. A soft-start operation will be triggered. The

be

switch will

part will be enabled again when the die temperature has
dropped by 5°C (nominal).

Loop Compensation

Loop compensation determines the stability and transient
performance. The LT3757/LT3757A use current mode
control to regulate the output which simplifies loop com­pensation. The LT3757A improves the no-load to heavy
load transient response, when compared to the LT3757.
New internal circuits ensure that the transient from not
switching to switching at high current can be made in a
few cycles.

For control and protection, the LT3757 measures the
power MOSFET current by using a sense resistor (R

SENSE

)
between GND and the MOSFET source. Figure 4 shows a
typical waveform of the sense voltage (V

SENSE

) across the
sense resistor. It is important to use Kelvin traces between
the SENSE pin and R
close as possible to the GND terminal of the R

, and to place the IC GND as

SENSE

SENSE

for

proper operation.

V

SENSE

V

SENSE(MAX)

DT

S

Figure 4. The Sense Voltage During a Switching Cycle

∆V

SENSE = χ • VSENSE(MAX)

V

SENSE(PEAK)

T

S

t

3757 F04

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Due to the current limit function of the SENSE pin, R

SENSE

should be selected to guarantee that the peak current sense
voltage V

SENSE(PEAK)

during steady state normal operation
is lower than the SENSE current limit threshold (see the
Electrical Characteristics table). Given a 20% margin,
V

SENSE(PEAK)

is set to be 80mV. Then, the maximum
switch ripple current percentage can be calculated using
the following equation:

∆V

c =

c

80mV − 0.5 • ∆V

is used in subsequent design examples to calculate in-

ductor value. ∆V

SENSE

SENSE

is the ripple voltage across R

SENSE

SENSE

The LT3757 switching controller incorporates 100ns timing
interval to blank the ringing on the current sense signal
immediately after M1 is turned on. This ringing is caused
by the parasitic inductance and capacitance of the PCB
trace, the sense resistor, the diode, and the MOSFET. The
100ns timing interval is adequate for most of the LT3757
applications. In the applications that have very large and
long ringing on the current sense signal, a small RC filter
can be added to filter out the excess ringing. Figure 5
shows the RC filter on SENSE pin. It is usually sufficient
to choose 22Ω for R
Keep R

’s resistance low. Remember that there is 65µA

F LT

(typical) flowing out of the SENSE pin. Adding R

and 2.2nF to 10nF for C

F LT

F LT

FLT

will

affect the SENSE current limit threshold:

V

SENSE_ILIM

= 108mV – 65µA • R

F LT

APPLICATION CIRCUITS

The LT3757 can be configured as different topologies. The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.

Boost Converter: Switch Duty Cycle and Frequency

The LT3757 can be configured as a boost converter for
the

applications where the converter output voltage is
higher than the input voltage. Remember that boost con­verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a

.

step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.

The conversion ratio as a function of duty cycle is

V

OUT

V

IN

=

1

1− D

in continuous conduction mode (CCM).

For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output

.

voltage (V
duty cycle (D

) and the input voltage (VIN). The maximum

OUT

) occurs when the converter has the

MAX

minimum input voltage:

V

− V

D

MAX

OUT

=

V

IN(MIN)

OUT

Discontinuous conduction mode (DCM) provides higher

FLT

FLT

M1

R

conversion ratios at a given frequency at the cost of reduced
efficiencies and higher switching currents.

SENSE

3757 F05

3757afd

GATE

LT3757

SENSE

GND

Figure 5. The RC Filter on SENSE Pin

R

C

14

applicaTions inForMaTion

LT3757/LT3757A

Boost Converter: Inductor and Sense Resistor Selection

For the boost topology, the maximum average inductor
current is:

•

1− D

1

MAX

I

L(MAX )

= I

O(MAX)

Then, the ripple current can be calculated by:

∆IL= c • I

L(MAX )

= c • I

O(MAX)

•

1− D

1

MAX

The constant c in the preceding equation represents the
percentage peak-to-peak ripple current in the inductor,
relative to I

L(MAX)

.

The inductor ripple current has a direct effect on the choice
of the inductor value. Choosing smaller values of ∆I

L

requires large inductances and reduces the current loop
gain (the converter will approach voltage mode). Accepting
larger values of ∆I

provides fast transient response and

L

allows the use of low inductances, but results in higher input
current ripple and greater core losses. It is recommended
that c fall within the range of 0.2 to 0.6.

Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value of the boost converter can be determined
using the following equation:

V

IN(MIN)

L =

∆IL• f

• D

MAX

The peak and RMS inductor current are:

c













2

2

c

12

I

L(PEAK)

I

L(RMS)

= I

= I

L(MAX )

L(MAX )

• 1+

• 1+

Based on these equations, the user should choose the
inductors having sufficient saturation and RMS current
ratings.

Set the sense voltage at I

L(PEAK)

to be the minimum of the
SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:

80mV

R

SENSE

=

I

L(PEAK)

Boost Converter: Power MOSFET Selection

Important parameters for the power MOSFET include the
drain-source voltage rating (V
(V

), the on-resistance (R

GS(TH)

and gate to drain charges (Q
drain current (I
resistances (R

θJC

) and the MOSFET’s thermal

D(MAX)

and R

θJA

), the threshold voltage

DS

), the gate to source

DS(ON)

and QGD), the maximum

GS

).

The power MOSFET will see full output voltage, plus a
diode forward voltage, and any additional ringing across
its drain-to-source during its off-time. It is recommended
to choose a MOSFET whose B

is higher than V

VDSS

OUT

by

a safety margin (a 10V safety margin is usually sufficient).

The power dissipated by the MOSFET in a boost conver­ter is:

P

• C

FET

= I

RSS

2

L(MAX)

• f /1A

• R

DS(ON)

• D

MAX

+ 2 • V

2

OUT

• I

L(MAX)

The first term in the preceding equation represents the
conduction losses in the device, and the second term, the
switching loss. C

is the reverse transfer capacitance,

RSS

which is usually specified in the MOSFET characteristics.

For maximum efficiency, R

DS(ON)

and C

should be

RSS

minimized. From a known power dissipated in the power
MOSFET,

its junction temperature can be obtained using

the following equation:

= TA + P

T

J

must not exceed the MOSFET maximum junction

T

J

• θJA = TA + P

FET

• (θJC + θCA)

FET

temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.

3757afd

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Boost Converter: Output Diode Selection

To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to:

c









• I



L(MAX )



2

I

D(PEAK )

= I

L(PEAK)

= 1+

It is recommended that the peak repetitive reverse voltage
rating V

is higher than V

RRM

by a safety margin (a 10V

OUT

safety margin is usually sufficient).

The power dissipated by the diode is:

P

D

= I

O(MAX)

• V

D

and the diode junction temperature is:

= TA + PD • R

T

J

The R
R

θJC

to be used in this equation normally includes the

θJA

for the device plus the thermal resistance from the

board to the ambient temperature in the enclosure. T

θJA

must

J

not exceed the diode maximum junction temperature rating.

these three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform for a typical boost converter is
illustrated in Figure 6.

t

t

ON

OFF

∆V

COUT

V

OUT

(AC)

∆V

ESR

Figure 6. The Output Ripple Waveform of a Boost Converter

RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)

3757 F05

The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ∆V
ing ∆V

. For the purpose of simplicity, we will choose

COUT

and the charging/discharg-

ESR

2% for the maximum output ripple, to be divided equally
between ∆V

ESR

and ∆V

. This percentage ripple will

COUT

change, depending on the requirements of the application,
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:

Boost Converter: Output Capacitor Selection

Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of

ESR

COUT

≤

0.01• V
I

D(PEAK )

OUT

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For the bulk C component, which also contributes 1% to
the total ripple:

I

≥

0.01• V

O(MAX)

OUT

• f

C

OUT

The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 6. The RMS ripple
current rating of the output capacitor can be determined
using the following equation:

D

I

RMS(COUT)

≥ I

O(MAX)

MAX

•

1− D

MAX

Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
the required RMS current rating. Additional ceramic capaci­tors in parallel are commonly used to reduce the effect of
parasitic inductance in the output capacitor, which reduces
high frequency switching noise on the converter output.

Boost Converter: Input Capacitor Selection

The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave­form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi­cally in the range of 10µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.

The RMS input capacitor ripple current for a boost con­verter is:

I

RMS(CIN)

= 0.3 • ∆I

L

FLYBACK CONVERTER APPLICATIONS

The LT3757 can be configured as a flyback converter
for the applications where the converters have multiple
outputs, high output voltages or isolated outputs. Figure
7 shows a simplified flyback converter.

The flyback converter has a very low parts count for mul-

outputs, and with prudent selection of turns ratio, can

tiple
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
the high peak currents, high peak voltages and consequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.

The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con­tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen­sation, and the disadvantage of higher peak-to-average
current and lower efficiency. In the high output voltage
applications, the flyback converters can be designed
to operate in discontinuous mode to avoid using large
transformers.

SUGGESTED

IN

RCD SNUBBER

–

V

SN

+

C

SN

3757 F06

R

LT3757

GATE

SENSE

SN

D

SN

GND

V

IN

C

NP:N

L

P

M

R

S

L

I

SW

+

V

DS

–

SENSE

D

I

D

S

+

C

OUT

–

Figure 7. A Simplified Flyback Converter

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Flyback Converter: Switch Duty Cycle and Turns Ratio

The flyback converter conversion ratio in the continuous
mode operation is:

V

OUT

V

N

D

S

=

•

N

IN

1− D

P

where NS/NP is the second to primary turns ratio.

Figure 8 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
period T
During DT
D2T

currents are zero during D3TS.

L

S

, three subintervals occur: DTS, D2TS, D3TS.

S

, M is on, and D is reverse-biased. During

S

, M is off, and LS is conducting current. Both LP and

S

The flyback converter conversion ratio in the discontinu­ous mode operation is:

V

OUT

V

N

D

S

=

•

N

IN

D2

P

According to the preceding equations, the user has relative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select­ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:

• Lower MOSFET RMS current I

SW(RMS)

, but higher

MOSFET VDS peak voltage

• Lower diode peak reverse voltage, but higher diode
RMS current I

• Higher transformer turns ratio (N

D(RMS)

)

P/NS

The choice,

1

=

3

D

D+ D2

V

DS

I

SW

I

SW(MAX)

I

D

I

D(MAX)

DT

S

Figure 8. Waveforms of the Flyback Converter
in Discontinuous Mode Operation

D2T

S

T

S

D3T

S

3757 F07

(for discontinuous mode operation with a given D3) gives
the power MOSFET the lowest power stress (the product
of RMS current and peak voltage). However, in the high
output voltage applications, a higher duty cycle may be
adopted to limit the large peak reverse voltage of the
diode. The choice,

2

=

3

D

D+ D2

(for discontinuous mode operation with a given D3) gives
the diode the lowest power stress (the product of RMS
current and peak voltage). An extreme high or low duty
cycle results in high power stress on the MOSFET or diode,

t

and reduces efficiency. It is recommended to choose a
duty cycle, D, between 20% and 80%.

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D2

LT3757/LT3757A

Flyback Converter: Transformer Design for
Discontinuous Mode Operation

The transformer design for discontinuous mode of opera­tion is chosen as presented here. According to Figure 8,
the minimum D3 (D3
has the minimum V
(P

). Choose D3

OUT

MIN

) occurs when the converter

MIN

and the maximum output power

IN

to be equal to or higher than 10%
to guarantee the converter is always in discontinuous
mode operation (choosing higher D3 allows the use of low
inductances, but results in a higher switch peak current).

The user can choose a D

as the start point. Then, the

MAX

maximum average primary currents can be calculated by
the following equation:

P

I

LP(MAX)

= I

SW(MAX)

=

D

MAX

OUT(MAX)

• V

IN(MIN)

• h

where h is the converter efficiency.

If the flyback converter has multiple outputs, P

OUT(MAX)

is the sum of all the output power.

The maximum average secondary current is:

I

I

LS(MAX )

= I

D(MAX)

OUT(MAX)

=

where:

D2 = 1 – D

MAX

– D3

the primary and secondary RMS currents are:

D

MAX

•

3

D2

•

3

I

LP(RMS)

I

LS(RMS)

= 2 • I

= 2 • I

LP(MAX)

LS(MAX )

According to Figure 8, the primary and secondary peak
currents are:

I

I

LP(PEAK)

LS(PEAK)

= I

SW(PEAK)

= I

D(PEAK)

= 2 • I

= 2 • I

LP(MAX)

LS(MAX)

The primary and second inductor values of the flyback
converter transformer can be determined using the fol­lowing equations:

2

D

D2

MAX

2 • P

2

2 •I

LP=

LS=

2

• V

IN(MIN)

OUT(MAX)

• (V

OUT

OUT(MAX)

• h

• f

+ VD)

• f

The primary to second turns ratio is:

N
N

L

P

S

P

=

L

S

Flyback Converter: Snubber Design

Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOS­FET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
In some cases a snubber circuit will be required to avoid
overvoltage breakdown at the MOSFET’s drain node. There
are different snubber circuits, and Application Note 19 is
a good reference on snubber design. An RCD snubber is
shown in Figure 7.

The snubber resistor value (R

) can be calculated by the

SN

following equation:

•

OUT

• LLK• f

N

P

N

S

RSN= 2 •

2

V

SN

I

− VSN• V

2

SW(PEAK)

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where VSN is the snubber capacitor voltage. A smaller

results in a larger snubber loss. A reasonable VSN is

V

SN

2 to 2.5 times of:

V

• N

OUT

P

N

S

LLK is the leakage inductance of the primary winding, which
is usually specified in the transformer characteristics. L

LK

can be obtained by measuring the primary inductance with
the secondary windings shorted. The snubber capacitor
value (C

) can be determined using the following equation:

CN

V

CCN=

SN

∆VSN• RCN• f

where ∆VSN is the voltage ripple across CCN. A reasonable

is 5% to 10% of VSN. The reverse voltage rating of

∆V

SN

should be higher than the sum of VSN and V

D

SN

IN(MAX)

.

Flyback Converter: Sense Resistor Selection

In a flyback converter, when the power switch is turned
on, the current flowing through the sense resistor

SENSE

SENSE

) is:

= I

LP

LP(PEAK)

to be the minimum of

(I

I

Set the sense voltage at I
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:

80mV

R

SENSE

=

I

LP(PEAK)

Flyback Converter: Power MOSFET Selection

For the flyback configuration, the MOSFET is selected with

rating high enough to handle the maximum VIN, the

a V

DC

reflected secondary voltage and the voltage spike due to
the leakage inductance. Approximate the required MOSFET

rating using:

V

DC

DSS

> V

DS(PEAK)

BV

where:

V

DS(PEAK )

V

IN(MAX)

V

SN

The power dissipated by the MOSFET in a flyback con­verter is:

P
C

RSS

= I

FET

• f /1A

2

M(RMS)

• R

DS(ON)

+ 2 • V

2

DS(PEAK)

• I

L(MAX)

The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. C

is the reverse transfer capacitance, which is

RSS

usually specified in the MOSFET characteristics.

From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
equation:

= TA + P

T

J

must not exceed the MOSFET maximum junction

T

J

• θJA = TA + P

FET

• (θJC + θCA)

FET

temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.

•

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Flyback Converter: Output Diode Selection

The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.

Approximate the required peak repetitive reverse voltage
rating V

V

RRM

RRM

>

using:

N

S

• V

N

P

IN(MAX)

+ V

OUT

The power dissipated by the diode is:

P

D

= I

O(MAX)

• V

D

and the diode junction temperature is:

= TA + PD • R

T

J

The R
R

θJC

to be used in this equation normally includes the

θJA

for the device, plus the thermal resistance from the

board to the ambient temperature in the enclosure. T

θJA

must

J

not exceed the diode maximum junction temperature rating.

Flyback Converter: Input Capacitor Selection

The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
discontinuous operation can be determined using the
following equation:

I

RMS(CIN),DISCONTINUOUS

≥

P

OUT(MAX)

V

IN(MIN)

• h

•

4 − (3 • D

3 • D

MAX

MAX

)

SEPIC CONVERTER APPLICATIONS

The LT3757 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:

V

+ V

OUT

V

IN

D

D

=

1− D

Flyback Converter: Output Capacitor Selection

The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer
to the Boost Converter: Output Capacitor Selection section
for the calculation of C

and ESR

OUT

COUT

.

The RMS ripple current rating of the output capacitors
in discontinuous operation can be determined using the
following equation:

I

RMS(COUT),DISCONTINUOUS

≥ I

O(MAX)

4 − (3 • D2)

•

3 • D2

in continuous conduction mode (CCM).

In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.

Compared to the flyback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
output diode voltages are clamped by the capacitors (C
C

DC

and C

), therefore, there is less voltage ringing

OUT

IN

,

across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the inductor L1 is in series
with the input, and the ripple current flowing through the
input capacitor is continuous.

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SEPIC Converter: Switch Duty Cycle and Frequency

For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (V
forward voltage (V

The maximum duty cycle (D

), the input voltage (VIN) and the diode

OUT

).

D

) occurs when the converter

MAX

has the minimum input voltage:

+ V

V

D

=

MAX

V

IN(MIN)

OUT

+ V

OUT

D

+ V

D

SEPIC Converter: Inductor and Sense Resistor Selection

As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but can
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.

For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:

D

•

1− D

MAX

MAX

I

L1(MAX)

I

L2(MAX)

= I

IN(MAX)

= I

O(MAX)

= I

O(MAX)

In a SEPIC converter, the switch current is equal to IL1 +

when the power switch is on, therefore, the maximum

I

L2

average switch current is defined as:

I

SW(MAX)

= I

L1(MAX)

+ I

L2(MAX)

= I

O(MAX)

•

1− D

1

MAX

and the peak switch current is:

I

SW(PEAK)



= 1+





c



• I



O(MAX)



2

•

1− D

1

MAX

The constant c in the preceding equations represents the
percentage peak-to-peak ripple current in the switch, rela­tive to I

SW(MAX)

ripple current ∆I

SW

= c • I

∆I

, as shown in Figure 9. Then, the switch

can be calculated by:

SW

SW(MAX)

The inductor ripple currents ∆IL1 and ∆IL2 are identical:

∆I

= ∆IL2 = 0.5 • ∆I

L1

SW

The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of

requires large inductances and reduces the current

∆I

L

loop gain (the converter will approach voltage mode).
Accepting larger values of ∆I

allows the use of low in-

L

ductances, but results in higher input current ripple and
greater core losses. It is recommended that c falls in the
range of 0.2 to 0.4.

I

SW

I

SW(MAX)

DT

S

Figure 9. The Switch Current Waveform of the SEPIC Converter

∆I

SW = χ • ISW(MAX)

T

S

t

3757 F08

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Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value (L1 and L2 are independent) of the SEPIC
converter can be determined using the following equation:

V

L1= L2 =

IN(MIN)

0.5 • ∆ISW• f

• D

MAX

For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.

By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:

V

IN(MIN)

L =

∆ISW• f

• D

MAX

This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:

I

I

L1(PEAK)

L2(PEAK)

= I

= I

L1(MAX)

L2(MAX)

+ 0.5 • ∆I

+ 0.5 • ∆I

L1

L2

The RMS inductor currents are:

Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS cur­rent ratings.

In a SEPIC converter, when the power switch is turned on,
the current flowing through the sense resistor (I

SENSE

) is

the switch current.

Set the sense voltage at I

SENSE(PEAK)

to be the minimum
of the SENSE current limit threshold with a 20% margin.
The sense resistor value can then be calculated to be:

80 mV

R

SENSE

=

I

SW(PEAK)

SEPIC Converter: Power MOSFET Selection

For the SEPIC configuration, choose a MOSFET with a

rating higher than the sum of the output voltage and

V

DC

input voltage by a safety margin (a 10V safety margin is
usually sufficient).

The power dissipated by the MOSFET in a SEPIC con­verter is:

2

P

FET

= I

SW(MAX)

• R

DS(ON)

• D

MAX

I

L1(RMS)

where:

cL1=

I

L2(RMS)

where:

cL2=

= I

L1(MAX)

∆I

L1

I

L1 (MAX)

= I

L2(MAX)

∆I

L2

I

L2 (MAX )

• 1+

• 1+

2

c

L1

12

+ 2 • (V

The first term in this equation represents the conduction

IN(MIN)

+ V

OUT

)2 • I

L(MAX)

• C

RSS

• f /1A

losses in the device, and the second term, the switching
loss. C

is the reverse transfer capacitance, which is

RSS

usually specified in the MOSFET characteristics.

For maximum efficiency, R

DS(ON)

and C

should be

RSS

minimized. From a known power dissipated in the power

2

c

L2

12

MOSFET, its junction temperature can be obtained using
the following equation:

= TA + P

T

J

must not exceed the MOSFET maximum junction

T

J

• θJA = TA + P

FET

• (θJC + θCA)

FET

temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.

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SEPIC Converter: Output Diode Selection

To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current, and the peak current is equal to:

I

D(PEAK )



= 1+





c



• I



O(MAX)



2

•

1− D

1

MAX

It is recommended that the peak repetitive reverse voltage
rating V

is higher than V

RRM

OUT

+ V

IN(MAX)

by a safety

margin (a 10V safety margin is usually sufficient).

The power dissipated by the diode is:

P

D

= I

O(MAX)

• V

D

and the diode junction temperature is:

= TA + PD • R

T

J

The R

used in this equation normally includes the R

θJA

θJA

θJC

for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. T

must not

J

exceed the diode maximum junction temperature rating.

SEPIC Converter: Output and Input Capacitor Selection

The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
Please refer to the Boost Converter, Output Capacitor
Selection and Boost Converter, Input Capacitor Selection
sections.

CDC has nearly a rectangular current waveform. During
the switch off-time, the current through C
approximately –I

flows during the on-time. The RMS

O

is IIN, while

DC

rating of the coupling capacitor is determined by the fol­lowing equation:

I

RMS(CDC)

> I

O(MAX)

OUT

•

V

D

IN(MIN)

V

+ V

A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C

DC

.

INVERTING CONVERTER APPLICATIONS

The LT3757 can be configured as a dual-inductor inverting
topology, as shown in Figure 10. The V

V

− V

OUT

D

V

IN

= −

D

1− D

to VIN ratio is:

OUT

in continuous conduction mode (CCM).

C

+

M1

R

DC

SENSE

L2

–

C

D1

OUT

+

3757 F09

–

V

OUT

+

L1

V

IN

C

LT3757

IN

GATE

SENSE

GND

SEPIC Converter: Selecting the DC Coupling Capacitor

Figure 10. A Simplified Inverting Converter

The DC voltage rating of the DC coupling capacitor (C

DC

,
as shown in Figure 1) should be larger than the maximum
input voltage:

CDC

> V

IN(MAX)

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Inverting Converter: Switch Duty Cycle and Frequency

For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (V

The maximum duty cycle (D

) and the input voltage (VIN).

OUT

) occurs when the converter

MAX

has the minimum input voltage:

− V

V

D

=

MAX

V

OUT

OUT

− VD− V

D

IN(MIN)

Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections

The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an invert­ing converter are similar to those of the SEPIC converter.
Please refer to the corresponding SEPIC converter sections.

Inverting Converter: Output Capacitor Selection

The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
output capacitors are continuous. The output ripple voltage
is produced by the ripple current of L2 flowing through
the ESR and bulk capacitance of the output capacitor:

∆V

OUT(P –P)

= ∆IL2• ESR






COUT

+

8 • f • C



1




OUT

After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.

The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt­age ripple.

The RMS ripple current rating of the output capacitor
needs to be greater than:

I

RMS(COUT)

> 0.3 • ∆I

L2

Inverting Converter: Selecting the DC Coupling Capacitor

The DC voltage rating of the DC coupling capacitor (C

DC

,
as shown in Figure 10) should be larger than the maximum
input voltage minus the output voltage (negative voltage):

V

CDC

> V

IN(MAX)

– V

OUT

CDC has nearly a rectangular current waveform. During
the switch off-time, the current through C
approximately –I

flows during the on-time. The RMS

O

is IIN, while

DC

rating of the coupling capacitor is determined by the fol­lowing equation:

D

I

RMS(CDC)

> I

O(MAX)

•

1− D

MAX

MAX

A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C

DC

.

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Board Layout

The high speed operation of the LT3757 demands careful
attention to board layout and component placement. The
Exposed Pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the Exposed Pad and the ground
plane of the board. For the LT3757 to deliver its full output
power, it is imperative that a good thermal path be pro­vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.

To prevent radiation and high frequency resonance prob­lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies

C

IN

should be kept as tight as possible to reduce inductive
ringing:

• In boost configuration, the high di/dt loop contains

the output capacitor, the sensing resistor, the power
MOSFET and the Schottky diode.

• In flyback configuration, the high di

contains

the input capacitor, the primary winding, the

/dt primary loop

power MOSFET and the sensing resistor. The high di/
dt secondary loop contains the output capacitor, the
secondary winding and the output diode.

• In SEPIC configuration, the high di/dt loop contains

the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.

• In inverting configuration, the high di/dt loop contains

power MOSFET, sense resistor, Schottky diode and the
coupling capacitor.

V

IN

C

C1

C

C2

R1

R2

R

SS

R

T

VIAS TO GROUND
PLANE

R

C

1

2

3

4

5

LT3757

R3

10

9

8

7

6

C

OUT2

R4

C

VCC

1

2

R

S

M1

3

4

C

OUT1

L1

8

7

6

5

D1

Figure 11. 8V to 16V Input, 24V/2A Output Boost Converter Suggested Layout

3757 F10

V

OUT

26

3757afd

applicaTions inForMaTion

LT3757/LT3757A

Check the stress on the power MOSFET by measuring its
drain-to-source voltage directly across the device terminals
(reference the ground of a single scope probe directly to
the source pad on the PC board). Beware of inductive
ringing, which can exceed the maximum specified voltage
rating of the MOSFET. If this ringing cannot be avoided,
and exceeds the maximum rating of the device, either
choose a higher voltage device or specify an avalanche­rated power MOSFET.

The small-signal components should be placed away from
high frequency switching nodes. For optimum load regula­tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
the top of the output capacitor (Kelvin connection), staying
away from any high dV/dt traces. Place the divider resis­tors near the LT3757 in order to keep the high impedance
FBX node short.

Figure 11 shows the suggested layout of the 8V to 16V
Input, 24V/2A Output Boost Converter.

Recommended Component Manufacturers

Some of the recommended component manufacturers
are listed in Table 2.

Table 2. Recommended Component Manufacturers

VENDOR COMPONENTS WEB ADDRESS

AVX Capacitors avx.com

BH Electronics Inductors,

Coilcraft Inductors coilcraft.com

Cooper Bussmann Inductors bussmann.com

Diodes, Inc Diodes diodes.com

Fairchild MOSFETs fairchildsemi.com

General
Semiconductor

International Rectifier MOSFETs, Diodes irf.com

IRC Sense Resistors irctt.com

Kemet Capacitors kemet.com

Magnetics Inc Toroid Cores mag-inc.com

Microsemi Diodes microsemi.com

Murata-Erie Inductors,

Nichicon Capacitors nichicon.com

On Semiconductor Diodes onsemi.com

Panasonic Capacitors panasonic.com

Sanyo Capacitors sanyo.co.jp

Sumida Inductors sumida.com

Taiyo Yuden Capacitors t-yuden.com

TDK Capacitors,

Thermalloy Heat Sinks aavidthermalloy.com

Tokin Capacitors nec-tokinamerica.com

Toko Inductors tokoam.com

United Chemi-Con Capacitors chemi-con.com

Vishay/Dale Resistors vishay.com

Vishay/Siliconix MOSFETs vishay.com

Vishay/Sprague Capacitors vishay.com

Würth Elektronik Inductors we-online.com

Zetex Small-Signal

Transformers

Diodes generalsemiconductor.com

Capacitors

Inductors

Discretes

bhelectronics.com

murata.co.jp

component.tdk.com

zetex.com

3757afd

27

LT3757/LT3757A

Typical applicaTions

3.3V Input, 5V/10A Output Boost Converter

L1

V

3.3V

IN

C

IN

22µF

49.9k

6.3V
×2

41.2k
300kHz

CIN: TAIYO YUDEN JMK325BJ226MM
C

OUT1

C

OUT2

SHDN/UVLO

34k

0.1µF

: PANASONIC EEFUEOJ151R
: TAIYO YUDEN JMK325BJ226MM

SYNC

RT

SS

LT3757

V

C

6.8k

0.5µH

V

IN

INTV

CC

GATE

FBX

SENSE

GND

22nF 2.2nF

C

VCC

4.7µF
10V
X5R

22Ω

D1: MBRB2515L
L1: VISHAY SILICONIX IHLP-5050FD-01
M1: VISHAY SILICONIX SI4448DY

D1

M1

0.004Ω
1W

34k
1%

15.8k
1%

C

+

150µF

6.3V
×4

OUT1

V

OUT

5V
10A

C

OUT2

22µF

6.3V
X5R

×4

3757 TA02a

Efficiency vs Output Current

100

90

80

70

60

50

EFFICIENCY (%)

40

30

20

0.001

0.01

0.1 1 10

OUTPUT CURRENT (A)

3757 TA02b

V

3V TO 36V

Boost Preregulator for Automotive Stop-Start/Idle

IN

10µF
50V

1M

X5R
×2

698k

41.2k
300kHz

0.1µF

L1: COILTRONIX DR127-3R3
M1: VISHAY SILICONIX Si7848BDP
D1: VISHAY SILICONIX 50SQ04FN
C1: KEMET T495X106K050A

SHDN/UVLO

LT3757A

SYNC

RT

SS

V

C

10k

10nF 4.7µF

INTV

GATE

SENSE

GND

V

FBX

CC

3.3µH

IN

L1

M1

8mΩ

75k

16.2k

D1

10µF
50V
X5R

V

OUT

9V

MIN

2A

C1

+

10µF
50V

×4

3757 TA03a

Transient V

0V

and V

IN

OUT

OUTPUT POWER = 10W

10ms/DIV

Waveforms

3757 TA03b

V

OUT

5V/DIV
V

IN

5V/DIV

28

3757afd

Typical applicaTions

V

IN

8V TO 16V

R

T

41.2k
300kHz

C

IN

10µF
25V
X5R

8V to 16V Input, 24V/2A Output Boost Converter

C

100pF

C

SS

0.1µF

C2

R3
200k

R4

43.2k

SHDN/UVLO

LT3757

SYNC

RT
SS

VC

R

C

22k

C

C1

6.8nF

V

GND

IN

GATE

SENSE

FBX

INTV

CC

C

4.7µF
10V
X5R

VCC

L1
10µH

M1

R

S

0.01Ω
1W

D1

R2
226k
1%

R1

16.2k
1%

LT3757/LT3757A

V

OUT

24V
2A

C

OUT1

+

47µF
35V
×4

C

OUT2

10µF
25V
X5R

CIN, C
C
D1: ON SEMI MBRS340T3G
L1: VISHAY SILICONIX IHLP-5050FD-01 10µH
M1: VISHAY SILICONIX Si4840BDP

: MURATA GRM31CR61E106KA12

OUT2

: KEMET T495X476K035AS

OUT1

3757 TA04a

Efficiency vs Output Current Load Step Response at VIN = 12V

100

90

VIN = 8V

80

70

60

EFFICIENCY (%)

50

40

30

0.001

VIN = 16V

0.01

0.1 1

OUTPUT CURRENT (A)

10

3757 TA04b

V

500mV/DIV

(AC)

1.6A

I

OUT

1A/DIV

0.4A

OUT

500µs/DIV

3757 TA04c

3757afd

29

LT3757/LT3757A

Typical applicaTions

DANGER! HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

V

IN

5V TO 12V

C
47µF
16V
×4

140k
100kHz

IN

105k

46.4k

0.1µF

100pF

High Voltage Flyback Power Supply

SHDN/UVLO

SYNC

LT3757

RT
SS

V

C

6.8k

22nF

GND

INTV

GATE

SENSE

V

CC

FBX

IN

C

VCC

47µF
25V
X5R

22Ω

10nF

22Ω

220pF

V

0.02Ω

SW

•

T1

1:10

M1

D1

•

1.50M
1%

1M
1%

1M
1%

16.2k
1%

V
350V
10mA

C

OUT

68nF
×2

OUT

V

OUT

100V/DIV

: MURATA GRM32ER61C476K

C

IN

: TDK C3225X7R2J683K

C

OUT

D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
M1: VISHAY SILICONIX Si7850DP
T1: TDK DCT15EFD-U44S003

3757 TA05a

Start-Up Waveforms Switching Waveforms

V

OUT

5V/DIV

(AC)

V

SW

20V/DIV

2ms/DIV

3757 TA05b

5µs/DIV

3757 TA05c

30

3757afd

Typical applicaTions

+

V

IN

5.5V TO 36V

C

IN1

4.7µF
50V
×2

C

IN2

4.7µF
50V
×2

41.2k
300kHz

C

, CDC: TAIYO YUDEN UMK316BJ475KL

IN1

: KEMET T495X475K050AS

C

IN2

: KEMET T495X476K020AS

C

OUT1

C

: TAIYO YUDEN TMK432BJ106MM

OUT2

D1: ON SEMI MBRS360T3G
L1A, L1B: COILTRONICS DRQ127-4R7 (*COUPLED INDUCTORS)
M1: VISHAY SILICONIX Si7460DP

5.5V to 36V Input, 12V/2A Output SEPIC Converter

105k

46.4k

0.1µF

SHDN/UVLO

LT3757A

SYNC

RT
SS

V

C

10k

6.8nF

V

IN

GND

GATE

SENSE

INTV

FBX

CC

4.7µF
10V
X5R

V

•

L1A

SW

M1

0.01Ω
1W

I

L1A

50V, X5R, ×2

C

DC

4.7µF

I

L1B

LT3757/LT3757A

D1

L1B

•

105k
1%

15.8k
1%

C

+

47µF
20V

×4

3757 TA06a

OUT1

V
12V
2A

C

OUT2

10µF
25V
X5R

OUT

100

90

80

70

60

50

EFFICIENCY (%)

40

30

20

0.001

V

IN

V

OUT

5V/DIV

Efficiency vs Output Current Load Step Waveforms

VIN = 12V

V

OUT

VIN = 8V

0.01
OUTPUT CURRENT (A)

VIN = 16V

0.1 1

10

3757 TA06b

2V/DIV

AC-COUPLED

2A

I

OUT

2A/DIV

0A

500µs/DIV

3757 TA06c

Start-Up Waveforms Frequency Foldback Waveforms When Output Short-Circuits

= 12V

V

OUT

10V/DIV

V

SW

20V/DIV

V

= 12V

IN

I

+ I

L1A

I

L1A

+ I

L1B

5A/DIV

2ms/DIV

3757 TA06d

L1B

5A/DIV

50µs/DIV

3757 TA06e

3757afd

31

LT3757/LT3757A

Typical applicaTions

V

IN

5V TO 12V

C

IN2

+

47µF
16V

30.9k
400kHz

D1, D2: MBRS140T3
T1: COILTRONICS VP1-0076 (*PRIMARY = 4 WINDINGS IN PARALLEL)
M1: SILICONIX/VISHAY Si4840BDY

C

IN1

1µF
16V, X5R

0.1µF 100pF

105k

46.4k

SHDN/UVLO

SYNC

RT

SS

V

C

5V to 12V Input, ±12V/0.4A Output SEPIC Converter

22k

LT3757

6.8nF

V

GND

IN

GATE

SENSE

FBX

INTV

CC

C

4.7µF
10V
X5R

•

M1

0.02Ω

VCC

T1
1,2,3,4

C

DC1

4.7µF

16V, X5R

C

DC2

4.7µF
16V
X5R

•

D1

1.05k
1%

5

158Ω
1%

D2

6

•

3757 TA07

C

OUT2

4.7µF
16V, X5R
×3

C

OUT2

4.7µF
16V, X5R
×3

V

OUT1

12V

0.4A

GND

V

OUT2

–12V

0.4A

V

5V TO 16V

Nonisolated Inverting SLIC Supply

VP5-0155 (PRIMARY = 3 WINDINGS IN PARALLEL)

D1

IN

63.4k
200kHz

C

IN

22µF
25V, X5R
×2

0.1µF

R2
105k

R1

46.4k

100pF

SHDN/UVLO

LT3757

SYNC

RT

SS

V

C

9.1k

10nF

V

IN

GND

SENSE

INTV

GATE

FBX

CC

15.8k

C

VCC

4.7µF
10V, X5R

C2
10µF
50V
X5R

M1
Si7850DP

0.012Ω

0.5W

T1

1,2,3

464k

DFLS160

GND

•

4

•

D2

DFLS160

5

•

D3

DFLS160

6

•

C3
22µF
25V
X5R

C4
22µF
25V
X5R

C5
22µF
25V
X5R

3757 TA08

C

OUT

3.3µF
100V

V

OUT1

–24V
200mA

V

OUT1

–72V
200mA

32

3757afd

package DescripTion

DD Package

LT3757/LT3757A

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

0.70 ±0.05

3.55 ±0.05

1.65 ±0.05
(2 SIDES)2.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

0.50
BSC

(2 SIDES)

3.00 ±0.10
(4 SIDES)

0.75 ±0.05

1.65 ± 0.10
(2 SIDES)

0.00 – 0.05

R = 0.125

TYP

2.38 ±0.10
(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

106

15

0.50 BSC

0.40 ± 0.10

0.25 ± 0.05

PIN 1 NOTCH
R = 0.20 OR

0.35 × 45°
CHAMFER

(DD) DFN REV C 0310

3757afd

33

LT3757/LT3757A

MSE Package

package DescripTion

1.88 ±0.102

(.074 ±.004)

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev H)

BOTTOM VIEW OF

EXPOSED PAD OPTION

0.889 ±0.127
(.035 ±.005)

1

1.88

(.074)

1.68

(.066)

0.29
REF

5.23

(.206)

MIN

0.305 ± 0.038

(.0120 ±.0015)

TYP

RECOMMENDED SOLDER PAD LAYOUT

1.68 ±0.102
(.066 ±.004)

0.50

(.0197)

BSC

3.20 – 3.45

(.126 – .136)

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

10

8910

7

6

4.90 ±0.152

PLANE

(.193 ±.006)

(.043)

0.17 –0.27

(.007 – .011)

TYP

1.10

MAX

1 2

0.50

(.0197)

BSC

4 5

3

0.254
(.010)

GAUGE PLANE

0.18

(.007)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

DETAIL “A”

0° – 6° TYP

0.53 ±0.152
(.021 ±.006)

DETAIL “A”

SEATING

DETAIL “B”

0.497 ±0.076

(.0196 ±.003)

3.00 ±0.102
(.118 ±.004)

(NOTE 4)

0.86

(.034)

REF

0.1016 ±0.0508
(.004 ±.002)

MSOP (MSE) 0911 REV H

0.05 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

REF

34

3757afd

LT3757/LT3757A

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

B 3/10 Deleted Bullet from Features and Last Line of Description

Updated Entire Page to Add H-Grade and Military Grade
Updated Electrical Characteristics Notes and Typical Performance Characteristics for H-Grade and Military Grade
Revised TA04a and Replaced TA04c in Typical Applications
Updated Related Parts

C 5/11 Revised MP-grade temperature range in Absolute Maximum Ratings and Order Information sections

Revised Note 2
Revised formula in Applications Information
Updated Typical Application drawing TA04a values
Revised Typical Application title TA06

D 07/12 Added LT3757A version Throughout

Updated Block Diagram 8

Updated Programming the Output Voltage section 12

Updated Loop Compensation section 13

Added an application circuit in the Typical Applications section 28

Updated the schematic and Load Step Waveforms in the Typical Applications section 31

(Revision history begins at Rev B)

1
2

4 to 6

30
36

2

4
19
30
32

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3757afd

35

LT3757/LT3757A

Typical applicaTion

High Efficiency Inverting Power Supply

V

IN

5V TO

15V

C

R2

IN

47µF

105k

16V
X5R

R1

46.4k

41.2k
300kHz

0.1µF

L1, L2: COILTRONICS DRQ127-3R3 (*COUPLED INDUCTORS)

SHDN/UVLO

LT3757

SYNC

RT
SS

V

C

9.1k

10nF

V

GND

IN

INTV

GATE

SENSE

FBX

CC

C

VCC

4.7µF
10V
X5R

L1

•

25V, X5R

M1
Si7848BDP

0.006Ω
1W

C

DC

47µF

L2

D1
MBRD835L

V

•

84.5k

16k

OUT

–5V
3A to 5A

C

OUT

100µF

6.3V, X5R
×2

3757 TA09a

Efficiency vs Output Current

100

90

80

70

60

50

EFFICIENCY (%)

40

30

20

10

0.001

VIN = 5V

0.01
OUTPUT CURRENT (A)

VIN = 16V

0.1 1

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LT3758A Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V

Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages

LT3759 Boost, SEPIC and Inverting Controller 1.6V ≤ V

Operation Frequency, MSOP-12E Packages

LT3957A Boost, Flyback, SEPIC and Inverting Controller

with 5A, 40V Switch

LT3958 Boost, Flyback, SEPIC and Inverting Controller

with 3.3A, 84V Switch

LT3573/LT3574/

40V Isolated Flyback Converters Monolithic No-Opto Flybacks with Integrated 1.25A/0.65A/2.5A Switch

3V ≤ V
Frequency, 5mm × 6mm QFN Package

5V ≤ V
Frequency, 5mm × 6mm QFN Package

LT3575

LT3511/LT3512 100V Isolated Flyback Converters Monolithic No-Opto Flybacks with Integrated 240mA/420mA Switch

LT3798 Offline Isolated No Opto-Coupler Flyback

V

IN

Controller with Active PFC

LT3799/LT3799-1 Offline Isolated Flyback LED Controllers with

V

IN

Active PFC

≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable

IN

≤ 42V, Current Mode Control, 100kHz to 1MHz Programmable

IN

≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation

IN

≤ 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation

IN

and V

and V

Limited Only by External Components, MSOP-16 Package

OUT

Limited Only by External Components, MSOP-16 Package

OUT

10

3757 TA09b

36

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

3757afd

LT 0712 REV D • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2008