LT3083
Adjustable 3A
Single Resistor Low
Dropout Regulator
FEATURES
n
Outputs May be Paralleled for Higher Current and
Heat Spreading
n
Output Current: 3A
n
Single Resistor Programs Output Voltage
n
50µA Set Pin Current: 1% Initial Accuracy
n
Output Adjustable to 0V
n
Low Output Noise: 40µV
n
Wide Input Voltage Range: 1.2V to 23V
(10Hz to 100kHz)
RMS
(DD-Pak and TO-220 Packages)
n
Low Dropout Voltage: 310mV
n
<1mV Load Regulation
n
<0.001%/V Line Regulation
n
Minimum Load Current: 1mA
n
Stable with Minimum 10µF Ceramic Capacitor
n
Current Limit with Foldback and Overtemperature
Protection
n
Available in 16-Lead TSSOP, 12-Lead 4mm × 4mm
DFN, 5-Lead TO-220 and 5-Lead Surface Mount
DD-PAK Packages
APPLICATIONS
n
High Current All Surface Mount Supply
n
High Efficiency Linear Regulator
n
Post Regulator for Switching Supplies
n
Low Parts Count Variable Voltage Supply
n
Low Output Voltage Power Supplies
DESCRIPTION
The LT®3083 is a 3A low dropout linear regulator that can
be paralleled to increase output current or spread heat on
surface mounted boards. Architected as a precision current
source and voltage follower, this new regulator finds use
in many applications requiring high current, adjustability
to zero, and no heat sink. The device also brings out the
collector of the pass transistor to allow low dropout operation—down to 310mV—when used with multiple supplies.
A key feature of the LT3083 is the capability to supply a
wide output voltage range. By using a reference current
through a single resistor, the output voltage is programmed
to any level between zero and 23V (DD-PAK and TO-220
packages). The LT3083 is stable with 10µF of capacitance
on the output, and the IC is stable with small ceramic capacitors that do not require additional ESR as is common
with other regulators.
Internal protection circuitry includes current limiting and
thermal limiting. The LT3083 is offered in the 16-lead
TSSOP (with an exposed pad for better thermal characteristics), 12-lead 4mm × 4mm DFN (also with an exposed
pad), 5-lead TO-220, and 5-lead surface mount DD-PAK
packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.5V to 0.9V at 3A Supply (Using 3.3V V
V
CONTROL
3.3V
V
1.5V
IN
4.7µF
10µF
V
CONTROL
LT3083
SET
R
SET
18.2k
1%
OUTIN
3083 TA01a
0.1µF
10µF
CONTROL
*
R
MIN
909Ω
)
V
= 0.9V
OUT
= 3A
I
MAX
*OPTIONAL FOR
MINIMUM 1mA LOAD
REQUIREMENT
Set Pin Current Distribution
N = 1052
49
49.5 50 50.5
SET PIN CURRENT DISTRIBUTION (µA)
3083 TA01b
51
3083fa
1
LT3083
ABSOLUTE MAXIMUM RATINGS
(Note 1) All Voltages Relative to V
CONTROL Pin Voltage .............................................±28V
IN Pin Voltage (T5, Q Packages)
No Overload or Short-Circuit
IN Pin Voltage (DF, FE Packages)
No Overload or Short-Circuit
SET Pin Current (Note 7)
SET Pin Voltage (Relative to OUT)
OUT
....................18V, –0.3V
.....................23V, –0.3V
.....................8V, –0.3V
.....................14V, –0.3V
.....................................±25mA
.......................... ±10V
PIN CONFIGURATION
TOP VIEW
1
OUT
2
OUT
3
OUT
OUT
OUT
SET
12-LEAD (4mm × 4mm) PLASTIC DFN
= 125°C, θJA = 37°C/W, θJC = 8°C/W
T
JMAX
EXPOSED PAD (PIN 13) IS OUT, MUST BE SOLDERED TO PCB
4
5
6
13
OUT
DF PACKAGE
12
11
10
9
8
7
IN
IN
IN
IN
V
CONTROL
V
CONTROL
Output Short-Circuit Duration .......................... Indefinite
Operating Junction Temperature Range (Notes 2, 10)
E-, I-grades
MP-grade
Storage Temperature Range
........................................ –40°C to 125°C
........................................... –55°C to 125°C
.................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
T, Q, FE Packages Only
OUT
OUT
OUT
OUT
OUT
OUT
SET
OUT
16-LEAD PLASTIC TSSOP
= 125°C, θJA = 25°C/W, θJC = 8°C/W
T
JMAX
EXPOSED PAD (PIN 17) IS OUT, MUST BE SOLDERED TO PCB
..................................... 300°C
TOP VIEW
1
2
3
4
5
6
7
8
FE PACKAGE
17
OUT
OUT
16
IN
15
IN
14
IN
13
IN
12
V
11
CONTROL
V
10
CONTROL
OUT
9
FRONT VIEW
TAB IS
OUT
Q PACKAGE
5-LEAD PLASTIC DD-PAK
= 125°C, θJA = 15°C/W, θJC = 3°C/W
T
JMAX
5
4
3
2
1
IN
V
CONTROL
OUT
SET
NC
TAB IS
OUT
T
JMAX
FRONT VIEW
5
4
3
2
1
T PACKAGE
5-LEAD PLASTIC TO-220
= 125°C, θJA = 40°C/W, θJC = 3°C/W
IN
V
CONTROL
OUT
SET
NC
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3083EDF#PBF LT3083EDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083EFE#PBF LT3083EFE#TRPBF 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3083EQ#PBF LT3083EQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083ET#PBF LT3083ET#TRPBF LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083IDF#PBF LT3083IDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083IFE#PBF LT3083IFE#TRPBF 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
3083fa
2
LT3083
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3083IQ#PBF LT3083IQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083IT#PBF LT3083IT#TRPBF LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083MPDF#PBF LT3083MPDF#TRPBF 3083 12-Lead (4mm × 4mm) Plastic DFN –55°C to 125°C
LT3083MPFE#PBF LT3083MPFE#TRPBF 3083FE 16-Lead Plastic TSSOP –55°C to 125°C
LT3083MPQ#PBF LT3083MPQ#TRPBF LT3083Q 5-Lead Plastic DD-PAK –55°C to 125°C
LT3083MPT#PBF LT3083MPT#TRPBF LT3083T 5-Lead Plastic TO-220 –55°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3083EDF LT3083EDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083EFE LT3083EFE#TR 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3083EQ LT3083EQ#TR LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083ET LT3083ET#TR LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083IDF LT3083IDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT3083IFE LT3083IFE#TR 3083FE 16-Lead Plastic TSSOP –40°C to 125°C
LT3083IQ LT3083IQ#TR LT3083Q 5-Lead Plastic DD-PAK –40°C to 125°C
LT3083IT LT3083IT#TR LT3083T 5-Lead Plastic TO-220 –40°C to 125°C
LT3083MPDF LT3083MPDF#TR 3083 12-Lead (4mm × 4mm) Plastic DFN –55°C to 125°C
LT3083MPFE LT3083MPFE#TR 3083FE 16-Lead Plastic TSSOP –55°C to 125°C
LT3083MPQ LT3083MPQ#TR LT3083Q 5-Lead Plastic DD-PAK –55°C to 125°C
LT3083MPT LT3083MPT#TR LT3083T 5-Lead Plastic TO-220 –55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2).
PARAMETER CONDITIONS MIN TYP MAX UNITS
SET Pin Current I
– V
Output Offset Voltage (V
V
= 1V, V
IN
CONTROL
= 2V, I
OUT
LOAD
) VOS
SET
= 1mA
Load Regulation (DF, FE Packages) ∆I
∆V
Load Regulation (T, Q Packages) ∆I
∆V
Line Regulation (DF, FE Packages) ∆I
∆V
Line Regulation (T, Q Packages) ∆I
∆V
Minimum Load Current (Notes 3, 9) V
SET
VIN = 1V, V
V
≥ 1V, V
IN
CONTROL
CONTROL
= 2V, I
= 1mA, TJ = 25°C
LOAD
≥ 2V, 5mA ≤ I
≤ 3A (Note 9)
LOAD
DF, FE Packages
T, Q Packages
∆I
SET
OS
SET
OS
SET
OS
SET
OS
= 1mA to 3A
LOAD
∆I
= 5mA to 3A (Note 8)
LOAD
∆I
= 1mA to 3A
LOAD
∆I
= 5mA to 3A (Note 8)
LOAD
∆VIN = 1V to 14V, ∆V
∆V
= 1V to 14V, ∆V
IN
∆VIN = 1V to 23V, ∆V
∆V
= 1V to 23V, ∆V
IN
= 1V, V
IN
V
IN
CONTROL
= 14V (DF/FE) or 23V (T/Q), V
CONTROL
CONTROL
CONTROL
CONTROL
= 2V
= 2V to 25V, I
= 2V to 25V, I
= 2V to 25V, I
= 2V to 25V, I
CONTROL
LOAD
LOAD
LOAD
LOAD
= 25V
= 1mA
= 1mA
= 1mA
= 1mA
49.5 4950 5050.5
l
–3
–4
l
–4
–6
l
l
l
–10
–0.4 –1
–10
–0.7 –4
0.1
0.002 0.01
0.1
0.002 0.01
l
l
350 500
51
0
0
0
0
3
4
4
6
µA
mV
mV
mV
mV
nA
mV
nA
mV
nA/V
mV/V
nA/V
mV/V
µA
µA
1
mA
3083fa
3
LT3083
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2).
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
V
V
Dropout Voltage (Note 4) I
CONTROL
Dropout Voltage (Note 4) I
IN
Pin Current (Note 5) I
CONTROL
Current Limit V
Error Amplifier RMS Output Noise (Note 6) I
Reference Current RMS Output Noise (Note 6) 10Hz ≤ f ≤ 100kHz 1 nA
Ripple Rejection
V
= 0.5V
RIPPLE
C
= 10µF
OUT
Thermal Regulation, I
, IL = 0.1A, C
P-P
SET
= 0.1µF,
SET
= 100mA
LOAD
I
= 1A
LOAD
I
= 3A
LOAD
= 100mA
LOAD
= 1A, Q, T Packages
I
LOAD
I
= 1A, DF, FE Packages
LOAD
= 3A, Q, T Packages
I
LOAD
I
= 3A, DF, FE Packages
LOAD
= 100mA
LOAD
I
= 1A
LOAD
I
= 3A
LOAD
= 5V, V
IN
= 500mA, 10Hz ≤ f ≤ 100kHz, C
LOAD
CONTROL
= 5V, V
f = 120Hz
f = 10kHz
f = 1MHz
SET
= 0V, V
OUT
OUT
= –0.1V
= 10µF, C
l
l
l
l
l
l
l
l
l
l
l
= 0.1µF 40 µV
SET
1.2
1.22
1.25
1.55
1.6
10 25 mV
120 90190
160
310
240
5.5
18
40
510
420
10
35
80
mV
mV
mV
mV
mA
mA
mA
3 3.7 A
RMS
RMS
85
75
20
dB
dB
dB
10ms Pulse 0.003 %/W
V
V
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Unless otherwise specified, all voltages are with respect to V
OUT.
The LT3083 is tested and specified under pulse load conditions such that
T
≅ TA. The LT3083E is 100% tested at TA = 25°C. Performance of the
J
LT3083E over the full –40°C to 125°C operating junction temperature
range is assured by design, characterization, and correlation with
statistical process controls. The LT3083I regulators are guaranteed
over the full –40°C to 125°C operating junction temperature range. The
LT3083MP is 100% tested and guaranteed over the –55°C to 125°C
operating junction temperature range.
Note 3: Minimum load current is equivalent to the quiescent current of
the part. Since all quiescent and drive current is delivered to the output
of the part, the minimum load current is the minimum current required to
maintain regulation.
Note 4: For the LT3083, dropout is caused by either minimum control
voltage (V
) or minimum input voltage (VIN). Both parameters are
CONTROL
specified with respect to the output voltage. The specifications represent
the minimum input-to-output differential voltage required to maintain
regulation.
Note 5: The V
pin current is the drive current required for the
CONTROL
output transistor. This current will track output current with roughly a 1:60
ratio. The minimum value is equal to the quiescent current of the device.
Note 6: Output noise is lowered by adding a small capacitor across the
voltage setting resistor. Adding this capacitor bypasses the voltage setting
resistor shot noise and reference current noise; output noise is then equal
to error amplifier noise (see the Applications Information section).
Note 7: The SET pin is clamped to the output with diodes through 1k
resistors. These resistors and diodes will only carry current under
transient overloads.
Note 8: Load regulation is Kelvin sensed at the package.
Note 9: Current limit includes foldback protection circuitry. Current limit
decreases at higher input-to-output differential voltages.
Note 10: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Overtemperature protection
(thermal limit) is typically active at junction temperatures of 165°C.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
4
3083fa
LT3083
TYPICAL PERFORMANCE CHARACTERISTICS
SET Pin Current Set Pin Current Distribution
50.5
50.4
50.3
50.2
50.1
50.0
49.9
49.8
SET PIN CURRENT (µA)
49.7
49.6
49.5
–50
50
25–25 0 75 100 125
TEMPERATURE (°C)
150
3083 G01
Offset Voltage Distribution Offset Voltage (V
N = 1052
–2 –1 0 21
–3
V
DISTRIBUTION (mV)
OS
3
3083 G04
N = 1052
49
1.00
0.75
0.50
0.25
0
–0.25
OFFSET VOLTAGE (mV)
–0.50
–0.75
–1.00
49.5 50 50.5
SET PIN CURRENT DISTRIBUTION (µA)
I
= 5mA
LOAD
0
5
INPUT-TO-OUTPUT VOLTAGE (V)
– V
OUT
SET
10 15 20
TA = 25°C, unless otherwise noted.
Offset Voltage (V
1.0
I
= 5mA
LOAD
0.8
0.6
0.4
0.2
0
–0.2
–0.4
OFFSET VOLTAGE (mV)
–0.6
–0.8
3083 G02
–1.0
51
–50
25–25 0 75 100 125
TEMPERATURE (°C)
) Offset Voltage (V
0.25
3083 G05
–0.25
–0.50
–0.75
–1.00
OFFSET VOLTAGE (mV)
–1.25
–1.50
–1.75
25
0
0
0.5
TJ = 25°C
TJ = 125°C
1 1.5 2.52
LOAD CURRENT (A)
50
OUT
OUT
– V
– V
SET
SET
)
150
3083 G03
)
3
3083 G06
Load Regulation Minimum Load Current
0
CHANGE IN OFFSET VOLTAGE (V
–0.2
–0.4
CHANGE IN REFERENCE CURRENT
–0.6
–0.8
–1.0
–1.2
–1.4
∆I
= 5mA TO 3A
LOAD
= V
V
IN
CHANGE IN OFFSET VOLTAGE WITH LOAD (mV)
–1.6
–50
= V
CONTROL
OUT
50
25–25 0 75 100 125
TEMPERATURE (°C)
+ 2V
OUT
– V
SET
3083 G07
CHANGE IN REFERENCE CURRENT WITH LOAD (nA)
1.4
VIN = V
CONTROL
1.2
1.0
0.8
0.6
0.4
MINIMUM LOAD CURRENT (mA)
0.2
0
–50
V
IN,CONTROL
V
IN,CONTROL
TEMPERATURE (°C)
)
150
100
50
0
–50
–100
–150
–200
–250
–300
– V
= 23V
OUT
– V
= 1.5V
OUT
25–25 0 75 100 125
50
) (mV)
– V
MINIMUM VOLTAGE (V
150
3083 G08
Dropout Voltage, T/Q Packages
(Minimum IN Voltage)
400
OUT
IN
100
350
300
250
200
150
TJ = 25°C
50
0
0
0.5
TJ = 125°C
1 1.5 2 2.5
LOAD CURRENT (A)
TJ = –50°C
3
3083 G09
3083fa
5
LT3083
TYPICAL PERFORMANCE CHARACTERISTICS
= 25°C, unless otherwise noted.
T
A
Dropout Voltage, FE/DF Packages
400
350
) (mV)
300
OUT
– V
250
IN
200
150
100
50
MINIMUM VOLTAGE (V
0
0
0.5
TJ = 25°C
LOAD CURRENT (A)
TJ = 125°C
TJ = –50°C
1 1.5 2 2.5
Dropout Voltage (Minimum
V
CONTROL
1.6
1.4
TJ = –50°C
1.2
) (V)
1.0
OUT
PIN VOLTAGE
– V
0.8
CONTROL
0.6
CONTROL
(V
0.4
MINIMUM V
0.2
0
0
0.5
3
3083 G10
Pin Voltage)
TJ = 25°C
TJ = 125°C
1 1.5 2 2.5
LOAD CURRENT (A)
Dropout Voltage, T/Q Packages
(Minimum IN Voltage)
500
450
) (mV)
400
OUT
350
– V
IN
300
250
200
150
100
50
MINIMUM IN VOLTAGE (V
0
–50
3083 G13
I
LOAD
3
= 3A
I
LOAD
I
= 500mA
LOAD
25–25 0 75 100 125
50
TEMPERATURE (°C)
= 1.5A
I
= 100mA
LOAD
150
3083 G11
Dropout Voltage (Minimum
V
CONTROL
1.6
1.4
1.2
) (V)
1.0
OUT
PIN VOLTAGE
– V
0.8
CONTROL
0.6
CONTROL
(V
0.4
MINIMUM V
0.2
0
–50
Pin Voltage)
25–25 0 75 100 125
TEMPERATURE (°C)
Dropout Voltage, FE/DF Packages
(Minimum IN Voltage)
500
450
) (mV)
400
OUT
350
– V
IN
300
250
200
150
100
50
MINIMUM IN VOLTAGE (V
0
–50
I
= 3A
LOAD
50
I
= 3A
LOAD
I
= 1.5A
LOAD
I
= 500mA
LOAD
I
LOAD
25–25 0 75 100 125
50
TEMPERATURE (°C)
150
3083 G14
= 100mA
150
3083 G12
6
Current Limit
5.0
4.5
4.0
3.5
3.0
2.5
2.0
CURRENT LIMIT (A)
1.5
1.0
VIN = V
0
–50
CONTROL
= 0V
V
OUT
0.5
= 7V
50
25–25 0 75 100 125
TEMPERATURE (°C)
3083 G15
150
Current Limit
4.0
3.5
3.0
2.5
2.0
1.5
CURRENT LIMIT (A)
1.0
0.5
0
0
IN-TO-OUT DIFFERENTIAL (V
5 10 15
– V
IN
TJ = 25°C
) (V)
OUT
3083 G16
20
3083fa
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient Response Load Transient Response
150
VIN = 2V
= 3V
V
100
CONTROL
= 1V
V
OUT
= 0.1µF
C
SET
50
0
DEVIATION (mV)
–50
–100
1.0
0.5
LOAD CURRENT (A) OUTPUT VOLTAGE
0
0
C
= 22µF CERAMIC
OUT
C
= 10µF CERAMIC
OUT
∆I
= 100mA TO 1A
LOAD
80
6020 40 140 160100 120 180
TIME (µs)
3083 G17
200
Line Transient Response Turn-On Response Turn-On Response
7
6
5
CONTROL
4
VOLTAGE (V)
IN/ V
3
10
0
–10
DEVIATION (mV)
OUTPUT VOLTAGE
–20
0
V
= 1V
OUT
= 10mA
I
LOAD
= 10µF CERAMIC
C
OUT
= 0.1µF
C
SET
80
6020 40 140 160100 120 180
TIME (µs)
200
3083 G19
6
5
4
3
CONTROL
2
VOLTAGE (V)
IN/ V
1
0
1.0
0.5
0
OUTPUT
VOLTAGE (V)
–0.5
0
155 10 35 4025 30 45
250
150
–50
DEVIATION (mV)
–150
LOAD CURRENT (A) OUTPUT VOLTAGE
R
= 20k
SET
= 0
C
SET
R
LOAD
= 10µF CERAMIC
C
OUT
20
TIME (µs)
50
4
2
0
0
= 0.33Ω
= 25°C, unless otherwise noted.
T
A
VIN = 2V
= 3V
V
CONTROL
= 1V
V
OUT
= 0.1µF
C
SET
C
= 22µF CERAMIC
OUT
∆I
= 500mA TO 3A
LOAD
80 200
6020 40 140 160100 120 180
TIME (µs)
4
3
2
CONTROL
1
VOLTAGE (V)
IN/ V
0
1.0
0.5
0
OUTPUT
VOLTAGE (V)
–0.5
50
3083 G20
0
LT3083
3083 G18
R
= 20k
SET
= 0.1µF
C
SET
= 1Ω
R
LOAD
= 10µF CERAMIC
C
OUT
62 4 14 1610 12 18
8
TIME (ms)
20
3083 G21
V
CONTROL
80
70
60
50
40
I
PIN CURRENT (mA)
30
20
CONTROL
V
10
LOAD
I
= 1.5A
LOAD
0
0
2
4 6 8 10 12 14 16
IN-TO-OUT DIFFERENTIAL (V
Pin Current V
70
60
50
40
= 3A
DEVICE IN
CURRENT LIMIT
– V
) (V)
IN
OUT
3083 G22
18
30
PIN CURRENT (mA)
20
CONTROL
V
10
0
CONTROL
V
CONTROL
– V
V
IN
TJ = 25°C
0
Pin Current
– V
= 2V
OUT
= 1V
OUT
1 1.5 2 2.5
0.5
LOAD CURRENT (A)
TJ = –50°C
TJ = 125°C
3083 G23
600
500
400
300
200
OUTPUT VOLTAGE (mV)
100
3
Residual Output Voltage with
Less Than Minimum Load
V
= 20V
IN
V
= 10V
IN
V
= 5V
IN
ADD 1N4148 FOR
SET PIN = 0V
V
IN
0
0
500 1000 1500
(Ω)
R
SET
R
TEST
< 1k
V
OUT
R
TEST
3083 G24
2000
3083fa
7
LT3083
TYPICAL PERFORMANCE CHARACTERISTICS
Ripple Rejection, Dual Supply,
Ripple Rejection, Single Supply
100
90
80
70
60
I
I
LOAD
C
= 10µF CERAMIC
OUT
= 0.1µF CERAMIC
C
SET
RIPPLE = 50mV
V
– V
IN
0
10
100
LOAD
= 0.5A
CONTROL
50
40
30
RIPPLE REJECTION (dB)
20
10
I
= 0.1A
LOAD
= 1.5A
P-P
= V
OUT(NOMINAL)
1k 10k 100k 1M
FREQUENCY (Hz)
Ripple Rejection (120Hz)
80
79
78
77
76
75
74
73
RIPPLE REJECTOIN (dB)
VIN = V
72
71
70
CONTROL
RIPPLE = 500mV
= 0.5A
I
LOAD
= 0.1µF, C
C
SET
–50
+ 2V
10M
3083 G25
= V
OUT(NOMINAL)
, ƒ = 120Hz
P-P
= 10µF
OUT
25–25 0 75 100 125
50
TEMPERATURE (°C)
V
CONTROL
120
105
90
75
60
I
LOAD
45
RIPPLE REJECTION (dB)
30
C
C
15
V
V
0
10
+ 2V
3083 G28
Pin
I
LOAD
= 1.5A
= 10µF CERAMIC
OUT
= 0.1µF
SET
= V
IN
OUT(NOMINAL)
= V
CONTROL
100
150
= 0.1A
+ 1V
OUT(NOMINAL)
1k 10k 100k 1M
FREQUENCY (Hz)
+ 2V
Noise Spectral Density
1000
100
ERROR AMPLIFIER NOISE
SPECTRAL DENSITY (nV/√Hz)
10
10
TA = 25°C, unless otherwise noted.
Ripple Rejection, Dual Supply,
IN Pin
120
I
LOAD
I
LOAD
= 1.5A
+ 1V
OUT(NOMINAL)
1k 10k 100k 1M
FREQUENCY (Hz)
100
10
1
100k
3083 G29
10M
3083 G26
100
105
90
75
60
45
RIPPLE REJECTION (dB)
30
C
C
15
V
V
0
10
1k 10k
FREQUENCY (Hz)
I
LOAD
= 10µF CERAMIC
OUT
= 0.1µF
SET
= V
IN
OUT(NOMINAL)
= V
CONTROL
100
= 0.1A
= 0.5A
+ 2V
10M
3083 G27
SPECTRAL DENSITY (pA/√Hz)
REFERENCE CURRENT NOISE
8
V
OUT
100µV/DIV
Output Voltage Noise Error Amplifier Gain and Phase
21
18
PHASE
15
12
9
6
3
0
GAIN (dB)
GAIN
–3
V
C
I
LOAD
OUT
SET
= 1V, R
= 0.1µF, C
= 3A
TIME 1ms/DIV
= 20k
SET
= 10µF
OUT
3083 G30
–6
–9
–12
–15
I
= 0.5A
LOAD
= 1.5A
I
LOAD
= 3A
I
LOAD
10
100
1k 10k 100k
FREQUENCY (Hz)
3083 G31
1M
36
0
–36
–72
–108
–144
–180
–216
–252
–288
–324
–360
–396
3083fa
LT3083
PIN FUNCTIONS
(DF/FE/Q/T Packages)
OUT (Pins 1-5,13/Pins 1-6,8,9,16,17/ Pin 3, Tab/ Pin 3,
Tab): Output. The exposed pad of the DF package (Pin 13)
and the FE package (Pin 17) and the Tab of the DD-PAK
and TO-220 packages is an electrical connection to OUT.
Connect the exposed pad of the DF and FE packages and
the Tab of the DD-PAK package directly to OUT on the
PCB and the respective OUT pins for each package. There
must be a minimum load current of 1mA or the output
may not regulate.
SET (Pin 6/Pin 7/Pin 2/Pin 2): Set Point. This pin is the
non-inverting input to the error amplifier and the regulation set point. A fixed current of 50μA flows out of this
pin through a single external resistor, which programs
the output voltage of the device. Output voltage range is
zero to the V
IN(MAX)
– V
DROPOUT
. Transient performance
can be improved by adding a small capacitor from the
SET pin to ground.
V
CONTROL
(Pins 7,8/Pins 10,11/ Pin 4/Pin 4): Bias Sup-
ply. This is the supply pin for the control circuitry of the
device. Minimum input capacitance is 2.2µF (see Input
Capacitance and Stability in the Applications Information
section). The current flow into this pin is about 1.7% of
the output current. For the device to regulate, this voltage
must be more than 1.2V to 1.4V greater than the output
voltage (see dropout specifications in the Electrical Characteristics section).
IN (Pins 9-12/ Pins 12-15/Pin 5/Pin 5): Power Input. This
is the collector to the power device of the LT3083. The
output load current is supplied through this pin. Minimum
IN capacitance is 10µF (see Input Capacitance and Stability in Applications Information section). For the device to
regulate, the voltage at this pin must be more than 0.1V
to 0.5V greater than the output voltage (see dropout
specifications in the Electrical Characteristics section).
NC (NA/ NA/Pin 1/Pin 1): No Connection. No Connect pins
have no connection to internal circuitry and may be tied
to V
IN
, V
CONTROL
, V
, GND, or floated.
OUT
BLOCK DIAGRAM
V
CONTROL
IN
50µA
+
–
3083 BD
OUTSET
3083fa
9
LT3083
APPLICATIONS INFORMATION
The LT3083 regulator is easy to use and has all the protection
features expected in high performance regulators. Included
are short-circuit protection and safe operating area protection, as well as thermal shutdown with hysteresis.
The LT3083 fits well in applications needing multiple rails.
This new architecture adjusts down to zero with a single
resistor, handling modern low voltage digital IC’s as well as
allowing easy parallel operation and thermal management
without heat sinks. Adjusting to zero output allows shutting
off the powered circuitry. When the input is pre-regulated,
such as with a 5V or 3.3V input supply, external resistors
can help spread the heat.
A precision “0” TC 50μA reference current source connects
to the noninverting input of a power operational amplifier.
The power operational amplifier provides a low impedance
buffered output to the voltage on the noninverting input.
A single resistor from the noninverting input to ground
sets the output voltage. If this resistor is set to 0Ω, zero
output voltage results. Therefore, any output voltage can
be obtained between zero and the maximum defined by
the input power supply.
The benefit of using a true internal current source as the
reference, as opposed to a bootstrapped reference in older
regulators, is not so obvious in this architecture. A true
reference current source allows the regulator to have gain
and frequency response independent of the impedance on
the positive input. On older adjustable regulators, such as
the LT1086, loop gain changes with output voltage and
bandwidth changes if the adjustment pin is bypassed to
ground. For the LT3083, the loop gain is unchanged with
output voltage changes or bypassing. Output regulation
is not a fixed percentage of output voltage, but is a fixed
fraction of millivolts. Use of a true current source allows
all of the gain in the buffer amplifier to provide regulation,
and none of that gain is needed to amplify up the reference
to a higher output voltage.
The LT3083 has the collector of the output transistor connected to a separate pin from the control input. Since the
dropout on the collector (IN pin) is typically only 310mV,
two supplies can be used to power the LT3083 to reduce
dissipation: a higher voltage supply for the control circuitry
and a lower voltage supply for the collector. This increases
efficiency and reduces dissipation. To further spread the
heat, a resistor inserted in series with the collector moves
some of the heat out of the IC to spread it on the PC board
(see the section
Reducing Power Dissipation
).
The LT3083 can be operated in two modes. Three terminal mode has the V
CONTROL
pin connected to the IN pin
and gives a limitation of 1.25V dropout. Alternatively, the
V
CONTROL
pin is separately tied to a higher voltage and the
IN pin to a lower voltage giving 310mV dropout on the IN
pin, minimizing total power dissipation. This allows for a
3A supply regulating from 2.5V
1.2V
with low power dissipation.
OUT
to 1.8V
IN
or 1.8VIN to
OUT
Programming Output Voltage
The LT3083 sources a 50μA reference current that flows
out of the SET pin. Connecting a resistor from SET to
ground generates a voltage that becomes the reference
point for the error amplifier (see Figure 1). The reference voltage equals 50µA multiplied by the value of
the SET pin resistor. Any voltage can be generated and
there is no minimum output voltage for the regulator.
SET
R
LT3083
50µA
SET
+
–
OUT
V
OUT
C
C
SET
OUT
3083 F01
IN
V
CONTROL
+
+
V
OUT
V
V
CONTROL
IN
= 50µA • R
Figure 1. Basic Adjustable Regulator
SET
10
3083fa
APPLICATIONS INFORMATION
Table 1 lists many common output voltages and the closest standard 1% resistor values used to generate that
output voltage.
Regulation of the output voltage requires a minimum
load current of 1mA. For a true zero voltage output
operation, return this 1mA load current to a negative
supply voltage.
Table 1. 1% Resistors for Common Output Voltages
V
(V) R
OUT
1 20
1.2 24.3
1.5 30.1
1.8 35.7
2.5 49.9
3.3 66.5
5 100
SET
(k)
LT3083
OUT
GND
Figure 2. Guard Ring Layout Example
for DF Package
to remedy this is to bypass the SET pin with a small
amount of capacitance from SET to ground, 10pF to
20pF is sufficient.
SET PIN
3083 F02
With the lower level current used to generate the reference voltage, leakage paths to or from the SET pin can
create errors in the reference and output voltages. High
quality insulation should be used (e.g., Teflon, Kel-F);
cleaning of all insulating surfaces to remove fluxes and
other residues will probably be required. Surface coating
may be necessary to provide a moisture barrier in high
humidity environments.
Minimize board leakage by encircling the SET pin and
circuitry with a guard ring operated at a potential close
to itself. Tie the guard ring to the OUT pin. Guard rings
on both sides of the circuit board are required. Bulk leakage reduction depends on the guard ring width. 50nA
of leakage into or out of the SET pin and its associated
circuitry creates a 0.1% reference voltage error. Leakages
of this magnitude, coupled with other sources of leakage,
can cause significant offset voltage and reference drift,
especially over the possible operating temperature range.
Figure 2 depicts an example of a guard ring layout.
If guard ring techniques are used, this bootstraps any
stray capacitance at the SET pin. Since the SET pin is
a high impedance node, unwanted signals may couple
into the SET pin and cause erratic behavior. This will
be most noticeable when operating with minimum
output capacitors at full load current. The easiest way
Stability and Input Capacitance
Typical minimum input capacitance is 10µF for IN and
2.2µF for V
CONTROL
. These amounts of capacitance work
well using low ESR ceramic capacitors when placed close
to the LT3083 and the circuit is located in close proximity
to the power source. Higher values of input capacitance
may be necessary to maintain stability depending on the
application.
Oscillating regulator circuits are often viewed as a problem
of phase margin and inadequate stability with the output
capacitor used. More and more frequently, the problem
is not the regulator operating without sufficient output
capacitance, but instead with too little input capacitance.
The entire circuit must be analyzed and debugged as a
whole; conditions relating to the input of the regulator
cannot be ignored.
The LT3083 input presents a high impedance to its power
source: the output voltage and load current are independent
of input voltage variations. To maintain stability of the
regulator circuit as a whole, the LT3083 must be powered
from a low impedance supply. When using short supply
lines or powering directly from a large switching supply,
there is no issue—hundreds or thousands of microfarads
of capacitance are available through a low impedance.
3083fa
11
LT3083
APPLICATIONS INFORMATION
When longer supply lines, filters, current sense resistors,
or other impedances exist between the supply and the
input to the LT3083, input bypassing should be reviewed
if stability concerns are seen. Just as output capacitance
supplies the instantaneous changes in load current for
output transients until the regulator is able to respond,
input capacitance supplies local power to the regulator until
the main supply responds. When impedance separates the
LT3083 from its main supply, the local input can droop
so that the output follows. The entire circuit may break
into oscillations, usually characterized by larger amplitude
oscillations on the input and coupling to the output.
Low ESR, ceramic input bypass capacitors are acceptable
for applications without long input leads. However, applications connecting a power supply to an LT3083 circuit’s IN
and GND pins with long input wires combined with low
ESR, ceramic input capacitors are prone to voltage spikes,
reliability concerns and application-specific board oscillations. The input wire inductance found in many battery
powered applications, combined with the low ESR ceramic
input capacitor, forms a high-Q LC resonant tank circuit. In
some instances this resonant frequency beats against the
output current dependent LDO bandwidth and interferes
with proper operation. Simple circuit modifications/solutions are then required. This behavior is not indicative of
LT3083 instability, but is a common ceramic input bypass
capacitor application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the selfinductance of a 2-AWG isolated wire (diameter = 0.26") is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01"). One foot of 30-AWG wire has about 465nH of
self-inductance.
One of two ways reduces a wire’s self-inductance. One
method divides the current flowing towards the LT3083
between two parallel conductors. In this case, the farther
apart the wires are from each other, the more the self-inductance is reduced; up to a 50% reduction when placed
a few inches apart. Splitting the wires basically connects
two equal inductors in parallel, but placing them in close
proximity gives the wires mutual inductance adding to
the self-inductance. The second and most effective way
to reduce overall inductance is to place both forward and
return current conductors (the input and GND wires) in
very close proximity. Two 30-AWG wires separated by only
0.02", used as forward- and return- current conductors,
reduce the overall self-inductance to approximately onefifth that of a single isolated wire.
If wiring modifications are not permissible for the applications, including series resistance between the power supply
and the input of the LT3083 also stabilizes the application.
As little as 0.1Ω to 0.5Ω, often less, is effective in damping
the LC resonance. If the added impedance between the
power supply and the input is unacceptable, adding ESR to
the input capacitor also provides the necessary damping of
the LC resonance. However, the required ESR is generally
higher than the series impedance required.
Stability and Output Capacitance
The LT3083 requires an output capacitor for stability. It
is designed to be stable with most low ESR capacitors
(typically ceramic, tantalum or low ESR electrolytic). A
minimum output capacitor of 10μF with an ESR of 0.5Ω
or less is recommended to prevent oscillations. Larger
values of output capacitance decrease peak deviations
and provide improved transient response for larger load
current changes. Bypass capacitors, used to decouple
individual components powered by the LT3083, increase
the effective output capacitor value. For improvement in
transient performance, place a capacitor across the voltage setting resistor. Capacitors up to 1μF can be used.
This bypass capacitor reduces system noise as well, but
start-up time is proportional to the time constant of the
voltage setting resistor (R
bypass capacitor.
Give extra consideration to the use of ceramic capacitors.
Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature
and applied voltage. The most common dielectrics used
are specified with EIA temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
good for providing high capacitances in a small package,
but they tend to have strong voltage and temperature
coefficients as shown in Figures 3 and 4. When used with
a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an
in Figure 1) and SET pin
SET
3083fa
12
APPLICATIONS INFORMATION
LT3083
20
0
–20
–40
–60
CHANGE IN VALUE (%)
–80
–100
0
2 6
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
X5R
Y5V
4
8
DC BIAS VOLTAGE (V)
10
14
12
16
3083 F03
Figure 3. Ceramic Capacitor DC Bias Characteristics
40
20
0
–20
–40
–60
CHANGE IN VALUE (%)
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
–100
–50
–25 0
25 75
TEMPERATURE (°C)
X5R
Y5V
50 100 125
3083 F04
Figure 4. Ceramic Capacitor Temperature Characteristics
V
CONTROL
V
IN
LT3083
+
V
4.8V
TO 20V
10µF
–
SET
IN
V
CONTROL
V
IN
LT3083
+
–
SET
33k
OUT
OUT
10mΩ
10mΩ
3083 F05
Figure 5. Parallel Devices
V
3.3V
6A
10µF
OUT
effective value as low as 1μF to 2μF for the DC bias voltage
applied and over the operating temperature range. The X5R
and X7R dielectrics result in more stable characteristics
and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
while the X5R is less expensive and is available in higher
values. Care still must be exercised when using X5R and
X7R capacitors. The X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
Z5U capacitors, but can still be significant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress. In a
ceramic capacitor, the stress can be induced by vibrations
in the system or thermal transients.
Paralleling Devices
Higher output current is obtained by paralleling multiple
LT3083s together. Tie the individual SET pins together and
tie the individual IN pins together. Connect the outputs in
common using small pieces of PC trace as ballast resistors
to promote equal current sharing. PC trace resistance in
mΩ/inch is shown in Table 2. Ballasting requires only a
tiny area on the PCB.
Table 2. PC Board Trace Resistance
WEIGHT (oz) 10mil WIDTH 20mil WIDTH
1 54.3 27.1
2 27.1 13.6
Trace resistance is measured in mΩ/in
The worst-case room temperature offset, only ±4mV
(DD-PAK, T Packages) between the SET pin and the OUT
pin, allows the use of very small ballast resistors.
As shown in Figure 5, each LT3083 has a small 10mΩ
ballast resistor, which at full output current gives better
than 80% equalized sharing of the current. The external
3083fa
13
LT3083
APPLICATIONS INFORMATION
resistance of 10mΩ (5mΩ for the two devices in parallel) only adds about 30mV of output regulation drop at
an output of 6A. With an output voltage of 3.3V, this only
adds 1% to the regulation. Of course, paralleling more
than two LT3083s yields even higher output current.
Spreading the devices on the PC board also spreads the
heat. Series input resistors can further spread the heat if
the input-to-output difference is high.
Quieting the Noise
The LT3083 offers numerous noise performance advantages. Every linear regulator has its sources of noise. In
general, a linear regulator’s critical noise source is the
reference. In addition, consider the error amplifier’s noise
contribution along with the resistor divider’s noise gain.
Many traditional low noise regulators bond out the voltage
reference to an external pin (usually through a large value
resistor) to allow for bypassing and noise reduction. The
LT3083 does not use a traditional voltage reference like
other linear regulators. Instead, it uses a 50µA reference
current. The 50µA current source generates noise current
levels of 3.16pA/√Hz (1nA
) over the 10Hz to 100kHz
RMS
bandwidth). The equivalent voltage noise equals the RMS
noise current multiplied by the resistor value.
The SET pin resistor generates spot noise equal to √4kTR
–23
(k = Boltzmann’s constant, 1.38 • 10
J/°K, and T is absolute temperature) which is RMS summed with the voltage
noise. If the application requires lower noise performance,
bypass the voltage setting resistor with a capacitor to GND.
Note that this noise-reduction capacitor increases start-up
time as a factor of the RC time constant.
The LT3083 uses a unity-gain follower from the SET pin
to the OUT pin. Therefore, multiple possibilities exist
(besides a SET pin resistor) to set output voltage. For
example, using a high accuracy voltage reference from
SET to GND removes the errors in output voltage due to
reference current tolerance and resistor tolerance. Active
driving of the SET pin is acceptable.
The typical noise scenario for a linear regulator is that the
output voltage setting resistor divider gains up the noise
reference, especially if V
is much greater than V
OUT
REF
.
The LT3083’s noise advantage is that the unity gain follower
presents no noise gain whatsoever from the SET pin to the
output. Thus, noise figures do not increase accordingly.
Error amplifier noise is typically 126.5nV/√Hz (40µV
RMS
)
over the 10Hz to 100kHz bandwidth). The error amplifier’s
noise is RMS summed with the other noise terms to give
a final noise figure for the regulator.
Curves in the Typical Performance Characteristics section show noise spectral density and peak-to-peak noise
characteristics for both the reference current and error
amplifier over the 10Hz to 100kHz bandwidth.
Load Regulation
The LT3083 is a floating device. No ground pin exists on
the packages. Thus, the IC delivers all quiescent current
and drive current to the load. Therefore, it is not possible
to provide true remote load sensing. The connection resistance between the regulator and the load determines load
regulation performance. The data sheet’s load regulation
specification is Kelvin sensed at the package’s pins. Negative-side sensing is a true Kelvin connection by returning
the bottom of the voltage setting resistor to the negative
side of the load (see Figure 6).
Connected as shown, system load regulation is the sum
of the LT3083’s load regulation and the parasitic line
resistance multiplied by the output current. To minimize
load regulation, keep the positive connection between the
regulator and load as short as possible. If possible, use
large diameter wire or wide PC board traces.
SET
LT3083
+
–
R
SET
PARASITIC
RESISTANCE
OUT
R
P
LOAD
R
P
R
P
3080 F06
IN
V
CONTROL
Figure 6. Connections for Best Load Regulation
14
3083fa
APPLICATIONS INFORMATION
LT3083
Thermal Considerations
The LT3083’s internal power and thermal limiting circuitry
protects itself under overload conditions. For continuous
normal load conditions, do not exceed the 125°C maximum
junction temperature. Carefully consider all sources of
thermal resistance from junction-to-ambient. This includes
(but is not limited to) junction-to-case, case-to-heat sink
interface, heat sink resistance or circuit board-to-ambient
as the application dictates. Consider all additional, adjacent
heat generating sources in proximity on the PCB.
Surface mount packages provide the necessary heat
sinking by using the heat spreading capabilities of the
PC board, copper traces, and planes. Surface mount heat
sinks, plated through-holes and solder-filled vias can also
spread the heat generated by power devices.
Junction-to-case thermal resistance is specified from the
IC junction to the bottom of the case directly, or the bottom
of the pin most directly in the heat path. This is the lowest
thermal resistance path for heat flow. Only proper device
mounting ensures the best possible thermal flow from this
area of the packages to the heat sinking material.
Note that the exposed pad of the DFN and TSSOP packages and the tab of the DD-PAK and TO-220 packages
are electrically connected to the output (V
OUT
).
Tables 3 through 5 list thermal resistance as a function
of copper areas on a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes and 2oz external trace planes with a
total finished board thickness of 1.6mm. Layers are not
connected electrically or thermally.
Table 3. DF Package, 12-Lead DFN
COPPER AREA
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
1000mm
225mm
100mm
*Device is mounted on topside.
2
2
2
2
BOARD AREA
2500mm
2500mm
2500mm
2500mm
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE
2
2
2
2
18°C/W
22°C/W
29°C/W
35°C/W
Table 4. FE Package, 16-Lead TSSOP
COPPER AREA
BOARD AREA
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
1000mm
225mm
100mm
*Device is mounted on topside.
2
2
2
2
2500mm
2500mm
2500mm
2500mm
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE
2
2
2
2
16°C/W
20°C/W
26°C/W
32°C/W
Table 5. Q Package, 5-Lead DD-PAK
COPPER AREA
BOARD AREA
125mm
2
2
2
2500mm
1000mm
*Device is mounted on topside.
2500mm
2500mm
2500mm
2
2
2
2500mm
2500mm
2500mm
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)TOPSIDE* BACKSIDE
2
2
2
13°C/W
14°C/W
16°C/W
T Package, 5-Lead TO-220
Thermal Resistance (Junction-to-Case) = 3°C/W
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
PCB layers, copper weight, board layout and thermal vias
affect the resultant thermal resistance. Tables 3 through 5
provide thermal resistance numbers for best-case 4-layer
boards with 1oz internal and 2oz external copper. Modern,
multilayer PCBs may not be able to achieve quite the same
level performance as found in these tables.
Calculating Junction Temperature
Example: Given an output voltage of 0.9V, a V
CONTROL
voltage of 3.3V ±10%, an IN voltage of 1.5V ±5%, output
current range from 10mA to 3A and a maximum ambient
temperature of 50°C, what will the maximum junction
2
temperature be for the DD-PAK on a 2500mm
2
topside copper of 1000mm
?
board with
3083fa
15
LT3083
I
3A
−
2A
APPLICATIONS INFORMATION
The power in the drive circuit equals:
P
where I
of output current. A curve of I
DRIVE
CONTROL
= (V
CONTROL
– V
is equal to I
)(I
OUT
/60. I
OUT
CONTROL
CONTROL
CONTROL
vs I
)
is a function
can be found
OUT
in the Typical Performance Characteristics curves.
The total power equals:
P
TOTAL
= P
DRIVE
+ P
OUTPUT
The current delivered to the SET pin is negligible and can
be ignored.
V
CONTROL(MAX_CONTINUOUS)
V
IN(MAX_CONTINUOUS)
V
OUT
= 0.9V, I
= 3A, TA = 50°C
OUT
= 3.630V (3.3V + 10%)
= 1.575V (1.5V + 5%)
Power dissipation under these conditions is equal to:
P
P
P
= (V
DRIVE
I
CONTROL
DRIVE
OUTPUT
CONTROL
OUT
=
60
= (3.630V – 0.9V)(50mA) = 137mW
= (VIN – V
=
– V
60
OUT
)(I
OUT
= 50mA
)(I
OUT
CONTROL
)
)
As an example, assume: V
and I
OUT(MAX)
Junction Temperature
Without series resistor R
= 2A. Use the formulas from the
section previously discussed.
, power dissipation in the LT3083
S
IN
= V
CONTROL
= 5V, V
= 3.3V
OUT
Calculating
equals:
P
TOTAL
= 5V − 3.3V
( )
= 3.46W
If the voltage differential (V
2A
•
+ 5V − 3.3V
( )
60
) across the NPN pass
DIFF
• 2A
transistor is chosen as 0.5V, then RS equals:
5V
RS=
3.3V−0.5V
= 0.6Ω
Power dissipation in the LT3083 now equals:
P
TOTAL
= 5V − 3.3V
( )
2A
•
+ 0.5V • 2A = 1.06W
60
The LT3083’s power dissipation is now only 30% compared
to no series resistor. R
dissipates 2.4W of power. Choose
S
appropriate wattage resistors or use multiple resistors in
parallel to handle and dissipate the power properly.
P
OUTPUT
= (1.575V – 0.9V)(3A) = 2.03W
Total Power Dissipation = 2.16W
Junction Temperature will be equal to:
TJ = TA + P
• θJA (using tables)
TOTAL
TJ = 50°C + 2.16W • 16°C/W = 84.6°C
In this case, the junction temperature is below the maxi-
mum rating, ensuring reliable operation.
Reducing Power Dissipation
In some applications it may be necessary to reduce the
power dissipation in the LT3083 package without sacrificing output current capability. Two techniques are available.
The first technique, illustrated in Figure 7, employs a
resistor in series with the regulator’s input. The voltage
drop across RS decreases the LT3083’s input-to-output
differential voltage and correspondingly decreases the
LT3083’s power dissipation.
V
V
C1
Figure 7. Reducing Power Dissipation Using a Series Resistor
CONTROL
SET
R
SET
LT3083
+
–
IN
OUT
3083 F07
IN
R
S
VIN′
V
OUT
C2
3083fa
16
5.5V − 3.2V
−
Ω
APPLICATIONS INFORMATION
LT3083
The second technique for reducing power dissipation,
shown in Figure 8, uses a resistor in parallel with the
LT3083. This resistor provides a parallel path for current
flow, reducing the current flowing through the LT3083.
This technique works well if input voltage is reasonably
constant and output load current changes are small. This
technique also increases the maximum available output
current at the expense of minimum load requirements.
V
V
C1
Figure 8. Reducing Power Dissipation Using a Parallel Resistor
CONTROL
LT3083
+
–
SET
R
SET
IN
OUT
3083 F08
IN
R
P
V
OUT
C2
As an example, assume: V
5.5V, V
I
OUT(MIN)
than 90% of I
Calculating R
RP=
= 3.3V, V
OUT
OUT(MIN)
= 0.7A. Also, assuming that RP carries no more
OUT(MIN)
yields:
P
= 630mA.
= 3.65Ω
= V
IN
= 3.2V, I
CONTROL
= 5V, V
OUT(MAX)
IN(MAX)
=
= 2A and
0.63A
(5% Standard Value = 3.6Ω)
The maximum total power dissipation is (5.5V – 3.2V) •
2A = 4.6W. However, the LT3083 supplies only:
5.5V
2A −
3.6
3.2V
= 1.36A
Therefore, the LT3083’s power dissipation is only:
P
R
P
= (5.5V – 3.2V) • 1.36A = 3.13W
DISS
dissipates 1.47W of power. As with the first technique,
choose appropriate wattage resistors to handle and dissipate the power properly. With this configuration, the
LT3083 supplies only 1.36A. Therefore, load current can
increase by 1.64A to a total output current of 3.64A while
keeping the LT3083 in its normal operating range.
3083fa
17
LT3083
TYPICAL APPLICATIONS
Adding Shutdown Current Source
ON OFF
V
IN
V
CONTROL
SHUTDOWN
IN
Q1
VN2222LL
LT3083
+
–
SET
R1
*
Q2 INSURES ZERO OUTPUT
IN THE ABSENCE OF ANY
OUTPUT LOAD.
C1
V
IN
10V
OUT
V
OUT
Q2*
VN2222LL
3083 TA02
Low Dropout Voltage LED Driver
V
CONTROL
LT3083
D1
IN
+
–
OUT
V
CONTROL
10µF
1A
IN
LT3083
+
–
SET
20k
V
IN
OUT
0.33Ω
I
OUT
0A TO 3A
10µF
3083 TA03
SPI
LTC2641
150k
150k
SET
R1
20k
DAC-Controlled Regulator
V
CONTROL
IN
V
IN
450k
–
+
LT1991
GAIN = 4
SET
LT3083
+
–
R2
1Ω
3083 TA04
OUT
10µF
3083 TA05
V
OUT
3083fa
18
TYPICAL APPLICATIONS
LT3083
Coincident Tracking
V
7V TO 20V
SET
34k
LT3083
+
–
C3
10µF
V
OUT2
3.3V
OUT
V
OUT3
5V
10µF
3083 TA06
IN
V
CONTROL
SET
R2
16.2k
LT3083
+
–
C2
10µF
V
OUT1
2.5V
OUT
IN
V
CONTROL
LT3083
V
CONTROL
IN
IN
+
SET
R1
49.9k
–
OUT
C1
10µF
Adding Soft-Start
V
4.8V to 20V
V
CONTROL
IN
IN
LT3083
V
12V TO 18V
SET
R1
66.5k
+
–
OUT
3083 TA07
V
OUT
3.3V
3A
C
OUT
10µF
D1
1N4148
C1
10µF
C2
0.01µF
Lab Supply
SETSET
R4
200k
LT3083
+
–
OUTOUT
10µF 100µF
+
V
0V TO 10V
3083 TA08
OUT
IN
V
CONTROL
+
15µF
LT3083
+
–
0.33Ω
+
20k
0A TO 3A
V
CONTROL
15µF
ININ
3083fa
19
LT3083
TYPICAL APPLICATIONS
High Voltage Regulator
SET
R
402k
6.1V
LT3083
+
–
SET
OUT
10µF
3083 TA09
V
OUT
3A
V
V
OUT
OUT
= 20V
= 50µA • R
SET
V
50V
10k
IN
1N4148
IN
BUZ11
V
CONTROL
+
10µF
+
15µF
Ramp Generator Reference Buffer
SET
LT3083
+
–
10nF
OUT
V
OUT
10µF
3083 TA10
V
IN
LT1019
V
IN
5V
10µF
IN
V
CONTROL
VN2222LL VN2222LL
V
CONTROL
INPUT
GND
IN
OUTPUT
SET
LT3083
+
–
C1
1µF
OUT
*MIN LOAD 0.5mA
C2
10µF
3083 TA11
V
OUT
*
20
Boosting Fixed Output Regulators
IN
V
CONTROL
5V
10µF
*4mV DROP ENSURES LT3083 IS
OFF WITH NO LOAD
MULTIPLE LT3083’S CAN BE USED
LT1963-3.3
LT3083
+
–
SET
20mΩ
42Ω* 47µF
33k
OUT
10mΩ
3.3V
4.5A
3083 TA12
OUT
3083fa
TYPICAL APPLICATIONS
Low Voltage, High Current Adjustable High Efficiency Regulator*
LT3083
2.7V TO 5.5V
†
100µF
PV
IN
SV
+
2×
2.2MEG 100k
1000pF
IN
LTC3610
PGOOD
RUN/SS
SYNC/MODE
SGND PGND
*DIFFERENTIAL VOLTAGE ON LT3083
IS 0.6V SET BY THE V
†
MAXIMUM OUTPUT VOLTAGE IS 1.5V
BELOW INPUT VOLTAGE
0.47µH
SW
I
TH
12.1k
R
T
294k
V
FB
78.7k
124k
OF THE 2N3906 PNP.
BE
470pF
+
2×
100µF
2N3906
10k
V
CONTROL
V
CONTROL
V
CONTROL
IN
LT3083
+
–
SET
IN
LT3083
OUT
10mΩ
+
–
SET
IN
LT3083
OUT
10mΩ
0V TO 4V
12A
†
+
–
SET
OUT
10mΩ
V
CONTROL
IN
LT3083
+
–
SET
100k
3083 TA13
OUT
10mΩ
+
100µF
3083fa
21
LT3083
TYPICAL APPLICATIONS
Adjustable High Efficiency Regulator*
4.5V TO 25V
†
10µF
1µF
15.4k
680pF
*DIFFERENTIAL VOLTAGE ON LT3083
≈ 1.4V SET BY THE TPO610L P-CHANNEL THRESHOLD.
†
MAXIMUM OUTPUT VOLTAGE IS 2V
BELOW INPUT VOLTAGE
100k
0.1µF
63.4k
600kHz
V
IN
BD
RUN/SS
V
CONTROL
RT
LT3680
GND
BOOST
SW
0.47µF
4.7µH
B340A
FB
10k
68µF
TP0610L
200k
V
CONTROL
IN
10k
SET
200k
LT3083
+
–
3083 TA14
OUT
4.7µF
0V TO 10V
3A
†
2 Terminal Current Source
C
*
COMP
IN
V
CONTROL
*C
COMP
R1 ≤ 10Ω 10µF
R1 ≥ 10Ω 2.2µF
SET
LT3083
+
–
20k
R1
3083 TA15
I
OUT
1V
=
R1
3083fa
22
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev H)
Exposed Pad Variation BB
3.58
(.141)
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev H)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
LT3083
3.58
(.141)
10 9
6.60 ±0.10
4.50 ±0.10
RECOMMENDED SOLDER PAD LAYOUT
0.09 – 0.20
(.0035 – .0079)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
0.45 ±0.05
0.65 BSC
4.30 – 4.50*
(.169 – .177)
0.50 – 0.75
(.020 – .030)
MILLIMETERS
(INCHES)
2.94
(.116)
1.05 ±0.10
1 3 45678
2
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
2.94
(.116)
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
FE16 (BB) TSSOP REV G 0910
6.40
(.252)
BSC
3083fa
23
LT3083
PACKAGE DESCRIPTION
2.50 REF
DF Package
12-Lead Plastic DFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1733 Rev Ø)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
3.38 ±0.05
2.65 ± 0.05
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.75 ± 0.05
PACKAGE OUTLINE
R = 0.115
2.50 REF
3.38 ±0.10
2.65 ± 0.10
16
TYP
BOTTOM VIEW—EXPOSED PAD
127
0.25 ± 0.05
0.50 BSC
0.40 ± 0.10
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45°
CHAMFER
(DF12) DFN 0806 REV Ø
24
NOTE:
0.00 – 0.05
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3083fa
PACKAGE DESCRIPTION
Q Package
5-Lead Plastic DD Pak
(Reference LTC DWG # 05-08-1461 Rev E)
LT3083
Q Package
5-Lead Plastic DD-PAK
(Reference LTC DWG # 05-08-1461 Rev E)
.256
(6.502)
.060
(1.524)
.300
(7.620)
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
.060
(1.524)
.060
(1.524)
.183
(4.648)
.075
(1.905)
TYP
.330 – .370
(8.382 – 9.398)
+.012
.143
.420
–.020
+0.305
3.632
( )
–0.508
.350
.585
(9.906 – 10.541)
.028 – .038
(0.711 – 0.965)
TYP
.080
.390 – .415
15° TYP
.067
(1.702)
BSC
.205
.165 – .180
(4.191 – 4.572)
.420
.276
.059
(1.499)
TYP
.013 – .023
(0.330 – 0.584)
.325
.585
.045 – .055
(1.143 – 1.397)
+.008
.004
–.004
+0.203
0.102
( )
–0.102
.095 – .115
(2.413 – 2.921)
.050 ± .012
(1.270 ± 0.305)
.067
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER)
2. DRAWING NOT TO SCALE
.042
.090
.320
.090
.067
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
.042
Q(DD5) 0610 REV E
3083fa
25
LT3083
PACKAGE DESCRIPTION
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
.390 – .415
(9.906 – 10.541)
.460 – .500
(11.684 – 12.700)
.067
BSC
(1.70)
(3.734 – 3.937)
.230 – .270
(5.842 – 6.858)
.330 – .370
(8.382 – 9.398)
.028 – .038
(0.711 – 0.965)
.147 – .155
DIA
.570 – .620
(14.478 – 15.748)
.260 – .320
(6.60 – 8.13)
(17.78 – 18.491)
SEATING PLANE
.152 – .202
(3.861 – 5.131)
.165 – .180
(4.191 – 4.572)
.700 – .728
.135 – .165
(3.429 – 4.191)
.620
(15.75)
TYP
.045 – .055
(1.143 – 1.397)
.095 – .115
(2.413 – 2.921)
.155 – .195*
(3.937 – 4.953)
.013 – .023
(0.330 – 0.584)
* MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801
26
3083fa
LT3083
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 4/11 Revised part markings in Order Information section 3
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
3083fa
27
LT3083
TYPICAL APPLICATION
Paralleling Regulators
IN
V
CONTROL
V
CONTROL
IN
V
4.8V TO 28V
IN
10µF
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1185 3A Negative Low Dropout Regulator V
LT1764/
LT1764A
3A, Fast Transient Response,
Low Noise LDO
LT1963/A 1.5A Low Noise, Fast Transient
Response LDO
LT1965 1.1A, Low Noise, Low Dropout
Linear Regulator
LT3022 1A, Low Voltage, VLDO Linear
Regulator
LT3070 5A, Low Noise, Programmable V
85mV Dropout Linear Regulator with
OUT
Digital Margining
LT3071 5A, Low Noise, Programmable Vout,
85mV Dropout Linear Regulator with
Analog Margining
LT3080/
LT3080-1
1.1A, Parallelable, Low Noise, Low
Dropout Linear Regulator
LT3082 200mA, Parallelable, Single Resistor,
Low Dropout Linear Regulator
LT3085 500mA, Parallelable, Low Noise,
Low Dropout Linear Regulator
LTC3026 1.5A, Low Input Voltage VLDO
Linear Regulator
Linear Technology Corporation
28
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
: –4.5V to –35V, 0.8V Dropout Voltage, DD-PAK and TO-220 Packages
IN
340mV Dropout Voltage, Low Noise: 40µV
“A” Version Stable Also with Ceramic Capacitors
340mV Dropout Voltage, Low Noise: 40µV
Ceramic Capacitors, TO-220, DD, SOT-223 and SO-8 Packages
290mV Dropout Voltage, Low Noise: 40µV
Stable with Ceramic Capacitors, TO-220, DD-PAK, MSOP and 3mm × 3mm DFN Packages
: 0.9V to 10V, Dropout Voltage: 145mV Typical, Adjustable Output (V
V
IN
Stable with Low ESR, Ceramic Output Capacitors, 16-Pin DFN (5mm × 3mm) and
16-Lead MSOP Packages
,
Dropout Voltage: 85mV, Digitally Programmable V
±1%, ±3% or ±5%, Low Output Noise: 25μV
10A Output, Stable with Low ESR Ceramic Output Capacitors (15μF Minimum),
28-Lead 4mm × 5mm QFN Package
Dropout Voltage: 85mV, Digitally Programmable V
Low Output Noise: 25μV
Output Current Monitor, Stable with Low ESR Ceramic Output Capacitors (15μF Minimum),
28-Lead 4mm × 5mm QFN Package
300mV Dropout Voltage (2-Supply Operation), Low Noise: 40µV
to 35.7V, Current-Based Reference with 1-Resistor V
Required), Stable with Ceramic Capacitors, TO-220, DD-PAK, SOT-223, MS8E and 3mm × 3mm
DFN-8 Packages; “-1” Version Has Integrated Internal Ballast Resistor
Outputs May Be Paralleled for Higher Output, Current or Heat Spreading, Wide Input Voltage
Range: 1.2V to 40V, Low Value Input/Output Capacitors Required: 0.22μF, Single Resistor Sets
Output Voltage, 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages
275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µV
to 35.7V, Current-Based Reference with 1-Resistor V
Required), Stable with Ceramic Capacitors, MS8E and 2mm × 3mm DFN-6 Packages
: 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External 5V), VDO = 0.1V, IQ = 950µA,
V
IN
Stable with 10µF Ceramic Capacitors, 10-Lead MSOP-E and DFN-10 Packages
www.linear.com
SET
SET
33.2k
LT3083
+
–
LT3083
+
–
10mΩ
OUT
10mΩ
OUT
RMS
RMS
RMS
(10Hz to 100kHz), Parallelable: Use Two for a 10A Output, I
RMS
V
OUT
3.3V
6A
22µF
3083 TA16
, VIN = 2.7V to 20V, TO-220 and DD Packages.
, VIN = 2.5V to 20V, “A” Version Stable with
, VIN: 1.8V to 20V, V
: 0.8V to 1.8V, Digital Output Margining:
OUT
(10Hz to 100kHz), Parallelable: Use Two for a
RMS
: 0.8V to 1.8V, Analog Margining: ±10%,
OUT
Set; Directly Parallelable (No Op Amp
OUT
Set; Directly Parallelable (No Op Amp
OUT
: 1.2V to 19.5V,
OUT
= V
REF
OUT(MIN)
, VIN: 1.2V to 36V, V
RMS
, VIN: 1.2V to 36V, V
RMS
LT 0411 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2011
= 200mV),
MON
: 0V
OUT
: 0V
OUT
3083fa
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