ANALOG DEVICES LT 1720 IS8 Datasheet

LT1720/LT1721

Dual/Quad, 4.5ns, Single

Supply 3V/5V Comparators

with Rail-to-Rail Outputs

FEATURES

n

UltraFast: 4.5ns at 20mV Overdrive

7ns at 5mV Overdrive

n

Low Power: 4mA per Comparator

n

Optimized for 3V and 5V Operation

n

Pinout Optimized for High Speed Ease of Use

n

Input Voltage Range Extends 100mV

Below Negative Rail

n

TTL/CMOS Compatible Rail-to-Rail Outputs

n

Internal Hysteresis with Specifi ed Limits

n

Low Dynamic Current Drain; 15μA/(V-MHz),

Dominated by Load In Most Circuits

n

Tiny 3mm × 3mm × 0.75mm DFN Package (LT1720)

APPLICATIONS

n

High Speed Differential Line Receiver

n

Crystal Oscillator Circuits

n

Window Comparators

n

Threshold Detectors/Discriminators

n

Pulse Stretchers

n

Zero-Crossing Detectors

n

High Speed Sampling Circuits

DESCRIPTION

The LT®1720/LT1721 are UltraFastTM dual/quad compara­tors optimized for single supply operation, with a supply
voltage range of 2.7V to 6V. The input voltage range extends
from 100mV below ground to 1.2V below the supply volt­age. Internal hysteresis makes the LT1720/LT1721 easy to
use even with slow moving input signals. The rail-to-rail
outputs directly interface to TTL and CMOS. Alternatively,
the symmetric output drive can be harnessed for analog
applications or for easy translation to other single supply
logic levels.

The LT1720 is available in three 8-pin packages; three pins
per comparator plus power and ground. In addition to SO
and MSOP packages, a 3mm × 3mm low profi le (0.8mm)
dual fi ne pitch leadless package (DFN) is available for space
limited applications. The LT1721 is available in the 16-pin
SSOP and S packages.

The pinouts of the LT1720/LT1721 minimize parasitic
effects by placing the most sensitive inputs (inverting)
away from the outputs, shielded by the power rails. The
LT1720/LT1721 are ideal for systems where small size and
low power are paramount.

TYPICAL APPLICATION

2.7V to 6V Crystal Oscillator with TTL/CMOS Output

2.7V TO 6V

2k

620Ω

1MHz TO 10MHz

CRYSTAL (AT-CUT)

220Ω

+

C1

1/2 LT1720

–

0.1μF 1.8k

GROUND

CASE

2k

17201 TA01

OUTPUT

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. UltaFast is
a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.

Propagation Delay vs Overdrive

8

7

6

5

4

DELAY (ns)

3

2

1

0

0

RISING EDGE

)

(t

PDLH

10 20 40

OVERDRIVE (mV)

25°C

= 100mV

V

STEP

= 5V

V

CC

= 10pF

C

LOAD

FALLING EDGE

)

(t

PDHL

30

50

17201 TA02

17201fc

1

LT1720/LT1721

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, VCC to GND ........................................7V

Input Current ....................................................... ±10mA

Output Current (Continuous) ............................. ±20mA

Junction Temperature .......................................... 150°C

(DD Package) .................................................... 125°C

Lead Temperature (Soldering, 10 sec) ..................300°C

PIN CONFIGURATION

TOP VIEW

1+IN A

–IN A

2

–IN B

3

+IN B

4

8-LEAD (3mm s 3mm) PLASTIC DFN

T

JMAX

UNDERSIDE METAL INTERNALLY

9

DD PACKAGE

= 125°C, θJA = 160°C/W

CONNECTED TO GND

8

V

CC

OUT A

7

OUT B

6

GND

5

(Note 1)

Storage Temperature Range ...................–65°C to 150°C

(DD Package) ..................................... –65°C to 125°C

Operating Temperature Range

C Grade ................................................... 0°C to 70°C

I Grade ............................................... –40°C to 85°C

TOP VIEW

8

+IN A

1

–IN A

2

–IN B

3

+IN B

4

MS8 PACKAGE

8-LEAD PLASTIC MSOP

T

= 150°C, θJA = 230°C/W

JMAX

7
6
5

V

CC

OUT A
OUT B
GND

+IN A

1

–IN A

2

–IN B

3

+IN B

4

8-LEAD PLASTIC SO

T

= 150°C, θJA = 200°C/W

JMAX

TOP VIEW

S8 PACKAGE

TOP VIEW

–IN A

1

+IN A

2

GND

V

8

CC

OUT A

7

OUT B

6

GND

5

3

OUT A

4

OUT B

5

GND

6

+IN B

7

–IN B

8

GN PACKAGE

16-LEAD NARROW

PLASTIC SSOP

T

= 150°C, θJA = 135°C/W (GN)

JMAX

= 150°C, θJA = 115°C/W (S)

T

JMAX

16

–IN D

15

+IN D

14

V

CC

13

OUT D

12

OUT C

11

V

CC

10

+IN C

9

–IN C

S PACKAGE

16-LEAD PLASTIC SO

2

17201fc

LT1720/LT1721

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT1720CDD#PBF LT1720CDD#TRPBF LAAV
LT1720IDD#PBF LT1720IDD#TRPBF LAAV

8-Lead (3mm × 3mm) Plastic DFN

8-Lead (3mm × 3mm) Plastic DFN
LT1720CMS8#PBF LT1720CMS8#TRPBF LTDS 8-Lead Plastic MSOP 0°C to 70°C
LT1720IMS8#PBF LT1720IMS8#TRPBF LTACW 8-Lead Plastic MSOP –40°C to 85°C
LT1720CS8#PBF LT1720CS8#TRPBF 1720 8-Lead Plastic SO 0°C to 70°C
LT1720IS8#PBF LT1720IS8#TRPBF 1720I 8-Lead Plastic SO –40°C to 85°C
LT1721CGN#PBF LT1721CGN#TRPBF 1721 16-Lead Narrow Plastic SSOP 0°C to 70°C
LT1721IGN#PBF LT1721IGN#TRPBF 1721I 16-Lead Narrow Plastic SSOP –40°C to 85°C
LT1721CS#PBF LT1721CS#TRPBF 1721 16-Lead Plastic SO 0°C to 70°C
LT1721IS#PBF LT1721IS#TRPBF 1721I 16-Lead Plastic SO –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifi

cations, go to: http://www.linear.com/tapeandreel/

0°C to 70°C
–40°C to 85°C

ELECTRICAL CHARACTERISTICS

The l denotes specifi cations that apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. VCC = 5V, VCM = 1V, C

= 10pF, V

OUT

OVERDRIVE

= 20mV, unless otherwise specifi ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC

I

CC

V

CMR

+

V

TRIP

–

V

TRIP

V

OS

V

HYST

ΔVOS/ΔT
I

B

I

OS

Supply Voltage
Supply Current (Per Comparator) VCC = 5V

V

= 3V

CC

Common Mode Voltage Range (Note 2)
Input Trip Points (Note 3)

Input Trip Points (Note 3)

Input Offset Voltage (Note 3)

Input Hysteresis Voltage (Note 3)
Input Offset Voltage Drift
Input Bias Current

Input Offset Current
CMRR Common Mode Rejection Ratio (Note 4)
PSRR Power Supply Rejection Ratio (Note 5)
A

V

V

OH

V

OL

t

PD20

t

PD5

Voltage Gain (Note 6)

Output High Voltage I

Output Low Voltage I

Propagation Delay V

Propagation Delay V

SOURCE

= 10mA, VIN = V

SINK

OVERDRIVE

OVERDRIVE

= 4mA, VIN = V

TRIP

= 20mV (Note 7)

= 5mV (Notes 7, 8)

TRIP

–

+

+ 10mV

– 10mV

l

2.7 6 V

l
l

l

–0.1 VCC – 1.2 V
–2.0

l

–3.0
–5.5

l

–6.5

4

3.5

7
6

5.5

6.5

2.0

3.0

1.0 3.0

l

l

2.0 3.5 7.0 mV

l

l

–6 0 μA

l

l

55 70 dB

l

65 80 dB

10 μV/°C

4.5

0.6 μA

∞

l

VCC – 0.4 V

l

0.4 V

4.5 6.5

l

8.0

71013ns

l

mA
mA

mV
mV

mV
mV

mV
mV

ns
ns

ns

17201fc

3

LT1720/LT1721

ELECTRICAL CHARACTERISTICS

The l denotes specifi cations that apply over the full operating temperature
range, otherwise specifi cations are at T

= 25°C. VCC = 5V, VCM = 1V, C

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Δt

PD

t

SKEW

t

r

t

f

t

JITTER

Differential Propagation Delay (Note 9) Between Channels 0.3 1.0 ns

Propagation Delay Skew (Note 10) Between t

Output Rise Time 10% to 90% 2.5 ns

Output Fall Time 90% to 10% 2.2 ns

Output Timing Jitter VIN = 1.2V

P-P

VCM = 2V, f = 20MHz t

f

MAX

Maximum Toggle Frequency V

OVERDRIVE

V

OVERDRIVE

= 50mV, VCC = 3V
= 50mV, VCC = 5V

= 10pF, V

OUT

PDLH/tPDHL

OVERDRIVE

(6dBm), ZIN = 50Ω t

= 20mV, unless otherwise specifi ed.

0.5 1.5 ns

PDLH

PDHL

15
11

70.0

62.5

ps
ps

RMS
RMS

MHz
MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: If one input is within these common mode limits, the other input
can go outside the common mode limits and the output will be valid.

Note 3: The LT1720/LT1721 comparators include internal hysteresis.
The trip points are the input voltage needed to change the output state in
each direction. The offset voltage is defi ned as the average of V

–

V

, while the hysteresis voltage is the difference of these two.

TRIP

Note 4: The common mode rejection ratio is measured with V
and is defi ned as the change in offset voltage measured from V
to V

= 3.8V, divided by 3.9V.

CM

Note 5: The power supply rejection ratio is measured with V
is defi ned as the change in offset voltage measured from V
V

= 6V, divided by 3.3V.

CC

TRIP

= 5V

CC

CM

= 1V and

CM

= 2.7V to

CC

+

and

= –0.1V

Note 6: Because of internal hysteresis, there is no small-signal region
in which to measure gain. Proper operation of internal circuity is ensured
by measuring V

Note 7: Propagation delay measurements made with 100mV steps.
Overdrive is measured relative to V

Note 8: t

PD

low values of overdrive. The LT1720/LT1721 are 100% tested with a
100mV step and 20mV overdrive. Correlation tests have shown that
t

limits can be guaranteed with this test, if additional DC tests are

PD

performed to guarantee that all internal bias conditions are correct.
Note 9: Differential propagation delay is defi ned as the larger of the two:
Δt

PDLH

Δt

PDHL

where (MAX) and (MIN) denote the maximum and minimum values
of a given measurement across the different comparator channels.

Note 10: Propagation Delay Skew is defi ned as:
t

TYPICAL PERFORMANCE CHARACTERISTICS

Input Offset and Trip Voltages
vs Supply Voltage

3

2

1

0

–1

AND TRIP POINT VOLTAGE (mV)

–2

OS

V

25°C

= 1V

V

CM

–3

2.5

3.0 3.5

V

V

4.0 5.0

SUPPLY VOLTAGE (V)

+

TRIP

V

OS

–

TRIP

4.5 5.5 6.0

17201 G01

Input Offset and Trip Voltages
vs Temperature

3

+

V

2

1

0

–1

AND TRIP POINT VOLTAGE (mV)

–2

OS

V

–3

–25 25 100

–50 0 50 75 125

TRIP

V

OS

–

V

TRIP

TEMPERATURE (°C)

and VOL with only 10mV of overdrive.

OH

±

.

TRIP

cannot be measured in automatic handling equipment with

= t

PDLH(MAX)

= t

PDHL(MAX)

SKEW

= |t

PDLH

– t

PDLH(MIN)

– t

PDHL(MIN)

– t

PDHL

|

Input Common Mode Limits
vs Temperature

4.2
VCC = 5V

4.0

3.8

3.6

0.2

0

–0.2

COMMON MODE INPUT VOLTAGE (V)

17201 G02

–0.4

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

17201 G03

4

17201fc

TYPICAL PERFORMANCE CHARACTERISTICS

LT1720/LT1721

Input Current
vs Differential Input Voltage

2

25°C

1

= 5V

V

CC

0

–1

–2

–3

–4

INPUT CURRENT (μA)

–5

–6

–7

–4 –3 –2 –1 0 5

–5

DIFFERENTIAL INPUT VOLTAGE (V)

Propagation Delay
vs Load Capacitance

9

25°C

= 100mV

V

8

STEP

OVERDRIVE = 20mV

7

= 5V

V

CC

6

5

4

DELAY (ns)

3

2

1

0

10 20 40

0

OUTPUT LOAD CAPACITANCE (pF)

1234

17201 G04

RISING EDGE

)

(t

PDLH

FALLING EDGE

)

(t

PDHL

30

17201 G07

Quiescent Supply Current
vs Temperature

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0
–50

QUIESCENT SUPPLY CURRENT PER COMPARATOR (mA)

VCC = 5V

–25 0 50

25

TEMPERATURE (˚C)

Propagation Delay
vs Temperature

8.0

7.5

7.0

6.5

6.0

5.5

5.0

PROPAGATION DELAY (ns)

4.5

50

4.0
–50

VCC = 3V

VCC = 5V

VCC = 5V

VCC = 3V

–25 0 50

25

TEMPERATURE (°C)

OVERDRIVE = 5mV

OVERDRIVE = 20mV

= 3V

V

CC

75 100 125

t

PDLH

VCM = 1V

= 100mV

V

STEP

= 10pF

C

LOAD

75 100 125

17201 G05

17201 G08

Quiescent Supply Current
vs Supply Voltage

7

6

5

4

3

2

1

SUPPLY CURRENT PER COMPARATOR (mA)

0

0

1

3

2

SUPPLY VOLTAGE (V)

125°C

25°C

–55°C

4

5

Propagation Delay
vs Supply Voltage

5.0
25°C

= 100mV

V

STEP

OVERDRIVE = 20mV

= 10pF

C

LOAD

RISING EDGE

)

4.5

DELAY (ns)

4.0

2.5

3.0 3.5

(t

PDLH

FALLING EDGE

(t

PDHL

4.5 5.5 6.0

4.0 5.0

SUPPLY VOLTAGE (V)

)

6

17201 G06

17201 G09

7

Output Low Voltage
vs Load Current

0.5
VCC = 5V

= 1V

V

CM

= –15mV

V

IN

0.4

0.3

–55°C

OUTPUT VOLTAGE (V)

0.2

0.1

4

0

OUTPUT SINK CURRENT (mA)

V

CC

8

125°C

= 2.7V

Output High Voltage
vs Load Current Supply Current vs Frequency

0.0

(V)

125°C

125°C

25°C

12

16

20

17201 G10

CC

–0.2

–55°C

–0.4

–0.6

–0.8

OUTPUT VOLTAGE RELATIVE TO V

–1.0

0

25°C

4

8

OUTPUT SOURCE CURRENT (mA)

VCC = 5V

= 1V

V

CM

= 15mV

V

IN

25°C

= 2.7V

V

CC

12

16

20

17201 G11

10

25°C

= 5V

V

CC

9

8

7

6

5

4

SUPPLY CURRENT PER COMPARATOR (mA)

3

0

C

= 20pF

LOAD

10 20 40

FREQUENCY (MHz)

30

NO LOAD

17201 G12

17201fc

5

LT1720/LT1721

PIN FUNCTIONS

LT1720
+IN A (Pin 1): Noninverting Input of Comparator A.
–IN A (Pin 2): Inverting Input of Comparator A.
–IN B (Pin 3): Inverting Input of Comparator B.
+IN B (Pin 4): Noninverting Input of Comparator B.
GND (Pin 5): Ground.
OUT B (Pin 6): Output of Comparator B.
OUT A (Pin 7): Output of Comparator A.

(Pin 8): Positive Supply Voltage.

V

CC

LT1721
–IN A (Pin 1): Inverting Input of Comparator A.
+IN A (Pin 2): Noninverting Input of Comparator A.
GND (Pins 3, 6): Ground.
OUT A (Pin 4): Output of Comparator A.
OUT B (Pin 5): Output of Comparator B.
+IN B (Pin 7): Noninverting Input of Comparator B.
–IN B (Pin 8): Inverting Input of Comparator B.
–IN C (Pin 9): Inverting Input of Comparator C.
+IN C (Pin 10): Noninverting Input of Comparator C.

(Pins 11, 14): Positive Supply Voltage.

V

CC

OUT C (Pin 12): Output of Comparator C.
OUT D (Pin 13): Output of Comparator D.
+IN D (Pin 15): Noninverting Input of Comparator D.
–IN D (Pin 16): Inverting Input of Comparator D.

6

17201fc

TEST CIRCUITS

15V

BANDWIDTH-LIMITED

P-P

TRIANGLE WAVE

~1kHz

50k

50Ω

50Ω

DUT

V

1/2 LT1720 OR

CM

NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM p15V.
200kW PULL-DOWN PROTECTS LTC203 LOGIC INPUTS
WHEN DUT IS NOT POWERED

1/4 LT1721

1/2 LT1638

+

–

100k

100k

LT1720/LT1721

±V

Test Circuit

TRIP

LTC203

V

CC

0.1μF

+

–

100k

100k

+

–

1/2 LT1638

200k

LTC203

2.4k

0.15μF

15 3 214

1000 s V

TRIP

HYST

OS

TRIP

+

–

1000 s V

10k

1000 s V

10k

1000 s V

17201 TC01

1μF

1μF

–

–

1/2 LT1112

+

1/2 LT1112

+

10nF

16

9

10 6 711

2 14 153

10nF

1

8

7 11 106

1

8

16

9

–3V

Response Time Test Circuit

– V

+V

CC

+

–

TRIP

–V

CM

0.01μF

10 s SCOPE PROBE

≈ 10pF)

(C

IN

0.01μF

CM

+

)

17201 TC02

17201fc

0V

–100mV

25Ω

0.1μF

0V

PULSE

IN

1N5711

50Ω

–5V

130Ω

400Ω

2N3866

750Ω

V1*

*V1 = –1000 • (OVERDRIVE  V
NOTE: RISING EDGE TEST SHOWN.
FOR FALLING EDGE, REVERSE LT1720 INPUTS

1/2 LT1720 OR

25Ω

50k

50Ω

DUT

1/4 LT1721

7

LT1720/LT1721

APPLICATIONS INFORMATION

Input Voltage Considerations

The LT1720/LT1721 are specifi ed for a common mode range
of –100mV to 3.8V when used with a single 5V supply. In
general the common mode range is 100mV below ground
to 1.2V below V
limit is that the output still responds correctly to a small
differential input signal. Also, if one input is within the
common mode limit, the other input signal can go outside
the common mode limits, up to the absolute maximum
limits (a diode drop past either rail at 10mA input current)
and the output will retain the correct polarity.

When either input signal falls below the negative common
mode limit, the internal PN diode formed with the substrate
can turn on, resulting in signifi cant current fl ow through
the die. An external Schottky clamp diode between the
input and the negative rail can speed up recovery from
negative overdrive by preventing the substrate diode from
turning on.

When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least –400mV common mode.
However, the offset and hysteresis in this mode will increase
dramatically, to as much as 15mV each. The input bias
currents will also increase.

When both input signals are above the positive common
mode limit, the input stage will become debiased and
the output polarity will be random. However, the internal
hysteresis will hold the output to a valid logic level, and
because the biasing of each comparator is completely
independent, there will be no impact on any other com­parator. When at least one of the inputs returns to within
the common mode limits, recovery from this state will
take as long as 1μs.

The propagation delay does not increase signifi cantly when
driven with large differential voltages. However, with low
levels of overdrive, an apparent increase may be seen with
large source resistances due to an RC delay caused by the
2pF typical input capacitance.

. The criterion for this common mode

CC

Input Protection

The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
equal to the supply voltage, limited only by the absolute
maximum currents noted. External input protection cir­cuitry is only needed if currents would otherwise exceed
these absolute maximums. The internal catch diodes can
conduct current up to these rated maximums without
latchup, even when the supply voltage is at the absolute
maximum rating.

The LT1720/LT1721 input stage has general purpose
internal ESD protection for the human body model. For
use as a line receiver, additional external protection may
be required. As with most integrated circuits, the level
of immunity to ESD is much greater when residing on a
printed circuit board where the power supply decoupling
capacitance will limit the voltage rise caused by an ESD
pulse.

Unused Inputs

The inputs of any unused compartor should be tied off in
a way that defi nes the output logic state. The easiest way
to do this is to tie IN

Input Bias Current

Input bias current is measured with both inputs held at 1V.
As with any PNP differential input stage, the LT1720/LT1721
bias current fl ows out of the device. With a differential
input voltage of even just 100mV or so, there will be zero
bias current into the higher of the two inputs, while the
current fl owing out of the lower input will be twice the
measured bias current. With more than two diode drops
of differential input voltage, the LT1720/LT1721’s input
protection circuitry activates, and current out of the lower
input will increase an additional 30% and there will be a
small bias current into the higher of the two input pins,
of 4μA or less. See the Typical Performance curve “Input
Current vs Differential Input Voltage.”

+

to VCC and IN– to GND.

8

17201fc

APPLICATIONS INFORMATION

LT1720/LT1721

High Speed Design Considerations

Application of high speed comparators is often plagued
by oscillations. The LT1720/LT1721 have 4mV of internal
hysteresis, which will prevent oscillations as long as
parasitic output to input feedback is kept below 4mV.
However, with the 2V/ns slew rate of the LT1720/LT1721
outputs, a 4mV step can be created at a 100Ω input source
with only 0.02pF of output to input coupling. The pinouts
of the LT1720/LT1721 have been arranged to minimize
problems by placing the most sensitive inputs (invert­ing) away from the outputs, shielded by the power rails.
The input and output traces of the circuit board should
also be separated, and the requisite level of isolation is
readily achieved if a topside ground plane runs between
the outputs and the inputs. For multilayer boards where
the ground plane is internal, a topside ground or supply
trace should be run between the inputs and outputs, as
illustrated in Figure 1.

Although both VCC pins are electrically shorted internal to
the LT1721, they must be shorted together externally as
well in order for both to function as shields. The same is
true for the two GND pins.

The supply bypass should include an adjacent 10nF ce­ramic capacitor and a 2.2μF tantalum capacitor no farther
than 5cm away; use more capacitance if driving more
than 4mA loads. To prevent oscillations, it is helpful to
balance the impedance at the inverting and noninverting
inputs; source impedances should be kept low, preferably
1kΩ or less.

The outputs of the LT1720/LT1721 are capable of very
high slew rates. To prevent overshoot, ringing and other
problems with transmission line effects, keep the output
traces shorter than 10cm, or be sure to terminate the lines
to maintain signal integrity. The LT1720/LT1721 can drive
DC terminations of 250Ω or more, but lower characteristic
impedance traces can be driven with series termination
or AC termination topologies.

(b)(a)

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Figure 1. Typical Topside Metal for Multilayer PCB Layouts

Figure 1a shows a typical topside layout of the LT1720
on such a multilayer board. Shown is the topside metal
etch including traces, pin escape vias, and the land pads
for an SO-8 LT1720 and its adjacent X7R 10nF bypass
capacitor in a 1206 case.

The ground trace from Pin 5 runs under the device up to
the bypass capacitor, shielding the inputs from the out­puts. Note the use of a common via for the LT1720 and
the bypass capacitor, which minimizes interference from
high frequency energy running around the ground plane
or power distribution traces.

Figure 1b shows a typical topside layout of the LT1721
on a multilayer board. In this case, the power and ground
traces have been extended to the bottom of the device
solely to act as high frequency shields between input and
output traces.

Hysteresis

The LT1720/LT1721 include internal hysteresis, which
makes them easier to use than many other comparable
speed comparators.

The input-output transfer characteristic is illustrated in
Figure 2 showing the defi nitions of V

and V

OS

HYST

based
upon the two measurable trip points. The hysteresis band
makes the LT1720/LT1721 well behaved, even with slowly
moving inputs.

OUT

V

V

HYST

+

– V

TRIP

TRIP

V

–

HYST

–

)

/2

V

TRIP

(= V

TRIP

V

OL

0

–

V

TRIP

VOS =

Figure 2. Hysteresis I/O Characteristics

+

V

+ V

TRIP

2

+

V

OH

$VIN = V

IN

17201 F02

+

– V

–

IN

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