Page 1
LT1468
90MHz, 22V/µs
16-Bit Accurate
Operational Amplifi er
FEATURES
n
90MHz Gain Bandwidth, f = 100kHz
n
22V/μs Slew Rate
n
Settling Time: 900ns (AV = –1, 150μV, 10V Step)
n
Low Distortion, –96.5dB for 100kHz, 10V
n
Maximum Input Offset Voltage: 75µV
n
Maximum Input Offset Voltage Drift: 2µV/°C
n
Maximum (–) Input Bias Current: 10nA
n
Minimum DC Gain: 1000V/mV
n
Minimum Output Swing into 2k: ±12.8V
n
Unity Gain Stable
n
Input Noise Voltage: 5nV/√Hz
n
Input Noise Current: 0.6pA/√Hz
n
Total Input Noise Optimized for 1k < RS < 20k
n
Specifi ed at ±5V and ±15V
P-P
APPLICATIONS
n
16-Bit DAC Current-to-Voltage Converter
n
Precision Instrumentation
n
ADC Buffer
n
Low Distortion Active Filters
n
High Accuracy Data Acquisition Systems
n
Photodiode Amplifi ers
DESCRIPTION
The LT®1468 is a precision high speed operational amplifi er
with 16-bit accuracy and 900ns settling to 150µV for 10V
signals. This unique blend of precision and AC performance
makes the LT1468 the optimum choice for high accuracy
applications such as DAC current-to-voltage conversion
and ADC buffers. The initial accuracy and drift characteristics of the input offset voltage and inverting input bias
current are tailored for inverting applications.
The 90MHz gain bandwidth ensures high open-loop gain
at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and
DC accuracy allow full 16-bit AC and DC performance.
The 22V/µs slew rate of the LT1468 improves large-signal
performance in applications such as active fi lters and
instrumentation amplifi ers compared to other precision
op amps.
The LT1468 is manufactured on a complementary bipolar
process. It is available in a space saving 3mm × 3mm leadless package, as well as small outline and DIP packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
16-Bit DAC I-to-V Converter
20pF
16
DAC
INPUTS
LTC
OFFSET: VOS + IB (6kΩ) < 1LSB
SETTLING TIME TO 150µV = 1.7µs
SETTLING LIMITED BY 6k AND 20pF TO COMPENSATE DAC OUTPUT CAPACITANCE
®
1597
6k
–
LT1468
2k
+
OPTIONAL NOISE FILTER
V
50pF
1468 TA01
OUT
Total Harmonic Distortion vs Frequency
–80
VS = ±15V
= 2
A
V
= 2k
R
L
–90
–100
–110
–120
TOTAL HARMONIC DISTORTION (dB)
–130
100
= 10V
V
OUT
P-P
1k 10k 100k
FREQUENCY (Hz)
1468 TA02
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1
Page 2
LT1468
(
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V–) .................................36V
Maximum Input Current (Note 2) ...........................10mA
Output Short-Circuit Duration (Note 3) ............ Indefi nite
Operating Temperature Range ................. –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
1NULL
–IN
+IN
V
8-LEAD
EXPOSED PAD IS INTERNALLY CONNECTED TO V
–
2
+
3
–
4
DD PACKAGE
3mm × 3mm) PLASTIC DFN
T
= 150°C, θJA = 43°C/W
JMAX
8
DNC*
+
V
7
OUT
6
NULL
5
–
(Note 1)
Specifi ed Temperature Range (Note 4) .... –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C
TOP VIEW
1
NULL
–IN
+IN
V
N8 PACKAGE
8-LEAD PDIP
T
JMAX
T
JMAX
–
2
+
3
–
4
*DO NOT CONNECT
= 150°C, θJA = 130°C/W (N8)
= 150°C, θJA = 190°C/W (S8)
8
DNC*
+
V
7
OUT
6
NULL
5
S8 PACKAGE
8-LEAD PLASTIC SO
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LT1468CN8#PBF NA LT1468CN8 8-Lead PDIP 0°C to 70°C
LT1468IN8#PBF NA LT1468IN8 8-Lead PDIP –40°C to 85°C
LT1468CS8#PBF LT1468CS8#TRPBF 1468 8-Lead Plastic Small Outline 0°C to 70°C
LT1468IS8#PBF LT1468IS8#TRPBF 1468I 8-Lead Plastic Small Outline –40°C to 85°C
LT1468ACDD#PBF LT1468ACDD#TRPBF LDJX 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LT1468AIDD#PBF LT1468AIDD#TRPBF LDJX 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LT1468CDD#PBF LT1468CDD#TRPBF LDJX 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LT1468IDD#PBF LT1468IDD#TRPBF LDJX 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LT1468CN8 NA LT1468CN8 8-Lead PDIP 0°C to 70°C
LT1468IN8 NA LT1468IN8 8-Lead PDIP –40°C to 85°C
LT1468CS8 LT1468CS8#TR 1468 8-Lead Plastic Small Outline 0°C to 70°C
LT1468IS8 LT1468IS8#TR 1468I 8-Lead Plastic Small Outline –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to:
For more information on tape and reel specifi cations, go to:
http://www.linear.com/leadfree/
http://www.linear.com/tapeandreel/
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2
Page 3
LT1468
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS V
V
OS
I
OS
–
I
B
+
I
B
e
n
i
n
R
IN
C
IN
CMRR Common Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio V
A
VOL
V
OUT
I
OUT
I
SC
SR Slew Rate A
GBW Gain Bandwidth f = 100kHz, RL = 2k ±15V
THD Total Harmonic Distortion AV = 2, VO = 10V
, t
t
r
f
Input Offset Voltage N8, S8 ±15V
Input Offset Current ±5V to ±15V 13 50 nA
Inverting Input Bias Current ±5V to ±15V 3 ±10 nA
Noninverting Input Bias Current ±5V to ±15V –10 ±40 nA
Input Noise Voltage 0.1Hz to 10Hz ±5V to ±15V 0.3 µV
Input Noise Voltage f = 10kHz ±5V to ±15V 5 nV/√Hz
Input Noise Voltage f = 10kHz ±5V to ±15V 0.6 pA/√Hz
Input Resistance V
Input Capacitance ±15V 4 pF
Input Voltage Range + ±15V
Input Voltage Range – ±15V
Large-Signal Voltage Gain V
Output Swing RL = 10k
Output Current V
Short-Circuit Current V
Full-Power Bandwidth 10V Peak, (Note 6)
Rise Time, Fall Time AV = 1, 10% to 90%, 0.1V ±15V
Overshoot AV = 1, 0.1V ±15V
Propagation Delay AV = 1, 50% VIN to 50% V
= 25°C. VCM = 0V unless otherwise noted.
A
SUPPLY
±5V
LT1468A, DD Package ±15V
±5V
LT1468, DD Package ±15V
±5V
= ±12.5V
CM
Differential
±15V
±15V
±5V
±5V
= ±12.5V
CM
V
= ±2.5V
CM
= ±4.5V to ±15V 100 112 dB
S
= ±12.5V, RL = 10k
OUT
V
= ±12.5V, RL = 2k
OUT
V
= ±2.5V, RL = 10k
OUT
V
= ±2.5V, RL = 2k
OUT
±15V
±5V
±15V
±15V
±5V
±5V
±15V
R
= 2k
L
R
= 10k
L
R
= 2k
L
= ±12.5V
OUT
V
= ±2.5V
OUT
= 0V, V
OUT
= –1, RL = 2k (Note 5) ±15V
V
= ±0.2V ±15V ±25 ±40 mA
IN
±15V
±5V
±5V
±15V
±5V
±5V
±15V
3V Peak, (Note 6)
±5V
±5V
AV = 2, VO = 10V
, f = 1kHz
P-P
, f = 100kHz
P-P
±15V
±15V
MIN TYP MAX UNITS
100
50
12.5
2.5
96
96
1000
500
1000
500
±13.0
±12.8
±3.0
±2.8
±15
±15
15
11
30
50
30
50
100
150
240
150
13.5
3.5
–14.3
–4.3
110
112
9000
5000
6000
3000
±13.6
±13.5
±3.6
±3.5
±22
±22
22
17
75
175
75
175
200
300
–12.5
–2.5
350
900
60
55
90
88
0.00007
0.0015
11
±5V
12
30
0.1V
OUT
±5V
,
±15V
±5V
35
9
10
µV
µV
µV
µV
µV
µV
P-P
M
k
V
V
V
V
dB
dB
V/mV
V/mV
V/mV
V/mV
V
V
V
V
mA
mA
V/µs
V/µs
kHz
kHz
MHz
MHz
%
%
ns
ns
%
%
ns
ns
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Page 4
LT1468
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS V
t
s
R
O
I
S
Settling Time 10V Step, 0.01%, AV = –1
Output Resistance AV = 1, f = 100kHz ±15V 0.02
Supply Current ±15V
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
0°C ≤ TA ≤ 70°C, VCM = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS V
V
OS
I
OS
–
I
B
+
I
B
CMRR Common Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio V
A
VOL
V
OUT
I
OUT
I
SC
SR Slew Rate A
GBW Gain Bandwidth f = 100kHz, RL = 2k ±15V
I
S
Input Offset Voltage N8, S8 ±15V
Input V
Drift (Note 7)
OS
Input Offset Current
Input Offset Current Drift
Inverting Input Bias Current
Negative Input Current Drift
Noninverting Input Bias Current
Large-Signal Voltage Gain V
Output Swing RL = 10k
Output Current V
Short-Circuit Current V
Supply Current ±15V
= 25°C. VCM = 0V unless otherwise noted.
A
SUPPLY
±15V
10V Step, 150µV, A
5V Step, 0.01%, A
V
= –1
V
= –1
±15V
±5V
±5V
SUPPLY
±5V
LT1468A, DD Package ±15V
±5V
LT1468, DD Package ±15V
±5V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
±5V to ±15V
= ±12.5V
CM
V
= ±2.5V
CM
= ±4.5V to ±15V
S
= ±12.5V, RL = 10k
OUT
V
= ±12.5V, RL = 2k
OUT
V
= ±2.5V, RL = 10k
OUT
V
= ±2.5V, RL = 2k
OUT
±15V
±5V
±15V
±15V
±5V
±5V
±15V
R
= 2k
L
R
= 10k
L
RL = 2k
= ±12.5V
OUT
V
= ±2.5V
OUT
= 0V, V
OUT
= –1, RL = 2k (Note 5) ±15V
V
= ±0.2V ±15V
IN
±15V
±5V
±5V
±15V
±5V
±5V
±5V
±5V
MIN TYP MAX UNITS
760
900
770
3.9
3.6
5.2
5.0
MIN TYP MAX UNITS
●
●
●
●
●
●
●
●
0.7 2.0 µV/°C
150
250
150
250
300
400
65 nA
60 pA/°C
●
±15 nA
40 pA/°C
●
94
●
94
●
98 dB
●
500
●
250
●
500
●
250
●
±12.9
●
±12.7
●
±2.9
●
±2.7
●
±12.5
●
±12.5
●
±17 mA
●
13
●
9
●
55
●
50
●
●
●
±50 nA
6.5
6.3
ns
ns
ns
mA
mA
µV
µV
µV
µV
µV
µV
dB
dB
V/mV
V/mV
V/mV
V/mV
V
V
V
V
mA
mA
V/µs
V/µs
MHz
MHz
mA
mA
4
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LT1468
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS V
V
OS
I
OS
–
I
B
+
I
B
CMRR Common Mode Rejection Ratio V
PSRR Power Supply Rejection Ratio V
A
VOL
V
OUT
I
OUT
I
SC
SR Slew Rate A
GBW Gain Bandwidth f = 100kHz, R
I
S
Input Offset Voltage N8, S8 ±15V
Input V
Drift (Note 7)
OS
Input Offset Current
Input Offset Current Drift
Inverting Input Bias Current
Negative Input Current Drift
Noninverting Input Bias Current
Large-Signal Voltage Gain V
Output Swing RL = 10k
Output Current V
Short-Circuit Current V
Supply Current ±15V
= 25°C. –40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted.
A
SUPPLY
±5V
LT1468A, DD Package ±15V
±5V
LT1468, DD Package ±15V
±5V
±5V to ±15V
±5V to ±15V
MIN TYP MAX UNITS
●
●
●
●
●
●
●
●
±5V to ±15V
±5V to ±15V
●
±5V to ±15V
±5V to ±15V
= ±12.5V
CM
V
= ±2.5V
CM
= ±4.5V to ±15V
S
= ±12V, RL = 10k
OUT
V
= ±10V, RL = 2k
OUT
V
= ±2.5V, RL = 10k
OUT
V
= ±2.5V, RL = 2k
OUT
R
= 2k
L
R
= 10k
L
R
= 2k
L
= ±12.5V
OUT
V
= ±2.5V
OUT
= 0V, V
OUT
= –1, RL = 2k (Note 5) ±15V
V
= ±0.2V ±15V
IN
= 2k ±15V
L
±15V
±5V
±15V
±15V
±5V
±5V
±15V
±15V
±5V
±5V
±15V
±5V
±5V
±5V
±5V
●
92
●
92
●
96 dB
●
300
●
150
●
300
●
150
●
±12.8
●
±12.6
●
±2.8
●
±2.6
●
±7
●
±7
●
±12 mA
●
9
●
6
●
45
●
40
●
●
●
230
330
230
330
400
500
0.7 2.5 µV/°C
80 nA
120 pA/°C
±30 nA
80 pA/°C
±60 nA
7.0
6.8
µV
µV
µV
µV
µV
µV
dB
dB
V/mV
V/mV
V/mV
V/mV
V
V
V
V
mA
mA
V/µs
V/µs
MHz
MHz
mA
mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by back-to-back diodes and two 100
series resistors. If the differential input voltage exceeds 0.7V, the input
current should be limited to 10mA. Input voltages outside the supplies will
be clamped by ESD protection devices and input currents should also be
limited to 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum when the output is shorted indefi nitely.
Note 4: The LT1468C is guaranteed to meet specifi ed performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C and at 85°C. The
LT1468I is guaranteed to meet the extended temperature limits.
Note 5: Slew rate is measured between ±8V on the output with ±12V input
for ±15V supplies and ±2V on the output with ±3V input for ±5V supplies.
Note 6: Full power bandwidth is calculated from the slew rate
measurement: FPBW = SR/2πV
P
Note 7: This parameter is not 100% tested.
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5
Page 6
LT1468
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage
and Temperature
7
6
5
4
3
SUPPLY CURRENT (mA)
2
1
0
5101520
SUPPLY VOLTAGE (±V)
125°C
25°C
–55°C
1468 G01
Input Common Mode Range
vs Supply Voltage
+
V
TA = 25°C
–0.5
–1.0
–1.5
–2.0
2.0
1.5
COMMON MODE RANGE (V)
1.0
0.5
V
< 100µV
ΔV
OS
–
0
3
6
SUPPLY VOLTAGE (±V)
912
Input Bias Current
vs Input Common Mode Voltage
80
VS = ±15V
= 25°C
T
60
A
40
20
0
–20
–40
INPUT BIAS CURRENT (nA)
–60
15
18
1468 G02
–80
–10 –5 5
–15
INPUT COMMON MODE VOLTAGE (V)
–
I
B
I
B
0
Input Bias Current
vs Temperature Input Noise Spectral Density 0.1Hz to 10Hz Voltage Noise
30
20
10
0
VS = ±15V
1000
i
–
I
B
100
n
VS = ±15V
= 25°C
T
A
= 101
A
V
= 100k FOR i
R
S
10
INPUT CURRENT NOISE (pA/√Hz)
n
1
VS = ±15V
+
15
10
1468 G03
–10
–20
INPUT BIAS CURRENT (nA)
–30
–40
–50
–25 0
+
I
B
50 100 125
25 75
TEMPERATURE (°C)
Warm-Up Drift vs Time
5
0
–5
–10
–15
–20
–25
–30
OFFSET VOLTAGE DRIFT (µV)
–35
–40
0 20 40 60 80 100 120 140
TIME AFTER POWER UP (s)
N8 ±5V
S0-8 ±5V
N8 ±15V
S0-8 ±15V
1468 G04
1468 G07
e
10
INPUT VOLTAGE NOISE (nV/√Hz)
n
1
1
10 100 1k 10k
Open-Loop Gain
vs Resistive Load
140
TA = 25°C
135
130
125
120
OPEN-LOOP GAIN (dB)
115
110
10
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
100k
1468 G05
VS = ±15V
VS = ±5V
100 1k 10k
1468 G08
0.1
0.01
160
150
140
130
120
110
OPEN-LOOP GAIN (dB)
100
90
VOLTAGE NOISE (100nV/DIV)
TIME (1s/DIV)
Open-Loop Gain
vs Temperature
RL = 2k
VS = ±15V
VS = ±5V
–50
–25 0
25 75
TEMPERATURE (°C)
1468 G06
50 100 125
1468 G09
6
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Page 7
TYPICAL PERFORMANCE CHARACTERISTICS
LT1468
Output Voltage Swing
vs Supply Voltage
+
V
–1
–2
–3
–4
4
3
2
OUTPUT VOLTAGE SWING (V)
1
= 25°C
T
A
–
V
0
5
SUPPLY VOLTAGE (±V)
Settling Time to 0.01%
vs Output Step, VS = ±15V
10
VS = ±15V
8
= 1k
R
L
6
4
2
0
–2
OUTPUT STEP (V)
–4
–10
–6
–8
0
AV = 1
200
400
SETTLING TIME (ns)
RL = 2k
R
= 10k
L
RL = 2k
RL = 10k
10 15 20
1468 G10
AV = –1
600
A
800
= 1
V
1468 G13
AV = –1
1000
Output Voltage Swing
vs Load Current
+
V
–0.5
VS = ±15V
–1.0
–1.5
–2.0
–2.5
2.5
2.0
1.5
OUTPUT VOLTAGE SWING (V)
1.0
V–0.5
–20
40°C
85°C
–15 –5
–10
OUTPUT CURRENT (mA)
Settling Time to 0.01%
vs Output Step, VS = ±5V
5
VS = ±5V
4
= 1k
R
L
3
2
1
0
–1
OUTPUT STEP (V)
–2
–3
–4
–5
300
AV = 1
AV = 1
400
SETTLING TIME (ns)
25°C
500
0
–40°C
25°C
600
5
AV = –1
85°C
10
15
AV = –1
700
1468 G11
1468 G14
20
800
Output Short-Circuit Current
vs Temperature
60
VS = ±15V
55
= ±0.2V
V
IN
50
–50
–25
SOURCE
0
50
25
TEMPERATURE (°C)
SINK
45
40
35
30
25
20
15
OUTPUT SHORT-CIRCUIT CURRENT (mA)
10
Settling Time to 150μV
vs Output Step
10
VS = ±15V
8
= –1
A
V
= RG = 2k
R
F
6
= 8pF
C
F
4
2
0
–2
OUTPUT STEP (V)
–4
–6
–8
–10
200
0
SETTLING TIME (ns)
400
600
800
100
125
1468 G12
1000
1468 G15
75
Gain Bandwidth and Phase
Margin vs Supply Voltage
98
TA = 25°C
= –1
A
96
V
= RG = 5.1k
R
F
= 5pF
C
F
94
= 2k
R
L
92
90
88
GAIN BANDWIDTH (MHz)
86
84
82
0
GAIN BANDWIDTH
5
10
SUPPLY VOLTAGE (±V)
PHASE MARGIN
15
1468 G17
104
44
102
42
100
PHASE MARGIN (DEG)
40
38
36
34
32
GAIN BANDWIDTH (MHz)
30
28
20
Gain Bandwidth and Phase
Margin vs Temperature Output Impedance vs Frequency
98
96
94
92
GAIN BANDWIDTH
90
88
86
84
–55
–25
PHASE MARGIN
25
0
TEMPERATURE (°C)
VS = ±15V
VS = ±5V
VS = 15V
VS = 5V
50
46
44
42
40
38
36
34
32
30
28
26
100
125
1468 G18
75
100
VS = ±15V
= 25°C
T
A
10
PHASE MARGIN (DEG)
OUTPUT IMPEDANCE (Ω)
0.01
0.001
AV = 100
1
= 10
A
V
0.1
= 1
A
V
10k 1M 10M 100M
100k
FREQUENCY (Hz)
1468 G19
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7
Page 8
LT1468
TYPICAL PERFORMANCE CHARACTERISTICS
Gain and Phase vs Frequency
70
60
50
40
30
GAIN (dB)
20
TA = 25°C
10
= –1
A
V
= RG = 5.1k
R
F
0
C
= 5pF
F
= 2k
R
L
–10
10k 1M 10M 100M
100k
FREQUENCY (Hz)
PHASE
±15V
±5V
GAIN
±15V
±5V
Frequency Response
±5V
V
±15V
= 1
vs Supply Voltage, A
5
TA = 25°C
4
= 1
A
V
= 2k
R
L
3
2
1
0
GAIN (dB)
–1
–2
–3
–4
–5
100k
1M 10M 100M
FREQUENCY (Hz)
1468 G16
1468 G22
100
80
60
PHASE (DEG)
40
20
0
–20
–40
–60
Power Supply Rejection Ratio
vs Frequency
160
VS = ±15V
= 25°C
T
A
140
120
100
80
60
40
20
POWER SUPPLY REJECTION RATIO (dB)
+PSRR
–PSRR
0
1k 10k 1M
100
100k
FREQUENCY (Hz)
Frequency Response
vs Supply Voltage, AV = –1
5
4
3
RF = RG = 5.1k
2
1
0
GAIN (dB)
–1
–2
–3
–4
–5
100k
TA = 25°C
= –1
A
V
= 2k
R
L
= 5pF
C
F
±5V
±15V
1M 10M 100M
FREQUENCY (Hz)
10M
1468 G20
RF = RG = 2k
±5V
±15V
1468 G23
100M
Common Mode Rejection Ratio
vs Frequency
120
100
80
60
40
20
COMMON MODE REJECTION RATIO (dB)
0
100
10k 100k 1M
1k
FREQUENCY (Hz)
Frequency Response
vs Capacitive Load, AV = 1
14
VS = ±15V
12
= 25°C
T
A
= 1
A
V
10
NO R
L
8
6
4
GAIN (dB)
2
0
–2
–4
–6
100k
1M 10M 100M
FREQUENCY (Hz)
100pF
50pF
20pF
VS = ±15V
= 25°C
T
A
10M 100M
10pF
1468 G21
1468 G24
Frequency Response
vs Capacitive Load, AV = –1 Slew Rate vs Supply Voltage Slew Rate vs Temperature
14
VS = ±15V
12
T
A
10
R
C
8
NO R
6
4
GAIN (dB)
2
0
–2
–4
–6
100k
= 25°C
A
= –1
V
= RG = 5.1k
F
= 5pF
F
L
300pF
200pF
100pF
50pF
1M 10M 100M
FREQUENCY (Hz)
1468 G25
30
TA = 25°C
= –1
A
V
28
= 2k
R
L
26
24
22
20
SLEW RATE (V/µs)
18
16
14
0
–SR
+SR
5
10
SUPPLY VOLTAGE (±V)
15
20
1468 G26
45
VS = ±15V
= –1
A
V
40
= 2k
R
L
35
30
25
20
SLEW RATE (V/µs)
15
10
5
–25 0 50
–50
8
–SR
+SR
25
TEMPERATURE (°C)
75 100 125
1468 G27
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Page 9
TYPICAL PERFORMANCE CHARACTERISTICS
LT1468
Total Harmonic Distortion + Noise
vs Frequency
0.010
VS = ±15V
= 25°C
T
A
= 600Ω
R
L
= 20V
V
O
P-P
NOISE BW = 80kHz
0.001
THD + NOISE (%)
0.0001
AV = 10
AV = 1
MEASUREMENT
LIMIT
20
100 1k 20k10k
FREQUENCY (Hz)
1468 G28
Total Harmonic Distortion + Noise
vs Amplitude
–50
–60
–70
–80
–90
THD + NOISE (dB)
TA = 25°C
= 10
A
V
–100
–110
= 600Ω
R
L
f = 10kHz
NOISE BW = 80kHz
0.01
0.1 1 10
OUTPUT SIGNAL (V
Small-Signal Transient, AV = 1 Small-Signal Transient, AV = –1
VS = ±15V
1468 G31
VS = ±15V
RMS
Undistorted Output Swing
vs Frequency, ± 15V
30
)
25
±15V±5V
)
1468 G29
P-P
20
15
10
5
OUTPUT VOLTAGE SWING (V
VS = ±15V
= 2k
R
L
0
1
10 100 1000
FREQUENCY (kHz)
AV = 1
AV = –1
1468 G30
Undistorted Output Swing
vs Frequency, ± 5V
10
VS = ±5V
9
= 2k
R
L
)
8
1468 G32
P-P
7
6
5
4
3
2
OUTPUT VOLTAGE SWING (V
1
0
1
10 100 1000
FREQUENCY (kHz)
AV = 1
AV = –1
1468 G33
Large-Signal Transient, AV = 1 Large-Signal Transient, AV = –1
VS = ±15V
1468 G34
VS = ±15V
1468 G35
Total Noise vs Unmatched
Source Resistance
100
VS = ±15V
= 25°C
T
A
f = 10kHz
10
1
TOTAL NOISE VOLTAGE (nV/√Hz)
0.1
10 1k 10k 100k
TOTAL
NOISE
RESISTOR
NOISE ONLY
R
S
+
–
100
SOURCE RESISTANCE, RS (Ω)
1468 G36
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9
Page 10
LT1468
APPLICATIONS INFORMATION
The LT1468 may be inserted directly into many operational
amplifi er applications improving both DC and AC performance, provided that the nulling circuitry is removed.
The suggested nulling circuit for the LT1468 is shown
below.
Offset Nulling
+
V
3
+
LT1468
2
–
1
5
100k
7
6
4
–
V
2.2µF0.1µF
2.2µF0.1µF
1468 AI01
Layout and Passive Components
The LT1468 requires attention to detail in board layout
in order to maximize DC and AC performance. For best
AC results (for example fast settling time) use a ground
plane, short lead lengths, and RF-quality bypass capacitors
(0.01µF to 0.1µF) in parallel with low ESR bypass capacitors (1µF to 10µF tantalum). For best DC performance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (i.e., 1.5G of leakage between an
input and a 15V supply will generate 10nA—equal to the
–
maximum I
specifi cation.)
B
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close
to that of the inputs. For inverting confi gurations tie the
ring to ground, in noninverting connections tie the ring
to the inverting input (note the input capacitance will
increase which may require a compensating capacitor as
discussed below.)
Microvolt level error voltages can also be generated in
the external circuitry. Thermocouple effects caused by
temperature gradients across dissimilar metals at the
contacts to the inputs can exceed the inherent drift of
the amplifi er. Air currents over device leads should be
minimized, package leads should be short, and the two
input leads should be as close together as possible and
maintained at the same temperature.
Make no connection to Pin 8. This pin is used for factory
trim of the inverting input current.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole that can cause peaking
or even oscillations. For feedback resistors greater than
2k, a feedback capacitor of the value:
> (RG)(CIN/RF)
C
F
should be used to cancel the input pole and optimize dynamic performance. For applications where the DC noise
gain is one, and a large feedback resistor is used, C
be greater than or equal to C
. An example would be a
IN
should
F
DAC I-to-V converter as shown on the front page of this
data sheet where the DAC can have many tens of pF of
output capacitance. Another example would be a gain of – 1
with 5k resistors; a 5pF to 10pF capacitor should be added
across the feedback resistor. The frequency response in a
gain of –1 is shown in the Typical Performance curves with
2k and 5.1k resistors with a 5pF feedback capacitor.
Nulling Input Capacitance
R
F
C
F
R
G
C
IN
V
–
LT1468
+
IN
V
OUT
1468 AI02
10
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Page 11
APPLICATIONS INFORMATION
LT1468
Input Considerations
Each input of the LT1468 is protected with a 100 series
resistor and back-to-back diodes across the bases of the
input devices. If the inputs can be pulled apart, the input
current should be limited to less than 10mA with an external series resistor. Each input also has two ESD clamp
diodes—one to each supply. If an input is driven above
the supply, limit the current with an external resistor to
less than 10mA.
The LT1468 employs bias current cancellation at the inputs.
The inverting input current is trimmed at zero common
mode voltage to minimize errors in inverting applications
such as I-to-V converters. The noninverting input current
is not trimmed and has a wider variation and therefore a
larger maximum value. As the input offset current can be
greater than either input current, the use of balanced source
resistance is NOT recommended as it actually degrades
DC accuracy and also increases noise.
The input bias currents vary with common mode voltage
as shown in the Typical Performance Characteristics.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
The LT1468 inputs can be driven to the negative supply
and to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the positive supply, the output reverses phase.
Total Input Noise
The curve of Total Noise vs Unmatched Source Resistance
in the Typical Performance Characteristics shows that
with source resistance below 1k, the voltage noise of the
amplifi er dominates. In the 1k to 20k region the increase
in noise is due to the source resistance. Above 20k the
input current noise component is larger than the resistor
noise.
Capacitive Loading
The LT1468 drives capacitive loads of up to 100pF in unity
gain and 300pF in a gain of –1. When there is a need to
drive a larger capacitive load, a small series resistor should
be inserted between the output and the load. In addition,
a capacitor should be added between the output and the
inverting input as shown in Driving Capacitive Loads.
Settling Time
The LT1468 is a single stage amplifi er with an optimal
thermal layout that leads to outstanding settling
performance. Measuring settling, even at the 12-bit level
is very challenging, and at the 16-bit level requires a great
deal of subtlety and expertise. Fortunately, there are two
excellent Linear Technology reference sources for settling
measurements, Application Notes 47 and 74. Appendix B
of AN47 is a vital primer on 12-bit settling measurements,
and AN74 extends the state of the art while concentrating
on settling time with a 16-bit current output DAC input.
Input Stage Protection
R1
100Ω
+IN –IN
Q1 Q2
R2
100Ω
1468 AI03
Driving Capacitive Loads
R
F
C
F
R
G
V
–
LT1468
+
IN
RO ≥ (1 + RF/RG)/(2πCL5MHz)
≥ 10R
R
F
O
CF = (2RO/RF)C
R
O
V
OUT
C
L
1468 AI04
L
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11
Page 12
LT1468
APPLICATIONS INFORMATION
The 150µV settling curve in the Typical Performance
Characteristics is measured using the Differential Amplifi er
method of AN74 followed by a clamped, nonsaturating
gain of 100. The total gain of 500 allows a resolution of
100µV/DIV with an oscilloscope setting of 0.05V/DIV
The settling of the DAC I-to-V converter on the front page
was measured using the exact methods of AN74. The
optimum nulling of the DAC output capacitance requires
20pF across the 6k feedback resistor. The theoretical limit
for 16-bit settling is 11.1 times this RC time constant or
1.33µs. The actual settling time is 1.7µs at the output of
the LT1468. The LT1468 is the fastest Linear Technology
amplifi er in this application.
The optional noise fi lter adds a slight delay of 100ns, but
reduces the noise bandwidth to 1.6MHz which increases
the output resolution for 16-bit accuracy.
Distortion
The LT1468 has outstanding distortion performance as
shown in the Typical Performance curves of Total Harmonic
Distortion + Noise vs Frequency and Amplitude. The high
open-loop gain and inherently balanced architecture reduce
errors to yield 16-bit accuracy to frequencies as high as
100kHz. An example of this performance is the Typical
Application titled 100kHz Low Distortion Bandpass Filter.
This circuit is useful for cleaning up the output of a high
performance signal generator such as the B & K type
1051 or HP3326A.
Another key application for LT1468 is buffering the input
to a 16-bit A/D converter. In a gain of 1 or 2 this straightforward circuit provides uncorrupted AC and DC levels
to the converter, while buffering the A/D input sampleand-hold circuit from high source impedance which can
reduce the maximum sampling rate. The front page graph
shows better than 16-bit distortion for a gain of 2 with a
10V
output.
P-P
SIMPLIFIED SCHEMATIC
+
V
I4 I6
I3
–
V
I2I1
Q8
Q5Q2
Q3
Q6Q1 –IN+IN
Q7
Q4
BIAS
C
I5
Q10
Q9
OUT
Q11
1468 SS
12
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Page 13
PACKAGE DESCRIPTION
LT1468
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 p0.05
3.5 p0.05
1.65 p0.05
(2 SIDES)2.10 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.50
BSC
2.38 p0.05
3.00 p0.10
(4 SIDES)
0.75 p0.05
0.00 – 0.05
1.65 p 0.10
(2 SIDES)
R = 0.125
TYP
0.25 p 0.05
2.38 p0.10
BOTTOM VIEW—EXPOSED PAD
0.40 p 0.10
85
14
0.50 BSC
(DD8) DFN 0509 REV C
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13
Page 14
LT1468
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
(10.160)
8 76
.255 ± .015*
(6.477 ± 0.381)
.400*
MAX
5
12
.300 – .325
(7.620 – 8.255)
.065
(1.651)
.008 – .015
(0.203 – 0.381)
+.035
.325
–.015
+0.889
8.255
()
–0.381
NOTE:
1. DIMENSIONS ARE
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
INCHES
MILLIMETERS
TYP
.045 – .065
(1.143 – 1.651)
.100
(2.54)
BSC
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
.050 BSC
.045 ±.005
(4.801 – 5.004)
8
3
.189 – .197
NOTE 3
7
4
.130 ± .005
(3.302 ± 0.127)
(3.048)
.018 ± .003
(0.457 ± 0.076)
5
6
.120
MIN
.020
(0.508)
MIN
N8 1002
14
.245
MIN
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.50
.00
8 – .010
(0.203 – 0.254)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
8)
.016 – .050
(0.406 – 1.270)
INCHES
(MILLIMETERS)
× 45°
.160
±.005
0°– 8° TYP
.228 – .244
(5.791 – 6.197)
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.150 – .157
(3.810 – 3.988)
NOTE 3
1
3
2
4
.050
(1.270)
BSC
.004 – .010
(0.101 – 0.254)
SO8 0303
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Page 15
LT1468
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
B 10/09 Change to Both Packages in Pin Confi guration 2
(Revision history begins at Rev B)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1468fb
15
Page 16
LT1468
TYPICAL APPLICATIONS
Instrumentation Amplifi er 16-Bit ADC Buffer
R5
1.1k
R2
5k
–
LT1468
+
C1
10pF
R3
5k
–
LT1468
+
R1
50k
–
V
IN
+
GAIN = [R4/R3][1 + (1/2)(R2/R1 + R3/R4) + (R2 + R3)/R5] = 102
TRIM R5 FOR GAIN
TRIM R1 FOR COMMON MODE REJECTION
BW = 480kHz
R4
50k
C2
2pF
2k
V
IN
V
OUT
1468 TA03
100kHz Low Distortion Bandpass Filter
–
+
10pF
2k
LT1468
200Ω
1000pF
33.2k
LTC1605
CAP
16 BITS
1468 TA04
2.2µF
1000pF
22.1k
1000pF
11k
V
IN
121Ω
fO = 100kHz
Q = 7
= –1
A
V
–
LT1468
+
R
V
OUT
L
100kHz Distortion
SIGNAL LEVEL
1V
RMS
2V
RMS
3.5V
RMS
1V
RMS
2V
RMS
3.5V
RMS
2ND HARMONIC
R
L
1M
1M
1M
2k
2k
2k
–106dB
–105dB
–106dB
–103dB
–99dB
–96.5dB
3RD HARMONIC
–103dB
–105dB
–104dB
–103dB
–103dB
–102dB
1468 TA05
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1167 Precision Instrumentation Amplifi er Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain
Nonlinearity
LTC1595/LTC1596 16-Bit Serial Multiplying I
LTC1597 16-Bit Parallel Multiplying I
LTC1604 16-Bit, 333ksps Sampling ADC ±2.5V Input, SINAD = 90dB, THD = –100dB
LTC1605 Single 5V, 16-Bit, 100ksps Sampling ADC Low Power, ±10V Inputs, Parallel/Byte Interface
LT1469 Dual 90MHz 16-Bit Accurate Op Amp Dual Version of LT1468
LT1800 80MHz, 25V/s Low Power Rail-to-Rail Precision Op Amp V
LT6220 60MHz, 20V/s Low Power Rail-to-Rail Precision Op Amp V
LT1722 200MHz, 70V/s Low Noise Precision Op Amp V
LTC6244HV Dual 50MHz, Low Noise, Precision CMOS Op Amp V
DACs ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
OUT
DAC ±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors
OUT
≤ ±5V, ICC = 1.6mA, VOS ≤ 350V
S
≤ ±5V, ICC = 0.9mA, VOS ≤ 350V
S
≤ ±5V, en = 3.8nV/√Hz, –85dBc at 1MHz
S
≤ ±5V, VOS ≤ 100V, IB ≤ 75pA
S
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
1468fb
LT 1009 REV B • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 1998
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