Analog Devices ee-86 Application Notes

Engineer To Engineer Note EE-86

Technical Notes on using Analog Devices’ DSP components and development tools

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Interfacing SHARC 2106x DSPs to PLX 9080 PCI Bridge Chips

Introduction

PCI is currently the most common local bus standard for PC systems, but it also is very common in embedded systems. In a
typical system, one or more DSPs are the main signal processing components of a PCI card, which is controlled by the main
processor of the system. While in some PCI based systems, the DSP cards include all of their own I/O, on many others,
significant quantities of data are passed over the PCI bus.
PCI is a back-plane with multiple PCI controllers. Some microprocessors contain PCI controllers within them, while other PCI
controllers are bridges, designed to interface PCI to a local bus. This, segments the system into a series of local buses. Each
local bus can contain local processors and peripherals. While the PCI interface is common to all systems, the local bus
interfaces depend on the devices on the bus. Most bridge chips are designed to interface to several different types of
microprocessors. Since no bridges directly interface to a SHARC, some glue logic is needed between the SHARC and the
bridge chip.
PLX is a leading vendor of PCI solutions. The PLX 9080 is commonly used with the SHARC, an example being the Bittware
Snaggletooth PCI board. It supports a 5V local bus. For systems using the 3.3V SHARCs, the PLX 9054 supports a superset
of the 9080 capabilities, and supports a 3.3V local bus system. This note will discuss the hardware interface of the SHARC to
the PLX 9080 or 9054.

Interface Description

Since the External Port of a SHARC does not match the Local Bus of the PCI 9080, there is need for some glue logic. The
complexity of this glue logic depends on how complex the local bus is, and on how much performance is needed over the bus.

SHARC External Port

The external port of the SHARC can be either a local bus master or slave. When a SHARC is bus master, it drives the address
and control lines, and the data lines on writes. When a SHARC is bus slave, either to another SHARC or to the host
processor, it responds to the control lines, and drives the data lines on reads. The SHARC external port includes the logic to
arbitrate for the bus among multiple SHARCs, as well as to yield the bus upon a host bus request. The SHARC addressing
scheme is word based, in this case 32 bit words. We will treat the external port as interfacing to 32 bit wide external memory or
a 32 bit wide host, only. Table 1 describes the pins of the SHARC external port.

Pin Name Type Description

HBR Host Bus Request I/A Must be asserted by a host processor to request control of the ADSP-

2106x’s external bus. When HBR is asserted in a multiprocessing system,
the ADSP-2106x that is bus master will relinquish the bus and assert HBG.
To relinquish the bus, the ADSP-2106x places the address, data, select,
and strobe lines in a high-impedance state. HBR has priority over all
ADSP-2106x bus requests ( BR1-6 ) in a multiprocessing system.

HBG Host Bus Grant. I/O Acknowledges an HBR bus request, indicating that the host processor may

take control of the external bus. HBG is asserted (held low) by the ADSP­2106x until HBR is released. In a multiprocessing system, HBG is output

a

by theADSP-2106x bus master and is monitored by all others.

Indicates a valid address and start of a new Bus access. Asserted for first clock

CS Chip Select I/A. Asserted by host processor to select the ADSP 2106x.
REDY Host Bus Acknowledge (o/d) O The ADSP-2106x deasserts REDY (low) to add wait states to an

asynchronous access of its internal memory or IOP registers by a host.
Open-drain output (o/d) by default; can be programmed in ADREDY bit
of SYSCON register to be active drive (a/d). REDY will only be output if
the CS and HBR inputs are asserted.

SBTS Suspend Bus Tristate I/S External devices can assert SBTS (low) to place the external bus address,

data, selects, and strobes in a high-impedance state for the following
cycle. If the ADSP-2106x attempts to access external memory while
SBTS is asserted, the processor will halt and the memory access will not
be completed until SBTS is deasserted. SBTS should only be used to
recover from PAGE faults or host processor/ADSP-2106x deadlock.

Table 1 SHARC External Port Pins

The SHARC external port is designed to provide 0 wait state access to external memory, so the address and data busses are
not multiplexed. On a write, address and data busses are both driven on the same cycle, and on a read, the address lines are
driven at the start of the cycle and the read lines are sampled at the end. Both reads and writes can be slowed down by
inserting wait states or by deasserting ACK to indicate that the SHARC is not yet ready. The SHARC external port can
support either synchronous or asynchronous accesses. It contains no signals to support burst accesses.
The external port also includes some FIFOs to buffer data when a SHARC is written to. This enables the throughput of a
SHARC to be greater on writes than on reads. Also, due to the internal structure of the SHARC, the response to I/O buffer
reads is quicker than that to memory reads. As a result, the highest throughput is achieved by using a SHARC DMA channel
than by doing individual memory transfers. Both of these should be controlled by system software to achieve the maximum
throughput.

9080 Local Bus

The 9080 local bus interface is designed to support several different types of interfaces. The one used to interface to the
SHARC is C mode: 32 bit address, 32 bit data, not multiplexed. The external port assumes a byte addressing scheme, and
provides individual byte enables. The 9080 local bus interface does not perform bus arbitration on its own, but includes
signals HOLD and HOLDA to request that another arbiter grant it the bus. It is designed for synchronous pipelined burst
access, so it drives the address bus for one cycle, then the databus in the following cycle, with the next address on the
address bus. The BLAST signal indicates that the last address has been presented on the bus. The READY lines are used to
add delay to transfers.

Pin Name Type Description

ADS# Address Strobe I/O TS

of a Bus access.

BLAST# Burst Last 1 I/O TS Signal driven by current Local Bus Master to indicate last transferin a Bus

access.

BTERM# Burst Terminate I For processors that burst up to four Lwords. If Bterm is disabled through

the PCI 9080 Configuration registers, the PCI 9080 also bursts up to four
Lwords. If enabled, the PCI 9080 continues to burst until a BTERM# input
is asserted. BTERM# is a ready input that breaks up a Burst cycle and
causes another Address cycle to occur. Used in conjunction with the PCI
9080 programmable wait state generator.

DEN# Data Enable O S Used in conjunction with DT/R# to provide control for data transceivers

attached to Local Bus.

DT/R# Data Transmit/Receive O TS Used in conjunction with DEN# to provide control for data transceivers

attached to Local Bus. When asserted, signal indicates the PCI 9080
receives data.

EE-86 Page 2

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], FTP: ftp.analog.com, EMAIL: [e-mail]