Analog Devices ee-36 Application Notes

Engineer To Engineer Note EE-36

Notes on using Analog Devices’ DSP, audio, & video components from the Computer Products Division

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ADSP-21xx interface to the IOM-2
bus

Last Modified: 7/23/97

Introduction

The IOM Revision 2 ( IOM-2 ) standard defines an
industry standard serial bus for interconnecting
telecommunications ICs. The serial interface satisfies the
requirements of ISDN and analog applications and has
been defined by four major European telephone equipment
manufacturers.

The IOM-2 Bus

The IOM-2 bus is a synchronous full duplex
communication link, containing user data,
control/programming, and status channels and has been
designed for terminal mode and line card mode. Both the
line card mode and terminal portions of the IOM-2
standard utilize the same basic frame and clocking
structure, but differ in the number and usage of the
individual channels that are time-multiplexed over a four­wire serial interface. Data is clocked by a Data Clock
(DCL) that operates at twice the data rate. A frame is
delimited by an 8-kHz Frame Synchronization Clock
(FSC). Data is transmitted over Data Upstream (DU) and
Data Downstream (DD).

Line Card Mode

The line card version of the IOM-2 provides a connection
path between line transceivers (ISDN) and codecs (analog),
and the line card controller; the line card controller
provides the connection to the switch backbone. In this
mode up to 8 ISDN transceiver or up to 16 codecs/filters
could be connected to the bus. Data, control and status
information is multiplexed into frame, which are
transmitted in an 8kHz rate. The frames are divided into 8
sub-frames, with one sub-frame being dedicated to each
transceiver or pair of codecs.

Terminal Mode

The Terminal Mode is designed for ISDN and NT1
applications.

The IOM-2 terminal version consists of three subframes,
each containing 32 bits. This 12 byte frame is repeated at
8kHz, giving an aggregate data rate of 768kbit/s.

ADSP-21xx Serial Port

The ADSP-21xx has one/two synchronous serial full­duplex 5 wire ports (SPORT) and one of these interfaces
supports time-multiplexed data streams. Data is clocked
by the Serial Clock (SCLK) that operates at the data rate.
Optional there is a Frame Sync Signal for the receive &
transmit side that indicates the start of a new word or
frame in multichannel mode. Data is sent over Data
Transmit (DT) and Data Receive (DR) lines. In normal
operation an interrupt is generated when an word has been
received or when a transmitted word has been shifted out
of the SPORT. There are two independent interrupt vector
locations to handle the receiving and transmitting section
separately.

Autobuffering

The generation of an interrupt after each transmitted/
received word would cause a huge overhead and for this
reason you could use an autobuffering mode that
automatically transfers SPORT data to/from the internal
memory of the DSP. For this application you have to
define a circular buffer in the internal memory that should
hold the data to be sent/received. The length of the buffer
is user defined and when the buffer is full or has been read
completely an interrupt will be generated and the buffer
will be filled/ read again by the SPORT. This means we
have to process the data in the buffer before the SPORT
accesses this memory again.

Multichannel Mode

As already mentioned above one of the SPORTs of the
DSP has the possibility to handle time-multiplexed data
streams. It is possible to choose between 24 or 32 time
slots. The user can define in which time slots he wants to
send data and which time slots should be ignored during
reception. This can be done independently for the receiving
& and transmitting side. The autobuffering mode could
also be combined with the MC mode. The best way to
combine autobuffering and multichannel mode is to set
the length of the circular autobuffer to the number of
time slots that should be sent/ received. In the following

sections it is assumed that an external device is generating

125 us

the SCLK and Frame Sync. Signals.
As the IOM-2 standard is using only one Frame Sync.
Signal, RFS and TFS of the DSP have to be shorted.

IOM-2 Line-Card Mode Interfacing

Remember that the IOM-2 standard is using a clock that
operates at twice the data rate. The ADSP-21xx family
does not have a double serial clock feature and therefore we
have to divide the DCL using a Flip Flop. In the Line­Card Mode we have 8 channels each consisting of 32 bits
(256 bits total length). The number of DSP channels is
set to 32 and therefore each DSP time slot is 1 Byte long
(256 bits total frame length/32 time slots). The word
length (SLEN) of the DSP is set to 7 and the DSP now
interprets all incoming data as words of the length of one
byte.

D0

CH0 x00 0x00 B1 (8 bits)

x01 0x00 B2 (8 bits)
x02 0x00 Monitor (8bits)
x03 0x00

D2(2)C/I(4)

MR(1) MX(1)

CH1 x04 0x00 B1 (8 bits)

x05 0x00 B2 (8 bits)
x06 0x00 Monitor (8bits)
x07 0x00 D2 C/I MR MX

:

: :

CH7 x1c 0x00 B1 (8 bits)

x1d 0x00 B2 (8 bits)
x1e 0x00 Monitor (8bits)
x1f 0x00 D2 C/I MR MX

The Multichannel Word Select register could be used to
ignore certain time slots. In this case you could
implement a shorter autobuffer.

SC

CL

x IOM CH0

CH1 CH2 CH3 CH4 CH5 CH6 CH7

B1 (8) B2 (8) Monitor (8) D (2) C/I (4) MR MX
B1 (8) B2 (8) Monitor (8) C/I (6)

DSP

time slot 0

DSP

time slot 1

DSP

time slot 2

DSP

time slot 3

Figure 1: IOM-2 Line Card Frame Structure

DCL=4.096MHz

At last we must declare an autobuffer in the data memory
(DM) of the DSP that is 32 locations deep as we are
going to handle 32 time slots.

- MC enabled / 32 slots

- Autobuffering enabled

- SLEN = 7

- DTYPE = 00 (right justified MSBs zero filled )

- MCWS = FF FF (all time slots enabled )

MR MX

CH0

In the following example only the B1, B2 channels should
be serviced and the monitor and control bits should be
ignored.
The following settings could be used:

- MC enabled / 32 slots

- Autobuffering enabled

- SLEN = 7

- DTYPE = 00 (right justified MSBs zero filled )

- MCWS = CC CC (1st two time slots of each IOM
channel )

In this case it is convenient to use a 16 ( two B words * 8
channels ) location deep autobuffer. This would generate
an interrupt after the all B1 & B2 data of all 8 IOM
channels has been sent/received and we have to process the
content of the autobuffer before the SPORT is accessing
again the autobuffer.
Remember: The buffer occupies only 16 address locations
as we do not want to receive/transmit the monitor &
control data.

The table below illustrates the content of the declared
autobuffer.

IOM2 Addr Autobuffer in DM Memory/16 bits wide

D15 D8 D7

IOM2 Addr Autobuffer in DM Memory/16 bits wide

D15
D0

CH0 x00 0x00 B1 (8 bits)

EE-36 Page 2

Notes on using Analog Devices’ DSP, audio, & video components from the Computer Products Division

Phone: (800) ANALOG-D or [phone], FAX: [phone], EMAIL: [e-mail]