ANALOG DEVICES EE-236 Service Manual

Engineer-to-Engineer Note EE-236

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Technical notes on using Analog Devices DSPs, processors and development tools

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Real-Time Solutions Using Mixed-Signal Front-End Devices with the
Blackfin® Processor

Contributed by Prashant Khullar Rev 1 – May 18, 2004

Introduction

Certain areas of telecommunications
infrastructure are evolving towards the creation
of smaller, localized wireless networks. These
so-called ‘picocells’ can extend wireless
connectivity to areas where terrestrial networks
are not present. The development of this micro­infrastructure brings about the need for compact
devices that can perform some of the tasks
traditionally associated with larger wireless base
stations.

The Blackfin® family of processors can be
gluelessly integrated with a mixed-signal front­end (MxFE) for these and a wide variety of other
real-time applications. The Blackfin
architecture’s signal processing performance,
ease of programmability, and flexible parallel
port make it an ideal candidate for such roles.
Additionally, MxFE devices integrate the
necessary analog front-end functionality onto a
single chip with a programmable architecture.

Hardware Architecture

The AD9866 MxFE is chosen for this discussion.
The 12-bit data converters (A/D and D/A) on the
MxFE connect to the Blackfin’s parallel
peripheral interface (PPI) without any external
logic. The PPI is a half-duplex 16-bit parallel
port which runs at up to half the speed of the
Blackfin system clock (SCLK/2). At the

maximum SCLK frequency of 133 MHz, this
translates to a PPI update rate of 66 MHz. The
MxFE serial interface for control register
configuration connects directly to the Blackfin’s
serial peripheral interface (SPI). Depending on
the application’s bandwidth requirements, a half­duplex or full-duplex implementation can be
used. The former can be accomplished using the
ADSP-BF531/BF532/BF533 line of processors
which have a single PPI.

Full-duplex applications require a dual

!

PPI device such as the ADSP-BF561
symmetric multiprocessor. Such
implementations are not discussed in
this EE-Note.

As shown in Figure 1, the parallel digital
interfaces of the 12-bit ADC and 12-bit DAC
connect directly to the Blackfin PPI. A fixed
number of samples is transferred directly using
DMA from the ADC to a buffer in the
processor’s internal memory. Signal processing
may then be performed on this block of data
before the PPI direction is reversed and the data
is transferred out to the DAC.

General-purpose flag pins are used to alternately
enable and disable the ADC and DAC in a
deterministic fashion. All data transfers are
synchronized by a single clock sourced by an
oscillator running at frequencies up to 60 MHz.

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Figure 1. Hardware Interconnection

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The serial connection between the Blackfin and
AD9866 is used to program the MxFE’s on­board register set. These registers control various
aspects of the device’s operation including power
management, clocking, programmable gain
amplifiers, and interpolation filters.

Software-Controlled Data Flow

To implement such a half-duplex communication
scheme, the PPI and DMA controller on the
Blackfin processor need to reverse their direction
of data transfer at specified intervals. This can be
accomplished in software using a block of
configuration code placed in an interrupt service
routine (ISR). In the tested implementation, a
general-purpose timer was used to generate the
interrupts that trigger this routine at deterministic
intervals. The timer period was chosen
empirically such that the time between
successive interrupts was adequate to ensure that
the ongoing DMA transfer is able to complete
and that the ‘turnaround’ code is also able to
execute to completion.

the main execution flow and the ISR. The delay
involved with reconfiguring the GPIO, DMA,
and PPI register sets constitutes the remainder of
the turn-around time.

The subsequent quantitative analysis of this
dataflow uses the following abbreviations:

N: Number of Samples (Data Window

Size)

CCLK: Blackfin Core Clock Frequency

SCLK: Blackfin System Clock Frequency

DCLK: Data Clock/PPI Clock (synchronizes

MxFE converters and PPI)

RX 0, RX 1: first and second halves of the received

data window, respectively

TX 0, TX 1: first and second halves of the

transmitted data window, respectively

P0, P1: signal processing of first and second

data window halves, respectively

The following benchmarks were obtained
empirically:

The latency associated with the DMA/PPI turn­around code has two components. The first is the
time associated with switching context between

Real-Time Solutions Using Mixed-Signal Front-End Devices with the Blackfin® Processor (EE-236) Page 2 of 5

Context Switch Latency (Using EX_InterruptHandler with
the stack in L1 Data Memory) =
ISR Initialization Latency +