Analog Devices EE205 Application Notes

Engineer To Engineer Note EE-205

Technical Notes on using Analog Devices' DSP components and development tools

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Considerations for Porting Code from the ADSP-TS101S TigerSHARC® Processor to the ADSP-TS201S TigerSHARC Processor

Contributed by Stephen Francis September 3, 2003

Introduction

Memory

System

Memory Acknowledge

SOC Bus - 128 bits data, 32 bits address

CORE

SOC Interface

Extended Core

Interrupt

Vector

Controller

DMA Interrupts

Interrupt

pins

Link Interrupts

developed for the ADSP-TS101S to the ADSPTS201S. The following sections describe the register map changes, the program sequencer, internal memory and cache, Direct Memory Access (DMA) programming, the communications logic unit (CLU), and instruction set changes. This document also includes a section that highlights the differences in the three parts (ADSP-TS201S, ADSPTS202S and ADSP-TS203S) in the new ADSPTS20xS family of embedded processors.

SOC

JTAG

Pins

Cluster

Bus

Interface

Cluster

Interface

Address

Bypass

DMA

External DMA

Requests

Internal

DMA

req

Link

Ports

LVDS Link

Ports

Figure 1: ADSP-TS201S Functional Block Diagram

The ADSP-TS20xS TigerSHARC® processor is the second generation of the TigerSHARC family. The ADSP-TS20xS TigerSHARC processor core is similar to that of the previous TigerSHARC processor and is targeted towards applications similar to the ADSP-TS101S, such as wireless base-stations, image processing, and military applications.

This EE-Note discusses the differences between the ADSP-TS201S and the ADSP-TS101S TigerSHARC processors, and what must be considered when porting code currently

Functional Differences of the ADSP-TS201S and ADSP-TS101S

The ADSP-TS201S operates with up to a 600 MHz core clock, and delivers an aggregate performance of up to 4800 16-bit Million Multiply Accumulates per second (MMACs/sec). In addition to the processor core, ADSP-TS201S includes 24 Mbits of on-chip Dynamic RAM (DRAM) memory; a cluster bus interface, which includes a Synchronous Dynamic RAM (SDRAM) Controller; 4 link channel pairs with Low Voltage Differential Signaling (LVDS) links and 14 DMA channels.

The ADSP-TS201S Functional Block Diagram can be seen in Figure 1. The Processor Block Diagram is divided into two major parts – the Extended Core and the SOC (System on Chip) section. The extended core includes the DSP Core, the Interrupt controller, the SOC Interface, and 24 Mbits of on-chip DRAM. The SOC

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includes the External cluster bus interface, the Link ports, the DMA controller and the JTAG emulation port.

The ADSP-TS201S is a functional variant of the TigerSHARC family, with some enhancements to the previous processor core’s internal units and bus system, memory organization and external link ports. Because the cores of the ADSP-TS201S and ADSP-TS101S processors are functionally identical, they both can execute the same instructions, along with some additional instructions that the ADSP-TS201 can execute, the XCORRS operation for example.

Register Map Changes

Changes in the Extended Core include modifications in the register map. Some of the registers are on the SOC agents and others are in the core. Changes to the register map are highlighted in the following sub-sections, and a summary table (Table 1) of the bit definition register changes is provided at the end of this section. For more details on the register map, please refer to the Memory and Register Map Chapter (Chapter 2) in the ADSP-TS201 TigerSHARC Processor Hardware Reference Manual, and also the defTS201.h system header file that is installed with the TigerSHARC VisualDSP++™ development tools (C:\Program Files\Analog Devices\VisualDSP\TS\include). Note: System Header Files, such as defTS201.h, are used to declare global definitions, especially memory mapped registers, system architecture and processors.

Sequencer register files

Some of the registers that were part of the Sequencer on the ADSP-TS101S now become part of the Interrupt Controller on the ADSPTS201S. A number of the remaining registers in the Sequencer have some bit definition changes, and some new registers, for the operation of the

Flag pins, have been added to the Sequencer on the ADSP-TS201S.

The registers that are moved to the Interrupt Control block are the ILAT (low and high with set and clear addresses), IMASK (low and high), PMASK (low and high), the TIMER (0 and 1, low and high) and TMRIN registers (0 and 1, low and high). The ILAT, IMASK and PMASK registers have the same bit definitions as on the ADSP-TS101S with a few exceptions. The differences can be seen in Figure 2 and Figure 3.

Figure 2: IMASKH, ILATH, PMASKH (Upper) Register Bits on the ADSP-TS101S

Figure 3: IMASKH, ILATH, PMASKH (Upper) Register Bits on the ADSP-TS201S

These changes in the ILAT, IMASK and PMASK registers are only in the ILATH, IMASKH and PMASKH (upper) registers, and so only these sections of the ILAT, IMASK and PMASK registers are shown here. The remainder of the ILAT, IMASK and PMASK registers are unchanged in the ADSP-TS201S.

Considerations for Porting Code from the ADSP-TS101S TigerSHARC® Processor to the ADSP-TS201S TigerSHARC Processor (EE-205) Page 2 of 14

There are a number of bit definition changes in the Sequencer Control (SQCTL) Register on the ADSP-TS201S, compared to the ADSP-TS101S.

Figure 4: SQCTL (Upper) Register Bits on the ADSPTS101S

The Flag bits, located at bits 27-20 in the SQCTL register on the ADSP-TS101S (Figure 4) have been moved to the new FLAGREG register on the ADSP-TS201S (see Figure 10).

Figure 5: SQCTL (Upper) Register Bits on the ADSPTS201S

The Edge/Level interrupt control bits, located at bits 19-16 in the SQCTL register on the ADSPTS101S (Figure 4) have been moved to the interrupt control (INTCTL) register in the Interrupt Controller Block on the ADSP-TS201S,

Figure 11. Bits 27-16 in the SQCTL register are

now reserved on the ADSP-TS201S as can be seen in Figure 5.

The Exception and Global Interrupt Enable bits (IMASK: bits 62 and 60 in the ADSP-TS101S,

Figure 2) have been removed from the IMASK

register and have been added to the SQCTL register on the ADSP-TS201S (bits 3 and 2 respectively in Figure 7). The Emulation bit (IMASK: bit 63 in the ADSP-TS101S, Figure 2) has been removed from the IMASK register and now the EMEN bit in the EMUCTL register includes this functionality.

Figure 7: SQCTL (Lower) Register Bits on the ADSPTS201S

The BTB lock (BTBLK) and BTB enable (BTBEN) bits located at bits 1-0 in the SQCTL register on the ADSP-TS101S (Figure 6) have been moved to the SQSTAT register on the ADSP-TS201S and are controlled by new instructions.

There are a number of bit definition changes in the Sequencer Status (SQSTAT) Register on the ADSP-TS201S, compared to the ADSP-TS101S.

Figure 8: SQSTAT (Upper) Register Bits on the

Figure 6: SQCTL (Lower) Register Bits on the ADSPTS101S

The Timer Control bits, located at bits 13-12 in the SQCTL register on the ADSP-TS101S (Figure 6) have also been moved to the INTCTL

Considerations for Porting Code from the ADSP-TS101S TigerSHARC® Processor to the ADSP-TS201S TigerSHARC Processor (EE-205) Page 3 of 14

ADSP-TS101S

The BTBEN and BTBLK bits, which have been moved from the SQCTL register (Figure 6), are located at bits 28 and 29 respectively in the SQSTAT register on the ADSP-TS201S (Figure

9). BTBEN is set while the BTB is enabled.

When BTBLK is set, every new entry is put into

the BTB with the lock bit set. The Emulation, Exception and HW interrupt bits have been removed from the PMASK register and have been added to the SQSTAT register (bits 22, 21 and 20 respectively) on the ADSP-TS201S (Figure 9).

Figure 9: SQSTAT (Upper) Register Bits on the ADSP-TS201S

New registers have been added to the Sequencer for the operation of the Flag Pins. The Flag (FLAGREG) register, Figure 10, contains the Flag direction and Flag value bits that have been removed from the SQCTL register (bits 27-20 in SQCTL on the ADSP-TS101). The bits to control the direction of the Flag pins (3-0) are located at bits 3-0 respectively. The Flag value bits for the Flag pins (3-0) are located at bits 7-4 respectively. Note: the FLGx bits do not change location and are located in the SQSTAT register on both the ADSP-TS101S and the ADSPTS201S. The FLAGREGST register is used to set a bit in FLAGREG, while the FLAGREGCL register is used to clear a bit in FLAGREG.

Figure 10: FLAGREG (Lower) Register Bits on the ADSP-TS201S

addresses), IMASK (low and high), PMASK (low and high), the TIMER (0 and 1, low and high), and TMRIN registers (0 and 1, low and high).

The bit definitions of the ILATL, IMASKL and PMASKL registers do not change in the ADSPTS201S relative to the ADSP-TS101S, while bit definitions of the ILATH, IMASKH and PMASKH registers are identical to the ADSPTS101S, except for the bits that have been moved to the SQCTL and SQSTAT registers (Bits 31:28), as described previously.

The ILATSTL register is used to set a bit in ILATL, while the ILATCLL register is used to clear a bit in ILATL. Likewise, The ILATSTH register is used to set a bit in ILATH, while the ILATCLH register is used to clear a bit in ILATH.

Figure 11: INTCTL (Lower) Register Bits on the ADSP-TS201S

The INTCTL register, Figure 11, on the ADSPTS201S contains the Edge/Level interrupt control bits and the Timer Control bits, which have been moved from the SQCTL register, as described previously. The Edge/Level interrupt control bits for IRQ3-0 are located at bits 3-0 respectively. The Timer Control bits, TMR1RN and TMR0RN, are located at bits 5-4 respectively. The remainder of the INTCTL register is reserved.

Interrupt Control Registers

The Interrupt Controller register block on the ADSP-TS201S includes a number of registers that have been moved from the Sequencer on the ADSP-TS101. The registers that have been moved to the Interrupt Control block are the ILAT (low and high with set and clear

Considerations for Porting Code from the ADSP-TS101S TigerSHARC® Processor to the ADSP-TS201S TigerSHARC Processor (EE-205) Page 4 of 14

External Interface Registers

There are changes in the Link port registers relative to the ADSP-TS101S. The link ports on the ADSP-TS201S are similar to those on the ADSP-TS101S in the way they are accessed by the core and the DMA, but different in their physical implementation. Figure 12 and Figure

13 highlight the differences in the basic link port

configuration. Note, the link ports on the ADSPTS201S are not compatible with previous TigerSHARC processor or SHARC DSP link ports.

Figure 12: ADSP-TS101S Minimal Link Port Configuration – No Buffering

The ADSP-TS201S’s four full-duplex link ports each provide additional four-bit receive and fourbit transmit I/O capability, using Low-Voltage, Differential-Signal (LVDS) technology. With the ability to operate at a double data rate—latching data on both the rising and falling edges of the clock – running at 500 MHz, each link port can support up to 500M bytes per second per direction, for a combined maximum throughput of 4G bytes per second.

defined on the ADSP-TS101S. Additional registers are added to reflect the additional receive and transmit capability of the link ports, ie., the link receive and link transmit control registers (LRCTLx, LTCTLx) the link receive status and receive status clear registers (LRSTATx, LRSTATCx), and the transmit status and transmit status clear registers (LTSTATx, LTSTATCx). Please refer to the defts201.h header file for the bit definitions for the above link port registers.

Bit Function Register Changes Summary

The following table (Table 1) gives a summary of the bit definitions that change registers from the ADSP-TS101S to the ADSP-TS201S.

FUNCTION ADSP-TS101S

(BIT Locations)

FLAGx_OUT SQCTL – (27-24) FLAGREG – (7-4)

FLAGx_EN SQCTL – (23-20) FLAGREG – (3-0)

IRQx_EDGE SQCTL – (19-16) INTCTL – (3-0)

TMRxRN SQCTL – (13-12) INTCTL – (5-4)

ADSP-TS201S Register

(BIT Locations)

BTBLK SQCTL – (1) SQSTAT – (29)

BTBEN SQCTL – (0) SQSTAT – (28)

Figure 13: ADSP-TS201S Minimal Link Port Configuration – No termination indicated

Additional pins are provided for the Link ports on the ADSP-TS201S, as can be seen in Figure

13. For the hardware connection guidelines for

the links ports on the ADSP-TS201S, please refer to EE-179 - ADSP-TS201S Hardware System Design Guidelines.

The link buffer registers, LBUFTXx, LBUFRXx,

EMUL (IMASK)

EXCEPT (IMASK)

GIE (IMASK) IMASKH – (60) SQCTL – (2)

EMUL (PMASK)

EXCEPT (PMASK)

GIE (PMASK) PMASKH – (60) SQSTAT – (20)

Table 1: Summary of bit definition register changes.

IMASKH – (63) EMEN bit in

EMUCTL includes this functionality

IMASKH – (62) SQCTL – (3)

PMASKH – (63) SQSTAT – (22)

PMASKH – (62) SQSTAT – (21)

(“x” stands for channel number 3:0) are as

Considerations for Porting Code from the ADSP-TS101S TigerSHARC® Processor to the ADSP-TS201S TigerSHARC Processor (EE-205) Page 5 of 14

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