Analog Devices EE189 Application Notes

Engineer To Engineer Note EE-189

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Technical Notes on using Analog Devices' DSP components and development tools

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Link port tips & tricks for ADSP-2106x & ADSP-2116x SHARC® DSPs

Contributed by R. Murphy October 27, 2003

Introduction

Some members of the SHARC® DSP family
have Link Ports that enable point-to-point
communication between DSPs. This EE-note is
intended to supplement the existing
documentation and facilitate debugging Link
Port systems. In this EE-note we will briefly
cover the basics of using link ports, provide
some tips on link port operation across the
SHARC DSP family, and discuss the anomalies
associated with some of the Link Port
functionality.

• Suitable for long distance transfers

Sending the data along with the LACK (Link
Acknowledge) signal as well as the ability for
LACK to hold off further words lends itself to
long trace-length usage.

• Link Port Booting

The ability to boot the DSP via the link port
can further free up the external bus and allows
for complex booting schemes in which many
DSPs can be booted in sequence via link
ports, even with unique application code for
each DSP.

Why Use Link Ports?

The Basics

• Point-to-Point Inter-processor Communication

Use the Link Ports to transfer data amongst
the DSPs in the cluster, freeing up the external
port for other accesses.

• Flexible, efficient data control

Link Ports can use the core or the zero­overhead DMA controller to transfer data to /
from the DSP for efficient data I/O.

• Bi-directional communication on a single link

The Link Ports are bi-directional, so a routine
can easily switch the direction of the transfer.

• Multiple simultaneous transfers

The Link Ports allow the DSP to
communicate with other DSPs simultaneously
saving time and board layout.

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Link Ports Availability by DSP

ADSP-21060 & ADSP-21062:

6 Link ports, 4 bits wide, 1x or 2x core clock

ADSP-21160:

6 Link ports, 8 bits wide, up to 95* MHz

ADSP-21161:

2 Link ports, 8 bits wide, up to 100 MHz

*ADSP-21160M = 80MHZ, ADSP-21160N = 95MHz

The ADSP-2106x and ADSP-2116x Link Ports

!

are logically but not electrically compatible.
Please see EE-160 on www.analog.com/sharc
for more information on using these peripherals
together.

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Link Port Buffers:

These are Memory Mapped two location deep
FIFOs with support for either 32 or 48 bit words.
The user has the flexibility to assign any link

Transmitter Receiver

LDATx

Each

Link
Port

LCLKx LCLKx

LACKx LACKx

SHARC

Figure 1 .Link Port Connections 21xxx DSPs

4/8

port to any link buffer, and each link buffer has a
dedicated DMA channel. In order to prevent lost
data, a read of an empty buffer or a write to a full
buffer results in core hang.

LDATx

Each

Link
Port

SHARC

Figure 1 displays the connection of the link port
signals. The data path is 4 bits wide on the
ADSP-2106x DSPs, and configurable for either 4
or 8 bits wide on the ADSP-2116x DSPs. The
LDATx and LCKx signals are driven by the

transmitter. LACKx is driven by the receiver.
Data is driven on the rising edge of LCLKx and
sampled on the falling edge. The receiver will
deassert the LACKx signal to hold off the
transfer if it’s link buffer is full.

Figure 2.Link Port Communication Examples

Link port tips & tricks for ADSP-2106x & ADSP-2116x SHARC® DSPs (EE-189) Page 2 of 6