Analog Devices EE183v04 Application Notes

Engineer-to-Engineer Note EE-183

a

Technical notes on using Analog Devices DSPs, processors and development tools

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Rational Sample Rate Conversion with Blackfin® Processors

Contributed by Jeff Sondermeyer, Senior DSP FAE Rev 4 – March 18, 2004

Introduction

The process of converting the sampling rate of a signal

from one rate to another is called sampling rate conversion

(or SRC). This technique is encountered in many
application areas such as:

• Digital Audio (the focus of this paper)

• Communications systems

• Speech Processing

• Antenna Systems

• Radar Systems

Sampling rates may be changed upward or downward.
Increasing the sampling rate is called interpolation, and
decreasing the sampling rate is called decimation.

Reducing the sampling rate by a factor of M is achieved by
discarding every M-1 samples, or, equivalently keeping
every M’th sample. Increasing the sampling rate by a
factor of L (interpolation by factor L) is achieved by
inserting L-1 zeros into the output stream after every

sample from the input stream of samples.

This system can perform SRC for the following cases:

reduction of the sampling rate and interpolation is the
increasing of the sample rate.

Decimation

A reduction of sample rate (decimation) by a factor of M is
achieved by sequentially discarding M-1 samples and
retaining every M’th sample. While discarding M-1 of
every M input samples reduces the original sample rate by
a factor of M, it also causes input frequencies above one-

half the decimated sample rate to be aliased into the
frequency band from DC to the decimated Nyquist
frequency. To mitigate this effect, the input signal must be
lowpass filtered to remove frequency components from
portions of the output spectrum which are required to be
alias free in subsequent signal processing steps. A benefit
of the decimation process is that the lowpass filter may be
designed to operate at the decimated sample rate, rather
than the faster input sample rate, by using a FIR filter
structure, and by noting that the output samples associated

with the M-1 discarded samples need not be computed.

• Decimation by a factor of M

• Interpolation by a factor of L

• SRC by a rational factor of L/M.

SRC by L/M requires performing an interpolation to a
sampling rate which is divisible by both L and M. The final
output is then achieved by decimating by a factor of M.

Appropriate lowpass filtering is required to prevent both
imaging and aliasing. This system employs the polyphase,
multistage technique in the process of the sampling rate
conversion for computational savings.

1.1 Sample Rate Conversion Designs

SRC designs use the basic properties of decimation and
interpolation to change sampling rates. Decimation is the

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Interpolation

An increase in sample rate (interpolation) by a factor of L
is achieved by inserting L-1 uniformly spaced, zero value
samples between each input sample. While adding L-1 new

samples between each input sample increases the sample

rate by a factor of L, it also introduces images of the input

spectrum into the interpolated output spectrum at
frequencies between the original Nyquist frequency and
the higher interpolated Nyquist frequency. To mitigate this
effect, the interpolated signal must be lowpass filtered to
remove any image frequencies which will disturb
subsequent signal processing steps. A benefit of the
interpolation process is that the lowpass filter may be
designed to operate at the input sample rate, rather than the
faster output sample rate, by using a FIR filter structure,

and by noting that the inputs associated with the L-1

inserted samples have zero values.

a

Sample rate changes using both interpolation and decimation

When the specified SRC factor is not an integer factor,
SRC design uses interpolation to increase the sample rate
to a rate which is divisible by both the input and final
output sample rates. This interpolation is then followed by
decimation to achieve the specified output rate. Note that
the output sample rate may be faster or slower than the
original input rate. In cases where both interpolation and
decimation are performed in tandem it is possible to
combine the anti-imaging filter of the interpolator and the
anti-aliasing filter of the decimator into a single filter
which satisfies both requirements. The filters which run at
the low data rate are actually implemented as a particular
structure known as a polyphase filter, which will be
discussed shortly.

1.2 Decimation

If the sampling rate is decreased by a factor M, in order to

avoid aliasing, a lowpass filter is needed with the specific
restrictions that the ratio of the half sample frequency to

the passband frequency must be less than or equal to M.

Let x(m) be the input signal, h(k), 0 <= k < K, be the
coefficients of a given lowpass filter and z(m) be the

output signal before decimating by a factor M, then:

K

−

kmxkh

z(m) = (1)

Now let the output signal after the decimator be y(r) =

z(rM) where the sampling rate is reduced by a factor M.

Clearly, y(r) = z(rM) if the output signal is decimated by a
factor M.

y(r) =

Looking carefully at this equation, one can see that the
filter is in effect using the downsampled signal. Thus the
operations of downsampling and lowpass filtering have

∑

k

K

∑

=

k

=

0

0

)()(

−

krMxkh

)()(

(2)

been embedded in such a way that the lowpass filter is
operating at the reduced data rate and the average number
of computations to generate one output sample is reduced

by M.

1.3 Interpolation

Given an incoming sample rate of F

factor of L, then the resulting output sampling frequency is

= L*F

F

out

output signal is required such that the cutoff frequency is

/2.

F

in

Let x(n) be the original input sequence, v(n) the sequence

with L-1 zeros inserted, y(n) the output sequence of the

lowpass filter and let h(0), ..., h(K-1) be the coefficients of
the lowpass filter, then:

y(n) = (3)

However, v(n-k) = 0 unless n-k is a multiple of L, since L­1 zeros were inserted in the sequence x(n) to get v(n).

Again let x(n) be the input signals, and h(k) be the filter
coefficients. Then the output signal y(r) has a simple
formula:

y(r) = (4)

The average number of computations during one sampling
time is reduced by L, the interpolation factor.

. To prevent imaging, a lowpass filter on the

in

K

−

knvkh

∑

=

k

∑

=

n

0

LK

/

−

0

)()(

nxLnrh

)()(

and an interpolation

in

1.4 Sample Rate Conversion by Rational Factor L/M

To perform sample rate conversion by a rational factor

L/M, the incoming signal is first interpolated by a factor M.

The interpolation must be performed first to preserve the
spectral content of the signal. Graphically, this process can
be represented by the following diagram:

x(n)

Sampling rate

Fx

Figure 1. Block Diagram of a Rational SRC

Rational Sample Rate Conversion with Blackfin® Processors (EE-183) Page 2 of 26

Up Sampler

by L

Anti-imaging

lowpass filter

sample rate LFx

Anti-Aliasing

lowpass filter

Down

Sampler

by M

y(m)

Sampling rate

(L/M)Fx

a

The anti-aliasing and anti-imaging lowpass filters can be
combined into a single low-pass filter.

1.5 Polyphase Filters

Polyphase filters are used to implement multirate filters.
The polyphase filters for interpolation-only and
decimation-only filters have a simpler structure than the
polyphase filter used between an interpolator and a
decimator.

1.5.1 Interpolator-Only Polyphase Filters

The computational efficiency of the Interpolator filter
structure can also be achieved by reducing the large FIR
filter of length K into a set of smaller filters. These smaller
filters will have a length N = K/L, where K is selected to
be a multiple of L. Since the interpolation process inserts L

- 1 zeros between successive values of x(n), only N out of
the K input values stored in the FIR filter at any one time
are nonzero. At one time instant, these nonzero values
coincide and are multiplied by the filter coefficients
h(0),h(L), h(2L),...,h(K - L). In the following instant, the
nonzero values of the input sequence coincide and are
multiplied by the filter coefficients h(1), h(L + 1), h(2L +

1),...h(K - L + 1), and so on. This observation leads us to
define a set of smaller filters called polyphase filters, with
unit sample responses:

pk (n)=h(k+nL) k = 0,1,...,L – 1
n = 0,1,...,N – 1 (5)
where N = K/L is an integer.

Additional insight can be gained about the characteristics
of the set of polyphase subfilters by noting that p
obtained from h(n) by decimation with a factor L.
Consequently, if the original filter frequency response
H(w) is flat over the range each of the polyphase subfilters
will possess a relatively flat response over the range (i.e.
the polyphase subfilters are basically allpass filters and
differ primarily in their phase characteristics). This
explains the reason for the term “polyphase” in describing
these filters. The polyphase filter can also be viewed as a
set of L subfilters connected to a common delay line.
Ideally, the kth subfilter will generate a forward time shift
of (k/L)F
subfilter. Therefore, if the zeroth filter generates zero
delay, the frequency response of the kth subfilter is:

pk(w) =e

in, for k = 0, 1 2,..., L - 1, relative to the zeroth

k

L

jw

(6)

(n) is

k

1.5.2 Decimator-Only Polyphase Filters

By transposing the interpolator structure we obtain a
commutator structure for a decimator that is based on the
parallel bank of polyphase filters. The unit sample
responses of the polyphase filter are now defined as:

pk(n) = h(k+nM) k = 0,1,...,M - 1

n = 0,1,...,N – 1 (7)

where N = K/M is an integer when K is selected to be a
multiple of M. The commutator rotates in a counter­clockwise direction starting with filter p

1.5.3 Simultaneous Interpolator and Decimator
Polyphase Filter

A Polyphase filter which is used to perform lowpass
filtering between an interpolator and decimator function is
more complicated than the structures previously discussed
for either the Decimator-Only or Interpolator-Only phases.
In the Interpolator-Only case, one input leads to several
outputs, and in the Decimator-Only case, many inputs lead
to a single output. Thus, there is a relatively simple
relationship between the polyphase subfilters and h(n), the
lowpass filter coefficients. An interpolator of L samples
followed by a decimator of M samples means that L input
values must lead to M output values.

y(m) is the output of the polyphase filter

g(n,m) is the polyphase filter coefficients

h(n) is the lowpass filter used for both anti­imaging of the interpolator and anti-aliasing of the
decimator

(n).

0

[x] denotes the largest integer in x (8)

mM

g(n,m) = h(nL +mM - [

]* l)

L

n=0,…,N-1 and m=0,…,L-1 (9)

y(m) =

−=10N

∑

n

g(n,m-[

M

] L) x([•

L

mM

L

]-n)

where K is the filter length of h(n) and L|K
with N = K/L, m=0,…,L-1 (10)

In a multistage implementation, this type of polyphase
filter is used between the interpolator and the decimator
stage. All other stages are either simple decimation or

Rational Sample Rate Conversion with Blackfin® Processors (EE-183) Page 3 of 26

a

interpolation stages. The polyphase filters are exactly those
described in Section1.5.1 and Section1.5.2. An excellent
discussion of this topic is available in Chapter 10 of

Digital Signal Processing by Proakis and Manolakis.

1.6 Polyphase, Multistage Filter Design

Given an input sampling frequency F
output sampling frequency F
frequency F
of both F

is the Least Common Multiplier (or LCM)

min

and F

in

. The decimator of the sample rate

out

conversion is defined as D = F
is defined as U = F

/ F

min

(integer), then the smallest

out

min

. The number of primes in the

in

decimator is the maximum number of stages in the
decimation structure design. If the decimator is 24= 2 * 2 *
2 * 3, then the maximum number of stages is 4. Likewise,
the number of primes in the interpolator is the maximum
number of stages in the interpolation structure design. Thus
it is possible to have a different optimum multirate
structure for a multistage decimation structure as opposed
to a multistage interpolation structure.

If you choose M = D, L = U, then you are in a design of a
SRC system (U/D), but you can also choose M = RD, and
L = RU to get an equivalent system (RU/RM) for any
positive integer R. The user can choose R = 1, 2, 4,...

A design of a SRC requires the selection of a structure:

decimation or interpolation, over-sample rate R = 1, 2,

4,…, number of stages, a factor for each stage, and a
lowpass filter for each stage. The product of all the stage
factors should be equal to the decimator if a decimation
structure is selected or interpolator if an interpolation

structure is selected, times the over-sample rate R.

Momentum Data Systems (MDS) has developed a program
to create and optimize SRC structures and generate

coefficients: Advanced QED Series Sample Rate

Conversion System (Windows 95/NT Version only) Version

www.mds.com). This program has two methods for

2.2. (

best design of decimation and interpolation structures:
minimizing the sum of filter lengths, and minimizing the
number of computations of the signal filtering. The number
of computations is calculated as follows:

If U1, U2 and U3 are up-sample factors for a 3-stage
interpolation structure, and L1, L2 and L3 are the filter

lengths for 3-stages respectively, then the number of
computations is

L1 + L2 * U1 + L3 * U1 * U2, or equivalent L3/U3 +
L2/(U2*U3) + L1/(U1*U2*U3)

If D1, D2 and D3 are down-sample factors for a 3-stage

decimation structure, then the number of computations is

(integer) and an

in

/ F

and the interpolator

out

L3 + L2 * D3 + L1 * D3 * D2, or equivalent L1/D1 +
L2/(D1*D2) + L3/(D1*D2*D3)

This design problem is not a single-objective optimization
problem. The number of computations, the number of filter
taps and the complexity of the multi-structure enter in the
calculations. The problem becomes particularly
complicated if the number of stages is greater than 3.

This EE-Note used the QED Series Sample Rate
Conversion System to determine the optimum SRC

structures and all coefficients.

1.7 SRC Code Overview

The work described in this EE-Note was based on the

principles discussed in Section 1.1 through Section 1.6.

From this, a polyphase multistage SRC was implemented
on the ADSP-BF535 Blackfin® Processor.

A zip file (SRC.zip) containing the VisualDSP++™ 3.1

projects discussed here can be obtained from Analog
Devices (
imported into later versions of VisualDSP++. The Default

C Linker Description File (*.ldf) for the latest version of

VisualDSP++ should be used to recompile/relink these

projects. Make sure BUFIN is defined in the assembly
options (see Section 1.7.3). The SRC and main program C
shell (SRC.c) were developed using the ADSP-BF535 EZ-

KIT Lite™ Evaluation Platform. The C shell contains
function calls and routines to initialize the state of the
ADSP-BF535 as well as the SRC. Since this code does not
use any DMA capabilities or peripherals, this ‘core’ code
should port directly to next generation ADSP-BF5xx
Blackfin Processors. All code for this project is listed in

the Appendix.

The following were the design objectives used in
developing the SRC functions:

• The optimized assembly routines are to be C callable

• All input and output data should be 16 bits.

• All intermediate calculations should be 32-bit double-

• All filter coefficients should be 32-bit.

• All filters were designed for audio applications with

0.2dB passband ripple
58dB stopband ripple

• The MIPS budget should be ≤ 2 MIPS for all SRC

www.analog.com). These files can be easily

(See src_init.asm and src_flt.asm in the Appendix).

precision (maintaining 31.5 bits of precision per MAC).

these criteria:

examples.

Rational Sample Rate Conversion with Blackfin® Processors (EE-183) Page 4 of 26

The program assumes input data comes from a 16-bit

buffer (initialized as ‘x’ in the shell). This data is copied
into a 32-bit buffer ‘in1’ within src_flt.asm. At the end of
src_flt.asm, the last 32-bit buffer ‘inx’ (where ‘x’ is the last
stage) is copied into a 16-bit buffer (‘y’ in the shell). These

16-bit input/output buffers can be eliminated to conserve
data space. In this case, you will need to undefine

‘BUFIN’ and preload 'in1' with 32-bit data and then use
the 32-bit output data from ‘inx’.

The filters were designed to convert between selected
standard audio sample rates (Hz): 48000, 44100, 32000,

22050, 16000, 11025, and 8000. See Figure 1 for the audio
SRC matrix. Note that an ‘x’ in the matrix denotes that the
SRC filter was designed and is included in SRC.zip. If you

have the SRC program from MDS (or similar) you can

generate coefficients for any SRC. See Section 1.7.2

below.

Figure 3. ‘x’ Input Data for 44.1KHz sampling of a
250Hz sine wave.

a

Figure 2. Audio SRC Matrix

The #2 workspace in this project has all the necessary plots
of the input/output stages as well as the intermediate
buffers. You can look at the data in the time domain or
apply the VisualDSP++ built-in FFT plotting function to
analyze the frequency domain. Load

‘plots_xxxxtoxxxx.vdw’ for a particular SRC.
A ‘SINE_xxxxx_16bit_1024.dat’ input file was generated

to test every SRC. This is a 16-bit, 1024-sample, 1KHz or
250Hz sine wave at the input sample rate. These input files
were generated using MATLAB® scripts (see

‘gen_sine_wave_comma_16.m’). It's easy to verify proper

SRC functionality by counting samples in one period at

both the input rate (in the ‘x’ plot) and the output rate (in
the ‘y’ plot) in workspace #2. See Figure 2 and Figure 3.

Figure 4. 'y' Output Data for 48KHz SRC of a
250Hz sine wave

The built-in FFT plotting functions were also used to

analyze input and output data. See Figure 4 and Figure 5.

Rational Sample Rate Conversion with Blackfin® Processors (EE-183) Page 5 of 26

Figure 5. FFT of 'x' Input Data at 250Hz

Figure 6. FFT of 'y' Output Data at 250Hz

1.7.1 Input/Output Data Sizes and the GCD

The size of NINPS and NOUTS can be modified in each
‘src_xxxxtoxxxx.h’ file (see example of src_441to48.h in
the Appendix). This will allow the user to vary the size of

the input/output buffers according to system block
processing needs. It was envisioned that the end
application would be operating on blocks of audio samples.
Note that the smallest block size can be no less than the

LCM discussed in Section 1.6. However, an integer

multiple of the LCM can be applied to increase the

a

processed block size. The user can increase or decrease the
integer multiple of the LCM (or Greatest Common

Denominator, GCD, in Table 2) by changing the buffer
sizes NINPS and NOUTS. These two numbers must be at

least half of the greatest filter coefficient count times the

INTPx to ensure valid output data. Table 1 was generated

from a simple C program:

GCD=48000, Original=48000/48000, NEW=1/1
GCD=300, Original=48000/44100, NEW=160/147
GCD=16000, Original=48000/32000, NEW=3/2
GCD=150, Original=48000/22050, NEW=320/147
GCD=16000, Original=48000/16000, NEW=3/1
GCD=75, Original=48000/11025, NEW=640/147
GCD=8000, Original=48000/8000, NEW=6/1
GCD=300, Original=44100/48000, NEW=147/160
GCD=44100, Original=44100/44100, NEW=1/1
GCD=100, Original=44100/32000, NEW=441/320
GCD=22050, Original=44100/22050, NEW=2/1
GCD=100, Original=44100/16000, NEW=441/160
GCD=11025, Original=44100/11025, NEW=4/1
GCD=100, Original=44100/8000, NEW=441/80
GCD=16000, Original=32000/48000, NEW=2/3
GCD=100, Original=32000/44100, NEW=320/441
GCD=32000, Original=32000/32000, NEW=1/1
GCD=50, Original=32000/22050, NEW=640/441
GCD=16000, Original=32000/16000, NEW=2/1
GCD=25, Original=32000/11025, NEW=1280/441
GCD=8000, Original=32000/8000, NEW=4/1
GCD=150, Original=22050/48000, NEW=147/320
GCD=22050, Original=22050/44100, NEW=1/2
GCD=50, Original=22050/32000, NEW=441/640
GCD=22050, Original=22050/22050, NEW=1/1
GCD=50, Original=22050/16000, NEW=441/320
GCD=11025, Original=22050/11025, NEW=2/1
GCD=50, Original=22050/8000, NEW=441/160
GCD=16000, Original=16000/48000, NEW=1/3
GCD=100, Original=16000/44100, NEW=160/441
GCD=16000, Original=16000/32000, NEW=1/2
GCD=50, Original=16000/22050, NEW=320/441
GCD=16000, Original=16000/16000, NEW=1/1
GCD=25, Original=16000/11025, NEW=640/441
GCD=8000, Original=16000/8000, NEW=2/1
GCD=75, Original=11025/48000, NEW=147/640
GCD=11025, Original=11025/44100, NEW=1/4
GCD=25, Original=11025/32000, NEW=441/1280
GCD=11025, Original=11025/22050, NEW=1/2
GCD=25, Original=11025/16000, NEW=441/640
GCD=11025, Original=11025/11025, NEW=1/1
GCD=25, Original=11025/8000, NEW=441/320
GCD=8000, Original=8000/48000, NEW=1/6
GCD=100, Original=8000/44100, NEW=80/441
GCD=8000, Original=8000/32000, NEW=1/4
GCD=50, Original=8000/22050, NEW=160/441
GCD=8000, Original=8000/16000, NEW=1/2
GCD=25, Original=8000/11025, NEW=320/441
GCD=8000, Original=8000/8000, NEW=1/1

Table 1. Greatest Common Denominator for Audio SRC

Rational Sample Rate Conversion with Blackfin® Processors (EE-183) Page 6 of 26

a

1.7.2 Coefficient Generation and Formatting

Assuming a program that is similar to the MDS tool is
used, some data formatting must be performed. The
following must be done to convert the raw decimal filter

coefficients. With MDS, a *.dsp file is produced. Table 2
is an example of the MDS data format for the *.dsp file.

This file must be properly formatted as a 32-bit

hexadecimal VisualDSP++ input data file (*.dat). This is

then read (by VisualDSP++) into the corresponding
variable at initialization:

a. Use Microsoft Excel to import the *.dsp file (space

delimited). Select the "D" column and erase everything
but the decimal filter coefficients. Save the file as a

‘Formatted Text (Space Delimited)(*.prn)’ file.

/* External References */
.external src_init;
.external src_flt;

#define STAGE 3 /* Number of stages */
#define INTP0 160 /* Interpolation factor */
#define DOWN0 147 /* Decimation factor */

/* ------------------------------------------------------------ */

/* parameters for each stage */
#define INTP1 2
#define DOWN1 1
#define LENG1 223
#define PLEN1 112
#define MLEN1 224
#define SHFT1 0
#define NINP1 147
#define SZIN1 512

#define INTP2 5
#define DOWN 2 1
#define LENG2 27
#define PLEN2 6
#define MLEN2 30
#define SHFT2 0
#define NINP2 94
#define SZIN2 512

#define INTP3 16
#define DOWN3 147
#define LENG3 49
#define PLEN3 4
#define MLEN3 64
#define SHFT3 0
#define NINP3 1470
#define SZIN3 2048

#define NINP4 160
#define SZIN4 256

/* ------------------------------------------------------------------------ */

.VAR/DM flt1[MLEN1];
.INIT flt1:
0xffc8, /* -1.72471041e-003 cf 000 pp 000 ft 1 */
0xfffe, /* -8.01035724e-005 cf 002 pp 000 ft 1 */
0x000f, /* 4.65568547e-004 cf 004 pp 000 ft 1 */

0xfffa, /* -2.00361260e-004 cf 006 pp 000 ft 1 */
0x000c, /* 3.90279025e-004 cf 008 pp 000 ft 1 */
0xfff2, /* -4.43292360e-004 cf 010 pp 000 ft 1 */
0x0013, /* 6.04802800e-004 cf 012 pp 000 ft 1 */
0xffe8, /* -7.54936936e-004 cf 014 pp 000 ft 1 */
0x001e, /* 9.43581218e-004 cf 016 pp 000 ft 1 */
., . . .
., . . .
., . . .

Listing 1. Coefficient Format from MDS

b. Use the included MATLAB® script ‘dec_file_to­_hex_file_converter.m’. This script will read in decimal

(exponential) data from the *.prn file and convert to a
32-bit Hexadecimal format (*.dat file) suitable to be read

by VisualDSP++ within a data initialization section. This
MATLAB® script can be easily modified for other
formats.

1.7.3 BUFIN Define

When ‘BUFIN’ is undefined (under VisualDSP++:
PROJECT OPTIONS / ASSEMBLER / ADDITIONAL
OPTIONS: ‘-D BUFIN’), the SRC program assumes that
buffer ‘in1’ is preloaded with 32-bit input data AFTER the
src_init is accomplished (buffer zeroing). This requires that

the shell program preload ‘in1’ from a 32-bit source.
Define ‘BUFIN’ to include the 16-bit buffer transfer code
within src_flt.asm. ‘x’ and ‘y’ 16-bit input buffers are not

necessary for a final application but they do allow for
easier data manipulation for test purposes.

1.7.4 Zeroing Filter Delays

To "zero" out filter delays, use the following equations as
offsets to first valid output data:

1st Offset = (LENG1-1)/(2*DOWN1)
2nd Offset = INTP2/DOWN2*1st Offset + (LENG2-1)/(2*DOWN2)
3rd Offset = INTP3/DOWN3*2nd Offset + (LENG3-1)/(2*DOWN3)

See the constants generated in the 'src_xxxxtoxxxx.h’ files.
DOFSx is actually the offset from the end of the buffer.

Therefore it is the number of valid output data samples.
This will determine how often this routine needs to be
executed in a block processed system. Be careful with this
number. The preprocessor in VisualDSP++ will not
generate fractional constants. Therefore, depending on the

math here, DOFSx could have an error of ±1 sample. For a
particular SRC, check the first sample in ‘y’ and adjust the
DOFSx accordingly.

Rational Sample Rate Conversion with Blackfin® Processors (EE-183) Page 7 of 26

a

1.7.5 Reducing Intermediate Buffers

One idea to reduce the number of intermediate buffers is to

implement a ‘zero_buf’ function (not included) that would

re-zero the buffers between filter sections. This would
reduce the number of intermediate buffers to two at the
expense of more MIPS to accomplish the SRC. However,
the MIPS increase would be negligible and is on the order
of the size of the buffer times the number of times it is
zeroed. These two intermediate buffers should be sized to
the maximum needed for any SRC.

1.7.6 Restrictions

If there is a large interpolation constant INTPx, this

severely reduces the number of valid data samples in the
final output buffer. For example, in the 44.1K to 48K SRC,
there is an interpolation constant of 16 in the 3rd stage. If
we only use L1 data sections (max = 4096 bytes) we only
get 111 valid data samples in the final output buffer.
However, if we can use L2 (like what is available in the
ADSP-BF535) and make this intermediate buffer as large
as 4096 words (16K bytes), we can get a relatively large
number of valid output data samples. Depending on
interpolation constants and the need to run out of single
cycle L1 memory, the limiting factor appears to be the L1
section size. We can maximize all the filters based on this
L1 section size (4096 bytes or 1024 32-bit words) or
assume we can use L2 (internal or external) and make the
intermediate buffers larger. In the latter case, the number
of valid output data samples greatly increases.

1.7.7 Unresolved Issues

The following SRCs produced corrupted output data when
using a 3-stage interpolator structure:

passband ripple = 0.0001 and a stopband ripple = 98dB.
This provided a overall SNR of 90dB through all 3 stages

of the filter. This was tested using Cooledit 2000 software.

If a lesser system SNR is desirable (50-70dB), a 32-bit
implementation will provide a SNR that is close to the
stopband attenuation. For higher system SNR's (above
90dB), much higher stopband attenuations are required.

Conclusions

The code and filters in this EE-Note were generated
specifically with audio SRC in mind. Notwithstanding, by
generating new filter input files with tighter passband and
stopband ripple, this code could be used unaltered for
many different applications. Keep in mind that we gained
computational efficiency by eliminating the LxL multiply
and thus only retaining 31.5 bits of precision for each
Multiply And Accumulate (MAC). This amount of
precision is more than enough for most applications.

Notice in src_flt.asm that the inner MAC loops are only 2

cycles, enabling double precision math with very little
overhead. This “low cycle” double precision capability of
Blackfin™ is one of the great advantages of this
architecture over competing single MAC architectures.

Placement of data and code sections (i.e. L1, internal or
external L2) is up to the user. However, coefficients and
data should be placed in separate banks to avoid stalls
(only applies to L1). Also, whether cache or SRAM is used
will greatly impact the overall cycle counts. Since there are
many filters required for all the various audio SRC
combinations, it was assumed that coefficients would be
placed in a larger external L2 SRAM or SDRAM. These
coefficients could either be cached internally or brought
into L1/L2 via DMA concurrent to block processing.

11025to16,
16to2204, and
8to11025

Therefore, a 2-stage filter decimator structure was used
instead and produced valid results. It appears that the MDS
filter generator produced corrupted 3rd stage outputs for all
SRCs that up-converted between two similar rates. The
MDS program chose by default a 3-stage interpolator
structure in each of these cases.

1.7.8 Case Study of Total SNR

Two common SRC changes are 44.1KHz to 48KHz and
48KHz to 44.1KHz. Instead of using the stopband and
passband ripples above, a filter was generated with

Rational Sample Rate Conversion with Blackfin® Processors (EE-183) Page 8 of 26

Recommendations for Further Development

The code developed in this EE-Note can be applied to any
application requiring SRC. For example, many video
applications require the ability to scale images to change
the video size (D1 to CIF, etc.). This Polyphase multistage
SRC approach could be modified to work on byte-wide
single precision video data. The basic structure of this code
would not require many alterations. Instead of working on
one time-domain double-precision data sample per cycle,
the SRC would be modified to operate on two byte-wide
frequency-domain data samples per cycle.

Finally, the code has not been completely optimized.
Improvements can be made to reduce overall cycles
particularly the elimination of pipeline stalls.