Analog Devices EE176v03 Application Notes

Engineer-to-Engineer Note EE-176

a

Technical notes on using Analog Devices DSPs, processors and development tools

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Hardware Design Checklist for ADSP-TS101S TigerSHARC® Processors

Contributed by Eric Yang Rev 3 – July 6, 2004

Introduction

This EE-Note discusses specific hardware issues when implementing a system design that incorporates
ADSP-TS101S TigerSHARC® processors. This document is provided as an aid to hardware engineers
when designing systems.

All items provided in this EE-Note apply to ADSP-TS101S TigerSHARC embedded processors with
250 MHz or 300 MHz core clocks.

Reset

1. Power-up reset: after power-up of the system, and strap options are stable, the RESET pin must be

asserted (low) for a minimum of 2 ms followed by a de-asserted (high) pulse of a minimum of 50
SCLK cycles and a maximum of 100 SCLK cycles and asserted (low) for a minimum of 100 SCLK

cycles. See Figure 1. A logic device may be required to generate the proper timing on the

RESET

signal.

TRST must also be asserted (low) during power-up to ensure proper operation of the device.

Figure 1. Power-up Reset Waveform

Booting

1. If an EPROM is used in the user’s system to boot the TigerSHARC processor's, the strap pin

must be pulled down with an external resistor to keep it stable during reset. After that,

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BMS

BMS

will act as

,

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the EPROM chip select signal. If EPROM is not used, pull up this pin with a 10KΩ resistor or tie it

directly to VDD_IO.

2. ADSP-TS101S processors have three boot modes — EPROM, host, and link port. Refer to [5]

“ADSP-TS101S TigerSHARC Processor Boot Loader Kernels Operation (EE-174)” and the source
code files under “..\Analog Devices\VisualDSP\Ts\ldr” to learn the whole process. Select one of the
modes to boot the TigerSHARC processors in your system.

Clock

1. Derive SCLK and LCLK from the same clock source.

2. If the system must work deterministically cycle-by-cycle, use an integer LCLK multiplication (2, 3, 4,

5, or 6) when setting LCLKRAT. Otherwise, a non-integer multiplier will also be fully functional and
perfectly acceptable.

3. The maximum LCLK/SCLK input jitter tolerance is 100 ps. Refer to the IDT

Cypress
RoboClock

®

(www.cypress.com) Web site to choose a proper clock buffer (TurboClock

™ 2

).

4. All ADSP-TS101S processors in a cluster (and any devices that interface an ADSP-TS101S in a

synchronous manner) should use the following guidelines.

®

(www.idt.com) or

™ 1

or

• Provide a single clock source for each fan-out buffer. Never mix frequencies. Refer to Figure 2.

Cl oc k
sources of
different
frequencies

Cl ock

source 1

Cl ock

source 2

Clock buffer with mul t i

reference i nputs

...

Cl ock

source

...

Bad G ood

Figure 2. Using fan-out buffers

Clock buffer with mul t i

ref erence inputs

...

...

Cl ock

source 1

Cl ock

source 2

Clock buffers with si ngl e

ref erence i nput

...

...

• Connections should be point-to-point from zero-skew clock buffer output to device clock input.

Match trace lengths to minimize skew. See Figure 3.

1

TurboClock™ is the trademark of IDT®.

2

RoboClock™ is the trademark of Cypress®.

Hardware Design Checklist for ADSP-TS101S TigerSHARC® Processors (EE-176) Page 2 of 11

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Cl ock

Source

Zer o- skew

cl ock buf fer

...

...

Ti ger SHARC ( I D=0)
Ti ger SHARC ( I D=1)

...

Ti ger SHARC ( I D=N)

Sync hr onous Host

SD R A M

Ot her Sy nchr onous
Memor y or Devi c es

These cl oc ks s houl d be dri ve
point to poi nt, and trace
l engths shoul d be matched.

n

Bus

Cl ust er

Figure 3. Clock distribution method

Power Supply

1. Note that the analog supply (VDD_A) provides power to the clock generator PLLs. To produce a

stable clock, systems must provide a clean power supply to power input VDD_A. Designers must pay
critical attention to bypassing the VDD_A supply. Figure 4 is a reference design of the filtering circuit.
Place components as close as possible to the device.

10uH

VDD

10uH

1uF 1nF

VVDDA

DDA

Ti ger SH A R C

VSSA
VSSA

Figure 4. Analog power supply filtering circuit reference design

2. The required power-on sequence for the DSP is to provide VDD (and VDD_A) before VDD_IO.

3. Ensure that the proper DC/DC module is chosen to provide the right voltage and enough current to the

core and I/O part of TigerSHARC. Refer to [4] “Estimating Power For The ADSP-TS101S (EE-169)”
to learn the method of power dissipation calculation. Consider the worst case.

4. Place bypass caps on the bottom side of the board, as close to the power pins as possible. There are

several ways to achieve this.

Hardware Design Checklist for ADSP-TS101S TigerSHARC® Processors (EE-176) Page 3 of 11

• 0.1uF low-inductance caps are recommended for bypass. 0.01uF and 0.001uF capacitors can also

be used with the 0.1uF capacitors for higher frequency filtering, provided their inductance is small
enough. In some cases SPICEing of the power supply filtering characteristics may be necessary.

• Use blind vias from the package balls to create sufficient space for capacitor placement. The

disadvantage to this is that blind vias are more expensive and that blind vias are not accessible for
scope probes.

• Part the traces in the four quadrants of the chip in four opposite directions, as shown in Figure 5.

Use the two resulting open horizontal and vertical lanes for placing SMD capacitors of size 0402
or smaller. The disadvantage is that small capacitor packages may be difficult to handle.

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Figure 5. Bypass capacitors layout scheme

5. Enough bulk capacitors are used to prevent voltage vibration on power supply plane caused by great

current variation. Several parallel electrolytic and tantalum capacitors are preferred in order to provide
high capacitance and low ESR.

JTAG Port

1. In a multiprocessor system, use separate buffers to drive the TCKs of different TigerSHARC

processors in order to get monotonic rising edges on these pins. For detailed and updated information,
refer to [6] “Analog Devices JTAG Emulation Technical Reference(EE-68)”.

2. Ensure that there is enough keep-out space around the JTAG connector so that the JTAG pod can be

easily plugged onto the board. For detailed and updated information, refer to [6] “Analog Devices
JTAG Emulation Technical Reference (EE-68)”.

Hardware Design Checklist for ADSP-TS101S TigerSHARC® Processors (EE-176) Page 4 of 11