Analog Devices ee-16 Application Notes

Engineer To Engineer Note EE-16

Technical Notes on using Analog Devices’ DSP components and development tools

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A slave can use this feature to request the token
from the master. The master, through a link

Using Token Passing to
Control SHARC Link Port
Bi-directional
Communication

Last Modified: 9/23/97

Contributed by: Richard G.

service request interrupt service routine, recognizes
the request for the token and decides whether or not
to release the token to the slave. Releasing the
token causes the master to set up its link port to
receive thus becoming a slave. The slave, having
verified that it has been given the token, will then
set up its link port to transmit and becomes the
master.

Using the Link Token Pass

Overview

Link port communication on the SHARC is bi­directional and can be switched at runtime through
software control. For bi-directional communication
to work, each link port must know which is the
transmitter and which is the receiver at any given
time. You can use token passing to accomplish this
type of software control. This document describes
how the link token pass example code implements
token passing on the SHARC.

Token Passing

Token passing is a software control scheme
designed to control the direction of communication
between two or more devices. It enables a program
to establish a master, or transmitter, in a given
communication system and to transfer that
mastership to any of the slaves at a given time.
The token, a software flag, resides in the master
link port and can be released to a slave upon
request or at the discretion of the master.

The link ports of the SHARC implement this
protocol through the link service request interrupt.

To use the link token pass example code, you must
load it on both the original master and the original
slave. The example code is ID intelligent for
multiprocessor systems: ID#1 is the original master
(transmitter) and ID#2 is original slave (receiver).

To implement token passing, the example code
follows this procedure:

1) The master transmits a buffer via DMA through
LPORT0 using LBUF3, and the slave receives
through LPORT0 using LBUF2.

2) The slave requests the token by generating an
LSRQ (link port service request) interrupt in the
disabled link port of the master (LPORT0).

3) The master responds by sending the token
release word and waits to see if it is accepted.

4) The slave checks the token release word and
accepts the token by emptying the master's link
buffer FIFO within a predetermined amount of
time.

a

5) If the token is accepted the slave becomes the
master and transmits a buffer of data to the new
slave. If the token is rejected, the master transmits
a second buffer.

6) When the transmission is complete the original
master finishes by setting up LBUF2 to receive
without DMA, and the original slave sets up
LBUF3 to transmit without DMA.

When implementing a software protocol for token
passing, it is important to note the following:

• Make sure that only one link buffer is enabled

to transmit at a time. Otherwise data will be
lost since neither link port will drive LxACK.
The example code polls the LSRQ register
status bits to ensure that the master becomes
the slave before the slave becomes the master
to avoid the two transmitter conflict.

• When using the status bits of the LSRQ register

for status detection and a link port that is
configured to receive is disabled, there will be
an RC delay before the 50k ohm pull-down
resistor on LxACK can pull the value below
logic threshold. In this instance, if the LxTM
(link port transmit request) bit is set in the
LSRQ register, then an LSR (link port service
request) will be latched and the LSRQ interrupt
may be generated unintentionally.

• In an application that uses timing control loops

to synchronize parallel code execution (such as
the example code), synchronization must not be
disrupted by unrelated influences at critical
sections. Disabling interrupt nesting is one of
the techniques the example code uses to control
synchronization.

/*_____________________________________________________________________________
ADSP-2106x LINK Token Pass Example
_______________________________________________________________________________*/

#include "def21060.h"

#define N 8 /* Size of buffer */

#define trw 0x0 /* Token release word */

#define orig_master_id 1 /* ID of SHARC to be original master */
#define orig_slave_id 2 /* ID of SHARC to be original slave */

.SEGMENT/DM dm_data;

.var source_1[N]= 0x11111111, 0x22222222, 0x33333333, 0x44444444,

0x11111111, 0x22222222, 0x33333333, 0x44444444;

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.var source_2[N]= 0x55555555, 0x66666666, 0x77777777, 0x88888888,

0x55555555, 0x66666666, 0x77777777, 0x88888888;

.var source_3[N]= 0x11111111, 0x22222222, 0x33333333, 0x44444444,

0x55555555, 0x66666666, 0x77777777, 0x88888888;

.var destination_1[N];

.var destination_2[N];

.var destination_3;

.ENDSEG;

.SEGMENT/PM isr_tabl; /* Interrupt Service Table */

NOP; NOP;NOP;NOP; /* Reserved interrupt */

rst_svc: NOP; jump start; NOP; NOP;

NOP; NOP; NOP; NOP;
sovfi_svc: RTI; RTI; RTI; RTI;
tmzhi_svc: RTI; RTI; RTI; RTI;
vrpti_svc: RTI; RTI; RTI; RTI;
irq2_svc: RTI; RTI; RTI; RTI;
irq1_svc: RTI; RTI; RTI; RTI;
irq0_svc: RTI; RTI; RTI; RTI;

NOP; NOP; NOP; NOP;
spr0_svc: RTI; RTI; RTI; RTI;
spr1_svc: RTI; RTI; RTI; RTI;
spt0_svc: RTI; RTI; RTI; RTI;
spt1_svc: RTI; RTI; RTI; RTI;
lp2_svc: NOP; jump lp2; NOP; NOP;
lp3_svc: NOP; jump lp3; NOP; NOP;
ep0_svc: RTI; RTI; RTI; RTI;
ep1_svc: RTI; RTI; RTI; RTI;
ep2_svc: RTI; RTI; RTI; RTI;
ep3_svc: RTI; RTI; RTI; RTI;
lsrq_svc: NOP; jump lsrq; NOP; NOP;
cb7_svc: RTI; RTI; RTI; RTI;
cb15_svc: RTI; RTI; RTI; RTI;
tmzl_svc: RTI; RTI; RTI; RTI;

.ENDSEG;

/*____________________MAIN ROUTINE___________________________________________*/

.SEGMENT/PM pm_code;

start:

bit set mode2 FLG0O; /* Set Flag0 for output */

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bit clr astat FLG0; /* Clear Flag0 for use as flag to test
*/

/* if this SHARC is the original master */
r0=dm(SYSTAT);
r0=FEXT r0 BY 8:3; /* Extract Processor ID from SYSTAT */

r1=orig_master_id;
r1=r0-r1; /* Test if this SHARC is original */
if eq jump start_as_master; /* master and jump appropriately */

r1=orig_slave_id;
r1=r0-r1; /* Test if this SHARC is original */
if eq jump start_as_slave; /* slave and jump appropriately */

idle;
nop;

/*_______________Start of Original Master
Routine____________________________________*/

start_as_master:

bit set astat FLG0; /* Set Flag0 to signify original master */

r0=source_1;
dm(II5)=r0; /* Set DMA tx index to start of source buffer */

r0=1;
dm(IM5)=r0; /* Set DMA modify (stride) to 1 */

r0=@source_1;
dm(C5)=r0; /* Set DMA count to length of data buffer */

r0=0xc000; /* LCOM Register: 2x rate on LBUF3, */
dm(LCOM)=r0; /* note:use r0=0x00010000 on rev. 0.X silicon */

r0=0x3f1ff; /* LAR Register: LBUF3->port 0 */
dm(LAR)=r0; /* All others inactive */

bit set imask LP3I; /* Enable Link buffer 3 interrupt */
bit set mode1 IRPTEN; /* Global interrupt enable */

r0=0x0000b000; /* LCTL Register: 32-bit data, LBUF3=tx */
dm(LCTL)=r0; /* enable DMA on LBUF3 */

/* This will start off the DMA transfer */

/* Always write LCTL after LAR */

wait_1: idle; /* Wait for Link buffer 3 interrupt */

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Technical Notes on using Analog Devices’ DSP components and development tools

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