Analog Devices ee-143 Application Notes

a

a Engineer To Engineer Note EE-143

aa

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp

• Internal memory ! Internal memory of

Understanding DMA on the
ADSP-TS101

other TigerSHARCs residing on the cluster
bus

Last modified: 25/10/01
Contributed By: A.C.

• Internal memory ! Host processor

• Internal memory ! Link port IO

The following Engineer-to-Engineer note will
discuss various forms of Direct Memory Accesses
on the TigerSHARC family of processors.
Assembly code examples are provided with this
note and explained.

The ADSP-TS101 is the first member of the
TigerSHARC® DSP family - ADI's new family of
ultra high-performance DSPs optimized for
telecommunications infrastructure as well as 16-bit
fixed point and 32-bit floating point general
purpose applications. The ADSP-TS101 features a
static superscalar architecture that combines RISC,
VLIW and standard DSP functionality.

Introduction

Direct Memory Access is a mechanism for
transferring data without the core being involved.
The TigerSHARC on-chip DMA controller allows
these transactions of data to take place as a
background task freeing up the processor core for
signal processing operations.
The TigerSHARC includes 14 DMA channels.
Four channels are dedicated to external memory
devices, eight to the link ports and two to the Auto
DMA registers. These channels are shown in
figure 1 in order of priority. The DMA controller
is capable of performing several types of data
transfers.

• Internal memory ! External memory and

memory-mapped peripherals

• External memory ! External peripherals

• External memory ! Link port IO

• Link port IO ! Internal memory

• Link port IO ! External memory

• Link port IO ! Link port IO

Most of the types listed above are demonstrated in
the examples described in this document.

Auto DMA Registers

Channel 13
Channel 12

Receiving Links

Channel 11 (Link 3 )
Channel 10 (Link 2 )

Channel 9 (Link 1)
Channel 8 (Link 0)

Transmitting Links

Channel 7 (Link 3)
Channel 6 (Link 2)
Channel 5 (Link 1)
Channel 4 (Link 0)

External Ports (EPs)

Channel 3 (DMAR3)
Channel 2 (DMAR2)
Channel 1 (DMAR1)
Channel 0 (DMAR0)

Highest priority

Lowest priority

Figure 1: DMA channels on TigerSHARC

Copyright 2001, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or a pplicatio n of customers’ prod u cts or for any
infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by
Analog Devices Applications and Development Tools Engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding the technical
accuracy of the content provided in all Analog Devices’ Engineer-to-Engineer Notes.

The afore mentioned data transfer types can be
broken down into the following main categories:

• Internal memory "! Cluster bus. This

transfer can be done in both directions and
requires the programming of two Transfer
Control Blocks, otherwise referred as a
TCB. One is a transmitting TCB and the
other a receiving TCB.

• Auto DMA register ! Internal memory.

This requires one receiver TCB.

• Internal/external memory ! Link ports.

Requires one transmitter TCB.

• Link ports ! Internal/external memory.

Requires one receiver TCB.

• Link port ! Link port.

Requires one receiver TCB.

The Transfer Control Block is a quad word (128­bit) that contains the vital information required to
perform a DMA. In the case of a transmitter TCB
the four words contain the address of the source
data, the number of words to be transferred, the
address increment and the control bits.

In the case of a receiver TCB these four words
contain destination address, the number of words
to be received, the address increment and the
control bits.

The TCB register is a 128-bit register, consisting
of four 32-bit registers as shown in figure 2.

Figure 2: DMA TCB Register

31

63

95

127

DI Register
DX Register
DY Register

DP Register

0
32

64
96

The DI register is the 32-bit index register for the
DMA. This contains the source or destination of
the data to be transmitted or received and can point
to internal, external memory or the link ports.

The DX register contains a 16-bit count value and
a 16-bit modify value. The count value is stored in
the upper 16 bits (16-31) and the modify in the
lower (0-15). If a two-dimensional DMA is
enabled then this register contains the modify and
count values for the X dimension only. The value
of X count must always be the number of normal
(32-bit) words to be transferred. Likewise, the
modify value is the number of normal words to
modify the count by. For example if we wanted to
transmit four quad words (16-normal words), then
the count value would be 0x10 and the modify
value 0x4 if the operand length in the DP register
is set to Quad word. If the operand length was set
to Long word then the modify value would be 0x2.
These values of course are application specific
however and would result in the entire data being
transferred in order, by altering the modify values
data can be transferred in any order required.

The DY register is used in conjunction with the
DX. This register contains the 16-bit modify and
16-bit count values for the DMA in the Y
dimension. If two-dimensional DMA is not
selected then this register is not used and the
contents are irrelevant.

The DP register contains all the control
information for the DMA. This register is split into
two main fields. The first contains all the control
information and the second the chaining
information. The breakdown of this register is
shown in figure 3.

EE-143 Page 2

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp

31-29 28 27 26-25 24 23 22 21-17 16-15 14-0

TY

PR

LEN

2DDMA

INT

DRQ

CHTG MS

CHEN

DMA Control

CHPT Chain Pointer:
Bits [14:0] Bits 16:2 of next TCB address.

Bits 1:0 of address are zero due to quad alignment.

MS Memory Select for chain pointer:
Bits[16:15] 00…Memory Block 0
01…Memory Block 1

10…Memory Block 2
11…Reserved

CHTG Chaining destination channel:
Bits[21:17] Specify device type:
00000…Channel 0 Source TCB

00001…Channel 0 Destination TCB
00010…Channel 1 Source TCB
00011…Channel 1 Destination TCB
00100…Channel 2 Source TCB
00101…Channel 2 Destination TCB
00110…Channel 3 Source TCB
00111…Channel 3 Destination TCB
01000…Channel 4 Link 0 Source TCB
01001…Channel 5 Link 1 Source TCB
01010…Channel 6 Link 2 Source TCB
01011…Channel 7 Link 3 Source TCB
10000…Channel 8 Link 0 Dest TCB
10001…Channel 9 Link 1 Dest TCB
10010…Channel 10 Link 2 Dest TCB
10011…Channel 11 Link 3 Dest TCB

10110...Channel 12 IFIFO DMA0 Dest TCB
10111

…Channel 13 IFIFO DMA1 Dest TCB

CHEN Chaining Enabled:
Bit[22] 0…No Chaining
1…DMA loads chaining targets channel TCB

registers from internal memory

DRQ DMA Request Enable:
Bit[23] 0…Once DMA channel is enabled, entire block
is transferred
1…DMA issies transactions only upon request

CHPT

Quad Word Address

Chaining Pointer

INT Interrupt Enable:
Bit [24] 0…DMA interrupt is disabled

1…DMA interrupts the core after transferring
whole block

LEN Operand Length:
Bits[26:25] 00…Reserved
01…Normal word

10…Long word
11…Quad word

2DDMA Two-dimensional DMA:
Bits[27] 0…One-dimensional DMA
1…Two-dimensional DMA

PR Determines Priority:
Bit[28] 0…DMA request priority is normal

1…DMA request priority is high

TY Specify the device type:
Bit[31:29] 000…DMA Disabled
001…IO Link ports
010…Internal Memory
011…Reserved
100…External Memory
101…External IO Device (fly-by)
110…Boot EPROM
111…Reserved

Figure 3: TCB DP Register

EE-143 Page 3

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp