Analog Devices EE129 Application Notes
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Engineer To Engineer Note EE-129
Technical Notes on using Analog Devices’ DSP components and development tools
Phone: (800) ANALOG-D, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com, FTP: ftp.analog.com, WEB: www.analog.com/dsp
has 80K words of SRAM and 4K words of ROM.
ADSP-2192 INTERPROCESSOR
COMMUNCATION
Modified 11/8/2000
Overview
Each DSP core on the ADSP-2192 has the ability
to communicate with the other DSP core directly
with DSP-to-DSP semaphores and interrupts or
indirectly with shared memory. The purpose of
this application note is to describe the
functionality of both forms.
ADSP-2192 Shared Memory
The ADSP-2192 is a 16-bit DSP with dual 219x
cores. The DSP memory map is shown in Figure
1.
The P1 DSP core has 48K words of SRAM and 4K
words of ROM. The P0 and P1 DSP cores also
share a 4K x 16-bit memory space.
The ADSP-2192 has a modified Harvard
architecture, which allows each DSP core to access
a data word and an instruction simultaneously.
This is accomplished by using two Data Address
Generators (DAG). As shown in Figure 2, each
DSP core has a DAG1 and a DAG2.
INTERRU PT CO NTRO LL ER/
ADSP -219X
DSP CORE
DAG1
4X4X16
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
MULT
TIMER/FLAGS
CACHE
64 X 24-BIT
DAG2
PROG RAM
4X4X16
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
PM DAT A BUS
DM DATA BUS
INPUT
REGISTERS
RESULT
REGISTERS
BARREL
SHIFTER
ALU
16 X 16-BIT
PROCESSOR P0 PROCESSOR P1
P0
MEMO R Y
16K324 PM
64K316 DM
BOOT ROM
ADDR DATA ADDR DATA
24
24
24
16
CORE
INTERF ACE
P0 DMA
CONTROLLER
FIFOS
SHARED
MEMOR Y
4K3 16 DM
ADDR DATA
ADDR DATA
SHAR ED DSP
I/O MA PPED
REGISTERS
P1
MEMOR Y
16K324 PM
32K316 DM
BOOT ROM
ADDR D ATAADDR DATA
P1 DMA
CONTROLLER
FIFOS
INTERRU PT CO NTRO LL ER/
CORE
INTERFACE
TIMER/ FL AG S
CACHE
64 X 24-BIT
PROGRAM
SEQUENCER
24
24
24
16
ALU
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BARREL
SHIFTER
GP I/O PINS
(& OPTIONA L
SERIAL
EEPROM)
SERIAL PORT
AC'97
COMPLIANT
HOST POR T
PCI 2. 2
OR
USB 1.1
JTAG
EMULATIO N
PORT
Fi
ure 2. ADSP-2192 Dual-Core DSP Block Diagram
Each DAG is associated with a particular data bus
and 16K word memory page, which allows it to
access its own DM/PM memory in addition to the
Figure 1. ADSP-2192 Memory Map
There are 140K words of internal memory on the
ADSP-2192. Within this space, the P0 DSP core
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Shared Memory. From settings at reset, DAG1
supplies addresses over the DM bus for memory
page 0 and DAG2 supplies addresses over the PM
bus for memory page 1. These memory page
selections may be changed using DMPGx
registers. For more information on address
generation, please refer to the Hardware
Reference Manual.
As shown in Figure 2, unlike core memory, shared
memory is internally single ported, so stalls will
happen when being accessed by both cores. Each
DSP core using the Data Memory (DM) bus can
access shared memory. Shared memory is
mapped to address 0x020000 and is thus on page
2. To access shared memory, DAG1 would be
initialized as follows:
INPUT
REGISTERS
RESULT
REGISTERS
16 X 16-BIT
ADSP-219X
DSP CORE
DAG2
4X4X16
CONNECT
DATA
REGIS T ER
FILE
DAG1
4X4X16
BUS
(PX)
MULT
DMPG1 = 0x2;
Shared memory could then be accessed over the
DM bus using either Direct or Indirect addressing.
The following example would write 0xFF to
location 0x020010, which resides in shared
memory.
AX0 = 0xFF;
DMPG1 = 0x2;
DM(0x0010) = AX0;
Unlike the internal memory of each DSP core,
every access to shared memory incurs at least one
cycle of stall (to perform synchronization),
therefore a minimum latency of 2 cycles is
incurred.
When accessing shared memory, a DSP core ‘locks
out’ the other DSP core for several cycles. A DSP
core can completely lock out the other core from
shared memory by performing back-to-back or
nearly back-to-back accesses to shared memory.
Once a particular DSP core "owns" the shared
memory, the shared memory interface is
relinquished only after 2 cycles of inactivity on the
interface. In the case where both cores try to
access shared memory in the same cycle, the
ADSP-2192 has a bus arbitration scheme to
handle the conflict. Arbitration is fixed at the
following priority: DSP0, DSP1.
Performing burst accesses is an effective way to
get good bandwidth from shared memory. Each
access after the first will take 2 cycles, which is
the maximum throughput.
Inter-processor Semaphores
The ADSP-2192 has a two internal DSP-to-DSP
core flags and an internal DSP-to-DSP core
interrupt controlled in the core semaphores
register. This is shown below in Figure 3.
Flag
Bit
0 Output DSP-DSP Semaphore 0
1 Output DSP-DSP Semaphore 1
2 Output DSP-DSP Interrupt
3 Reserved
4 Reserved
5 Reserved
6 Reserved
7 Output Register Bus Lock
8 Input DSP-DSP Semaphore 0 0
9 Input DSP-DSP Semaphore 1 1
10 Input DSP-DSP Interrupt 2
11 Input Reserved
12 Input AC’97 Register – PDC
13 Input PDC Interface Busy
14 Input Reserved
15 Input Register Bus Lock
The following example will illustrate the case
where DSP core P0 asserts DSP-DSP semaphore 0
of DSP core P1.
When a 1 is written to bit 0 of the core
semaphores register of DSP core P0, the resulting
core semaphore of DSP core P1, bit 8, is set. The
DSP-to-DSP semaphore 1 function the same way.
The DSP-to-DSP interrupt allows DSP core P0 to
interrupt DSP core P1 if the DSP-DSP interrupt is
unmasked in the IMASK register of DSP core P1.
The DSP-DSP interrupt routine can either be
Direction Function DSP Core
Flag In
4
Bus Access Status
5
Status (write from DSP
pending)
7
Status
Figure 3. DSP-to-DSP Semaphore Register Table
/* assert DSP-to-DSP flag 0 */
ax0 = 0x0001;
reg(0x34) = ax0;
EE-129 Page 2
Technical Notes on using Analog Devices’ DSP components and development tools
Phone: (800) ANALOG-D, FAX: (781)461-3010, EMAIL: dsp.support@analog.com, FTP: ftp.analog.com, WEB: www.analog.com/dsp
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