Analog Devices EE127 Application Notes

Engineer To Engineer Note EE-127

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the technical accuracy of the content provided in all Analog Devices’ Engineer-to-Engineer Notes.

Contributed by R. Hoffmann, European DSP Applications Rev 1 (20-March-02)

The ADSP-21065L On-chip SDRAM Controller

If you use a DSP to address SDRAM, you will need additional hardware or software to handle the
multiplexed row and column addressing and the refresh and precharge requirements. The ADSP-21065L
uses a hardware intensive solution, an on-chip SDRAM controller.

Introduction

The application note in troduces the On-chip SDRAM controller‘s characteristi cs. Basically, the internal
signal chain is shown with the necessary address-mapping scheme. The command truth table gives
detailed information about execution in the SDRAM. The important power up sequence summarizes
deep information to start successful designs. Code execution is described to get optimized performance.
A timing overview demonstrates the performance for different access modes. Refer to “EE-126: ABC of

SDRAMs”

a

1 – Signal Chain of SDRAM..................................................................................................................... 4

2 – On-Chip Controller Architecture ........................................................................................................ 5

2.1 – Controller Command Interface..................................................................................................... 5

2.2 – SHARC Address Buffer............................................................................................................... 5

2.3 – Controller Address Multiplexer ................................................................................................... 5

2.4 – Controller Delay Buffers.............................................................................................................. 5

3 – Command Coding ............................................................................................................................... 5

3.1 - Pin Description of Controller........................................................................................................ 5

3.2 - Controller Command Truth Table ................................................................................................ 6

Commands with SDCKE = high....................................................................................................... 6

Commands with Transition of SDCKE............................................................................................. 6

3.3 – Setup and Hold Times.................................................................................................................. 6

3.4 - Simplified State Diagram.............................................................................................................. 6

4 – Controller specific Properties.............................................................................................................. 8

4.1 – Address Mapping Scheme............................................................................................................ 8

4.2 – SHARC Bank Select (~MSx)........................................................................................................... 9

4.3 – Burst Stop (BST).......................................................................................................................... 9

4.4 – Mask Function (DQM)............................................................................................................... 10

4.5 – SDRAM Bank Select A[13:12].................................................................................................. 10

4.6 - Controller Address 10 (SDA 10) ................................................................................................ 10

4.7 – Burst Mode................................................................................................................................. 11

4.8 – Read Interruption........................................................................................................................ 11

4.9 – Write Interruption....................................................................................................................... 12

4.10 – Precharge All (PREA).............................................................................................................. 12

4.11 – Circular Access ........................................................................................................................ 12

4.12 – Auto Refresh (REF) ................................................................................................................. 13

5.13 – Self Refresh (SREF)................................................................................................................. 13

4.14 – Mode Register Set (MRS)........................................................................................................ 13

5 – Programming the SDRAM Interface................................................................................................. 13

5.1 – Wait Register.............................................................................................................................. 13

5.2 – Refresh Register......................................................................................................................... 13

5.3 - SDRAM Controller..................................................................................................................... 14

Timing Specs................................................................................................................................... 14

Power up Option.............................................................................................................................. 14

5.4 – SDRAM...................................................................................................................................... 14

5.5 – Memory Organization................................................................................................................ 15

5.6 – Setup Overview.......................................................................................................................... 15

1. Configuring the controller’s state machine................................................................................. 15

2. Configuring the SDRAM............................................................................................................ 16

5.7 – ADSP-21065L EZ-Kit Lite........................................................................................................ 16

6 – Timing of Power up Sequence..........................................................................................................17

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6.1 – Hardware.................................................................................................................................... 18

6.2 – Software Controller.................................................................................................................... 18

6.3 – Software Uniprocessor SDRAM................................................................................................ 18

6.4 – Example...................................................................................................................................... 18

6.5 – Interface after Reset.................................................................................................................... 19

6.6 – Disabling the Interface ............................................................................................................... 19

6.7 – Setting the I/O Flags................................................................................................................... 19

7 – Interface in Host Mode...................................................................................................................... 20

8 – DMA Transfers ................................................................................................................................. 21

8.1 – Internal Memory and SDRAM................................................................................................... 21

8.2 – Host and SDRAM ...................................................................................................................... 21

9 – Code Execution from SDRAM......................................................................................................... 21

9.1 – Requirements.............................................................................................................................. 22

9.2 – Instruction Pipeline .................................................................................................................... 23

9.3 – Sequential Code crossing Page/Bank......................................................................................... 24

9.4 – Non Sequential Code same Page/Bank...................................................................................... 25

9.5 – Non Sequential Code different Page/Bank................................................................................. 25

10 – Loop Execution from SDRAM....................................................................................................... 25

10.1 – Single Loop with DM Data Access.......................................................................................... 26

10.2 – Single Loop with PM Data Access, Cache enabled................................................................. 26

10.3 – Single Loop with PM Data Access, Cache disabled................................................................ 26

10.4 – Code Execution Performance Overview.................................................................................. 27

11 – Multiprocessing............................................................................................................................... 28

11.1 – Command Decoding................................................................................................................. 29

11.2 – MRS Decoding......................................................................................................................... 29

11.3 – REF Decoding.......................................................................................................................... 29

11.4 – SREF Decoding........................................................................................................................ 29

11.5 – Bus Transition Cycle................................................................................................................ 29

12 – Optimizing the Performance ........................................................................................................... 29

12.1 – SDRAMs in Parallel................................................................................................................. 29

12.2 – External Buffering.................................................................................................................... 30

12.3 – Using PC Modules ................................................................................................................... 31

12.4 – Rules for Optimized Performance............................................................................................ 31

13 – SDRAM and Booting...................................................................................................................... 32

13.1 – Loader Kernel........................................................................................................................... 32

13.2 – Booting Modes......................................................................................................................... 32

13.3 – In Circuit Emulation (ICE)....................................................................................................... 33

14 – Core and IOP Transfers to SDRAM................................................................................................ 33

14.1 – Sequential Reads without Interruption..................................................................................... 34

14.2 – Sequential Reads with minimum Interruption ......................................................................... 35

14.3 – Non Sequential Reads without Interruption............................................................................. 36

14.4 – Sequential Writes without Interruption.................................................................................... 37

14.5 – Sequential Writes with minimum Interruption......................................................................... 38

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14.6 – Non Sequential Writes without Interruption............................................................................ 39

14.7 – Minimum Write to Read Interval............................................................................................. 40

14.8 – Minimum Read to Write Interval............................................................................................. 41

14.9 – Reads between Page/Bank........................................................................................................ 42

14.10 – Writes between Page/Bank..................................................................................................... 43

14.11 – Auto Refresh .......................................................................................................................... 44

14.12 – Self Refresh............................................................................................................................ 45

14.13 – Chained DMA Transfers........................................................................................................ 46

14.14 – Host Access during Reads...................................................................................................... 47

References............................................................................................................................................... 48

1 – Signal Chain of SDRAM

Figure 1 illustrates the signal chain between the ADSP-21065L, the controller and the SDRAM itself.
The 3 parts for the signal flow to be considered:

• ADSP-21065L (core, IOP, address buffer)

• SDRAM Controller (control interface, delay buffer, address multiplexer)

• SDRAMemory

Core

IOP

Figure 1: Signal chain: ADSP-21065L to SDRAM

ADSP-21065L

int. CLK

int. RD

int. WR

int. Reset

int. ACK

int. MSx

Address

buffer

D31:0

busy

enable

a

m

m

o

e

t

C

n

I

A23:0

Delay buffe r

d

n

a

f

r

A

e

c

e

r

d

d

i

t

l

u

M

SDCLK
SDCKE

~RAS
~CAS

~SDWE

DQM

SDA10
~MSx

A13

s

r

s

e

x

A12

e

l

p

A11:0

max. 66 MHz

A10

CLK
CKE

~RAS
~CAS

~WE

DQM

SDRAM

~CS

BA0
BA1

A11:0

DQ31:0

D31:0A23:0

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2 – On-Chip Controller Architecture

The synchronous interface between the ADSP-21065L and the on-chip controller can be described in 3
basic parts:

2.1 – Controller Command Interface

Because of the 2 different timing protocols, the internal SHARC commands are converted to comply
with the JEDEC standard for SDRAMs. The SDCLK clock, maximum 66 MHz, is used for synchronous
operation. The SHARC’s internal request lines or strobes are used to access the SDRAM with pulsed
commands. The controller’s internal ACK line inserts variable wait states to the DSP during overhead
cycles, caused by DRAM technology.

2.2 – SHARC Address Buffer

The SHARC’s address buffer enables the controller activation depending on bank assignment and
external address. The SHARC’s address pipeline depth is 1, therefore address pipelining is not
supported.

2.3 – Controller Address Multiplexer

Every first read or write action is issued in multiplexed mode. A max imum of 4096 Rows within 1024
columns can be addressed. Furthermore, the A13 and A12 lines are used to select the current SDRAM
bank.

2.4 – Controller Delay Buffers

If systems incorporate a heavy busload, additional buffers are used to decouple the input from the
capacitive load. The internal delay buffer in conjunction with an external buffer reduces additional logic
to a minimum.

3 – Command Coding

3.1 - Pin Description of Controller

Controller Pin Type Signal Description

SDCLK0 (I/O/T/S) pulse master clock
SDCLK1 (O/T/S) pulse clock 2
SDCKE (I/O/T) level command
~MSx (I/O/T) pulse command
~RAS (I/O/T) pulse command
~CAS (I/O/T) pulse command
~SDWE (I/O/T) pulse command
SDA10 (O/T) level/pulse address/command
DQM (O/T) pulse DQ buffer control
A[9:0], A[11] (I/O/T) level address

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A[12] (I/O/T) level bank select
A[13] (I/O/T) level bank select

D[31:0] (I/O/T) level data
I=input, O=output, T=Hi-Z, S=synchronous

3.2 - Controller Command Truth Table

This section provides a table to get an overview of all commands provided by the SDRAM controller.
These commands are handled automatically by the interface.

Commands with SDCKE = high

Command SDCKE(n-1) SDCKE(n) ~CS ~RAS ~CAS ~SDWE SDA10 ADDR

MRS 1 1 0 0 0 0 v v
ACT 1 1 0 0 1 1 v v
RD 1 1 0 1 0 1 0 v
WR 1 1 0 1 0 0 0 v
Command without validity of address
DESL 1 1 1 x x x x x
NOP 1 1 0 1 1 1 x x
BST 1 1 0 1 1 0 x x
PREA 1 1 0 0 1 0 1 x
REF 1 1 0 0 0 1 1 x

Commands with Transition of SDCKE

While the SDCKE line toggles in asynchronous manner, the commands are sampled synchronous to the
CLK signal.

Command SDCKE(n-1) SDCKE(n) ~CS ~RAS ~CAS ~SDWE SDA10 ADDR

SREF En 1 0 0 0 0 1 x x
SREF Ma 0 0 x x x x x x
SREF Ex 0 1 1 x x x x x
x=don’t care, v=valid data input, 0=logic 0, 1=logic 1, En=entry, Ma=maintain, Ex=exit

Note: Power-down and Suspend mode are not supported and auto precharge is not allowed.

3.3 – Setup and Hold Times

The synchronous operation uses the SDCLK as reference. Commands, addresses and data are latched at
the rising edge of SDCLK. The valid time margin around the rising edge is defined as setup time (time
before rising edge) and hold time (time after rising edge) to guarantee that both the controller and the
SDRAM are working reliably together. Signal’s- slew rates, propagation delays (PCB) and capacitive
loads (devices) influence these parameters and should be taken into consideration. The controller’s
timing characteristics are available in the ADSP-21065L datasheet.

3.4 - Simplified State Diagram

The state diagram is useful to analyze all deterministic sequences. Figure 4 shows all the possible states.

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Figure 4: Simplified Stat e Diagram: ADSP-21065L SDRAM Controller

Mode

Register

Core

IOP
MMS
Host

tRCD=CL

MRS SREF

Idle

State

Exit

tMRD=2 tXSR=2+tRC

ACT

BST

RD

tRCD

1-3

T

S

B

Row

activate

B

S

BST

WR

T

SDRDIV
Counter

expired

tRCD

1-3

Self

Refresh

REF

Auto

Refresh

CL

1-3

Read

full page

Controller works in full page burst

(256- 512 -1024 words)

burst is not self terminating

set bit

SDPSS in

PREA

IOCTL

Automatic sequenc e

Manual input

PREA

Pre-

charge

all

RD

Write

full page

only one bank at the time

can be active

tRAS

1-7

tRP

1-7

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4 – Controller specific Proper ties

The next properties applies especially for the ADSP-21065L:

4.1 – Address Mapping Scheme

Basically, there are various possibilities accessing the SDRAM, for instance you access all rows in a
bank sequentially or you access all banks in a row sequentially. PC DIMM modules are accessed
different by its controller compared to a typical DSP application. The ADSP-21065L controller uses a
hardware map scheme optimized for digital signal processing.
Because different sizes can be switched to the controller, different map schemes should be enabled
decoded by the number of banks (bit SDBN in IOCTL) and page size (bit SDPGS in IOCTL):

Page x Bank Column Address Bank Select Row Address

256 x 2 IA[7:0] => EA[7:0] IA[8] => EA[13] IA[19:9] => EA[10:0]
512 x 2 IA[8:0] EA[8:0] IA[9] EA[13] IA[20:10] EA[10:0]
1024 x 2 IA[9:0] EA[9:0] IA[10] EA[13] IA[21:11] EA[10:0]
256 x 4 IA[7:0] EA[7:0] IA[9:8] EA[13:12] IA[21:10] EA[11:0]
512 x 4 IA[8:0] EA[8:0] IA[10:9] EA[13:12] IA[22:11] EA[11:0]
1024 x 4 IA[9:0] EA[9:0] IA[11:10] EA[13:12] IA[23:12] EA[11:0]

IA= controller input address, EA= controller output address

Note: The address map scheme allows you to understand the system’s performance.

Figure 2 reproduces an example of the controller’s address mapping for 32bit data. In page 0, the
SDRAM’s banks A to D are sequentially selected. As bank interleaving is not supported, every off bank
access has the same overhead as an off page access. The address region of a full page for instance
0x20000 to 0x203FF (1024 words) can be accessed with 1 cycle/word.

Note: Only one bank at a time can be active. Off-bank and off-page access have the same overhead.

Example: Controller Address Multiplexing of 16M x 4bit

~MSx

25 24

~MSx

25 24

~MSx

25 24

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Row Column

4096 1024

BA0 BA1

13 12

BA0 BA1

13 12

23

BA0 BA1

12

11 10

9

Row

Column

9

0

1. Output:

12

Rowaddress

0

Columnaddress

Input:

SHARC
address

2. Output:

Figure 2: Controller Addres s M app ing to b an k 0 o f AD SP -21 06 5L

4M x 4bit x 4, Page size 1024 words

Bank_A Bank_B Bank_C Bank_D

On Page

Access

g

a

P

g

a

P

0x20000
0x203FF

0x20400

0

e

0x2FF000
0x2FF3FF

5

9

0

4

e

0x207FF

Off Bank

Access

0x2FF400
0x2FF7FF

0x20800
0x20BFF

0x20C00
0x20FFF

Off Page

Access

0x2FF800
0x2FFBFF

0x2FFC00
0x2FFFFF

4.2 – SHARC Bank Select (~MSx)

Each SHARC bank (~MS0-3) can be mapped in the memory region of the SDRAM. Only one SHARC
bank can be connected (bit SDBS in IOCTL) to the interface at a time.

4.3 – Burst Stop (BST)

Although the controller works in full page burst only, there is one way to interrupt the full page burst
with the burst stop command. The next table lists the different situations in which the BST occurs:

BST issued if next access is:

• Non external SDRAM access (access to another SHARC bank)

• Core access (e.g. computation unit, interrupt, cache, DAG)

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• DMA operation (higher priority request of IOP)

• SDRDIV counter expired (refresh period counter)

• SDRAM read to write transition

• SDRAM off page and off bank access

• ~HBR asserted (host interface)

• ~BRx asserted (multiprocessing)

Note: The BST is an indicator for a SHARC core accesses.

4.4 – Mask Function (DQM)

The DQM pin is used by the controller to mask write and precharge operations directly, the affect
latency is zero cycles. It does not apply to read operations. It’s used to disconnect the SDRAM’s DQ
buffer to avoid data contention.

Command(n-1) Command(n) DQM(n)

x PREA 1
WR BST 1
x=don’t cares

Note: The controller does not support partial reads or writes. All DQM lines should be tied together.

4.5 – SDRAM Bank Select A[13:12]

The next tables show how address lines A12 and A13 select the different banks:
2 banked access:

Banks A13 A12 SDA10

Bank_A 0 - 0
Bank_B 1 - 0
Both banks x - 1

Note: A12 is not used in 2 banked memories.

4 banked access:

Banks A13 A12 SDA10

Bank_A 0 0 0
Bank_B 0 1 0
Bank_C 1 0 0
Bank_D 1 1 0
All_banks x x 1
x=don’t care, 0=logic 0, 1=logic 1

Note: It doesn’t matter if you connect A[13:12] to BA[1:0] or A[13:12] to BA[0:1].

4.6 - Controller Address 10 (SDA 10)

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This pin provides a special solution to gain control about the SDRAM, even by host accesses. It allows
accessing all banks simultaneously (without using addresses 12 and 13) during a refresh in slave mode. It
must be connected with the A10 pin of the SDRAM.

Note: This pin has multifunctional character: depending on command, it acts as an address- or as a
command pin.

4.7 – Burst Mode

The controller uses a full page burst only. Only the first read or write command is accompanied with an
external address, which is driven by the controller until the burst is interrupted by another address. The
SDRAM’s burst counter depending on the used page size internally addresses only sequential locations.
Note: The SDRAM must support full page burst.

4.8 – Read Interruption

The SHARC architecture doesn’t support address pipelining. The next address will only be latched until
the previous data are off-chip. For sequential reads, the controller simply applies the command and
address assuming that it will be sequential. For non-sequential reads, it inserts additional dummy reads
(NOPs) in order to reject the data given out by SDRAM (Figure 3), if the next address from the core is
non-sequential. It applies to:

• Non sequential reads

• Sequential reads interruption

• Read to write transition

Note: The burst (sequential reads) assumes address pipelining to benefit from its throughput.

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SDCLK

Figure 3: Non sequential Reads, CL=2

tDRD

CMD

ADDR

DATA

NOP NOPRD NOP RD

Dummy reads

COLQ0

Q0

Q+1 Q+2 Q+3

Data Q+1-3 ignored, because

controller's read buffers turned off

NOP NOPRD NOP

Dummy reads

COLQ2

Q8 Q+9 Q+10 Q+11

BST

The controller inserts dummy reads depending from the used read latency:

Command (n-x) tDRD cycles (n-1) Command (n)

RD CL+1 RD/BST

4.9 – Write Interruption

While the controller is working in full page burst only, there is a need to interrupt the current burst with
the BST command. Additionally, the write buffer must be masked to block the data immediately. It’s
realized by asserting the DQM pin during the BST command.

Note: Every write burst interruption is masked with the DQM pin during the BST command. It doesn’t
apply for non-sequential writes.

4.10 – Precharge All (PREA )

This command precharges all banks of the SDRAM simultaneously, (SDA 10 high to select all banks)
which returns the banks in idle state.

Note: The controller doesn’t support precharge of single bank while only one bank at the time is active.

4.11 – Circular Access

The controller supports the circular access during sequential read or writes in a page, performing a fixed
throughput of 1 cycle/word. At the end of the page (defined in the IOCTL register), for instance 1024
words, the instructions r0=dm(0x203FF) followed by r1=dm(0x20000) are also executed with 1
cycle/word.

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Note: This functionality is similar to the DAG’s circular buffering mode.

4.12 – Auto Refresh (REF)

The auto- or CAS before RAS- refresh requires only a command, no addresses. After the SDRAM
registers the command, it asserts internally CAS and delayed RAS to execute a row’s refresh. The row
interval is typically tRC=15,625 µs, it’s a good compromise between data access time and the refresh
reliability. The limit of refresh period is given through the tREFmax spec.
Note: The controller doesn’t support burst refresh.

5.13 – Self Refresh (SREF)

The self-refresh is a very effective way to reduce the application’s power consumption to a minimu m.
The device can run in this mode during long SHARC core operations. This mode is used to disable the
SDRAM controller. The device starts refreshing itself triggered by an internal timer.

4.14 – Mode Register Set (MRS)

With the MRS, the controller initializes the SDRAM with:
Burst length is fixed to full page burst
Burst type is fixed to sequential burst

5 – Programming the SDRAM Interface

The Interface is programmed through the mapped registers in following order:

1. WAIT Register (wait states and wait states mode)

2. SDRDIV Register (setting the refresh period value)

3. IOCTL Register (programs the controller and the SDRAM)

5.1 – Wait Register

For proper operation, make sure that the dedicated WAIT register of SHARC bank setting is

• Wait state mode: SDRAM is not stalled or suspended by assertion of ACK

• Wait states: zero wait states allowed only

Note: Zero wait state is required to enable the handshake between SHARC and SDRAM controller.

5.2 – Refresh Register

This counter enables applications to coordinate the clock rate with the SDRAM’s required refresh rate.
The SDRDIV register is used to enter the period of refresh commands in number of cycles calculated in
the following equation:

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

SDCLKSDRDIV




Note: This formula is not linear, because the specs tRP and CL vary through the different devices.

The controller sets SDRDIV=0 during the power up mode to initialize the refresh counter with 8 REF
cycles. Hereby, the controller issues permanent refresh commands within a tRCmin period.
Note: If you configure SDRDIV to 0, the controller issues permanent REF commands.

5.3 - SDRAM Controller

In order to support timing requirements and power up modes for different SDRAM vendors, the ADSP­21065L provides programmability of tRAS, tRP and CL in the IOCTL register.

Timing Specs

The SDTRP bit defines the precharge time tRPmin related to the vendor’s device.
The SDTRAS bit is used to define the row active time tRASmin related to the vendor’s device.

Note: The spec tRAS is used for the refresh cycle with tRC=tRAS+tRP.
Note: The specs tRP and tRAS depend on the different devices’ speed grades only.

The SDCL bit is used to define the Read latency CLmin related to the vendor’s device.
Note: This value depends on the application’s speed and different speed grades of devices. CL is the
most critical parameter to be set.
Note: The specification requires defining tRASmin, tRPmin and CLmin as a fraction of the SDCLK
period.

Power up Option

The SDPM bit controls 2 different software power-up options:
SDPM=0

• PREA command (brings the SDRAM in the defined idle state)

• 8 REF commands (charges SDRAM’s internal nodes)

• MRS command (initializes the SDRAM’s working mode)

SDPM=1

• PREA command

• MRS command

• 8 REF commands

Note: Some vendors don’t stick to the power up sequence.

tREF

⋅= CLtRP

Rows




4−−−



5.4 – SDRAM

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With the MRS (Mode register set), the Read latency (SDCL bit) is also used to program the state
machine of the SDRAM in order to get the best performance depending from the application’s speed.
Addresses [11:0] are used during the MRS to program the following specs:

Address bit Mode of operation

• A[2:0] Burst length is hardwired to full page burst

• A[3] Burst type is hardwired to sequential burst

• A[6:4] Read Latency: the user defines CLmin in 1-3 SDCLK cycles

• A[11:7] Operation mode is hardwired to 0

Note: The operation mode is reserved for test and future.

5.5 – Memory Organization

The SDBN- and SDPGS bits in IOCTL register are used to program the address map scheme:

256 x 2

Refresh Type Size Parallel Whole Size

2k 1M x 16bit 16 Mbit 2 32 Mbit

512 x 2

Refresh Type Size Parallel Whole Size

2k 2M x 8bit 16 Mbit 4 64 Mbit

1024 x 2

Refresh Type Size Parallel Whole Size

2k 4M x 4bit 16 Mbit 8 128 Mbit

256 x 4

Refresh Type Size Parallel Whole Size

2k 2M x 32bit 64 Mbit
4k 4M x 16bit 64 Mbit 2 128 Mbit
4k 4M x 32bit 128 Mbit

512 x 4

Refresh Type Size Parallel Whole Size

4k 8M x 8bit 64 Mbit 4 256 Mbit
4k 8M x 16bit 128 Mbit 2 256 Mbit

1024 x 4

Refresh Type Size Parallel Whole Size

4k 16M x 4bit 64 Mbit 8 512 Mbit (maximum size)
4k 16M x 8bit 128 Mbit 4 512 Mbit (maximum size)

Note: Each bank supports up to 16M x 32bit.

5.6 – Setup Overview

1. Configuring the controller’s state machine

Timing spec Description Controller Configuration
tCK clock cycle time, hardware 20–66 MHz

EE-127 Page 15

Technical Notes on using Analog Devices’ DSP components and development tools

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