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DS1307
64 X 8 Serial Real Time Clock
FEATURES
Real time clock counts seconds, minutes,
hours, date of the month, month, day of the
week, and year with leap year compensation
valid up to 2100
56 byte nonvolatile RAM for data storage
2-wire serial interface
Programmable squarewave output signal
Automatic power-fail detect and switch
circuitry
Consumes less than 500 nA in battery backup
mode with oscillator running
Optional industrial temperature range
-40°C to +85°C
Available in 8-pin DIP or SOIC
Recognized by Underwriters Laboratory
ORDERING INFORMATION
DS1307 8-Pin DIP
DS1307Z 8-Pin SOIC (150 mil)
DS1307N 8-Pin DIP (Industrial)
DS1307ZN 8-Pin SOIC (Industrial)
PIN ASSIGNMENT
l
8
V
7
6
5
8
7
6
5
CC
SQW/OUT
SCL
SDA
V
CC
SQW/OUT
SCL
SDA
X1
2
X2
V
3
BAT
GND
DS1307 8-Pin DIP (300 mil)
GND
DS1307Z 8-Pin SOIC (150 mil)
4
l
X1
2
X2
V
BAT
3
4
PIN DESCRIPTION
VCC - Primary Power Supply
X1, X2 - 32.768 kHz Crystal Connection
V
- +3V Battery Input
BAT
GND - Ground
SDA - Serial Data
SCL - Serial Clock
SQW/OUT - Square wave/Output Driver
DESCRIPTION
The DS1307 Serial Real Time Clock is a low power, full BCD clock/calendar plus 56 bytes of
nonvolatile SRAM. Address and data are transferred serially via a 2-wire bi-directional bus. The
clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the
month date is automatically adjusted for months with less than 31 days, including corrections for leap
year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1307
has a built-in power sense circuit which detects power failures and automatically switches to the battery
supply.
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DS1307
OPERATION
The DS1307 operates as a slave device on the serial bus. Access is obtained b y implementing a START
condition and providing a device identification code followed b y a re gister address. Subsequent re gisters
can be accessed sequentially until a STOP condition is executed. When V
falls below 1.25 x V
CC
BAT
the
device terminates an access in progress and resets the device address counter. Inputs to the device will
not be recognized at this time to prevent erroneous data from being written to the device from an out of
tolerance system. When V
mode. Upon power up, the device switches from battery to V
recognizes inputs when V
falls below V
CC
is greater than 1.25 x V
CC
BAT
the device switches into a low current battery backup
when VCC is greater than V
CC
. The block diagram in Figure 1 shows the main
BAT
+0.2V and
BAT
elements of the Serial Real Time Clock.
DS1307 BLOCK DIAGRAM Figure 1
SIGNAL DESCRIPTIONS
VCC, GND - DC power is provided to the device on these pins. V
applied within normal limits, the device is fully accessible and data can be written and read. When a
3-volt battery is connected to the device and V
is below 1.25 x V
CC
However, the Timekeeping function continues unaffected by the lower input voltage. As V
V
the RAM and timekeeper are switched over to the external power supply (nominal 3.0V DC) at
BAT
V
.
BAT
- Battery input for any standard 3-volt lithium cell or other energy source. Batter y voltage must be
V
BAT
held between 2.0 and 3.5 volts for proper operation. The nominal write protect trip point voltage at which
access to the real time clock and user RAM is denied is set by the internal circuitry as 1.25 x V
nominal. A lithium battery with 48 mAhr or greater will back up the DS1307 for more than 10 years in
the absence of power at 25 degrees C.
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is the +5 volt input. When 5 volts is
CC
, reads and writes are inhibited.
BAT
falls below
CC
BAT
DS1307
SCL (Serial Clock Input) - SCL is used to synchronize data movement on the serial interface.
SDA (Serial Data Input/Output) - SDA is the input/output pin for the 2-wire serial interface. The SDA
pin is open drain which requires an external pullup resistor.
SQW/OUT (Square Wave/ Output Driver) - When enabled, the SQWE bit set to 1, the SQW/OUT pin
outputs one of four square wave frequencies (1 Hz, 4 kHz, 8 kHz, 32 kHz). The SQW/OUT pin is open
drain which requires an external pullup resistor. SQW/OUT will operate with either Vcc or Vbat applied.
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 12.5 pF.
For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time Clocks.” The DS1307 can also be driven by an
external 32.768 kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated.
Please review Application Note 95, “Interfacing the DS1307 with a 8051-Compatible Microcontroller”
for additional information.
RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the DS1307 is shown in Figure 2. The real time
clock registers are located in address locations 00h to 07h. The RAM registers are located in address
locations 08h to 3Fh. During a multi-byte access, when the address pointer reaches 3 Fh, the end of RAM
space, it wraps around to location 00h, the beginning of the clock space.
DS1307 ADDRESS MAP Figure 2
00H
07H
08H
3FH
SECONDS
MINUTES
HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
56 x 8
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time and calendar are set or initialized by writing the
appropriate register bytes. The contents of the time and calendar registers are in the Binary-Coded
Decimal (BCD) format. Bit 7 of Register 0 is the Clock Halt (CH) bit. When this bit is set to a 1, the
oscillator is disabled. When cleared to a 0, the oscillator is enabled.
Please note that the initial po w er on state of al l regi sters is no t def in ed . Th eref ore it i s i mportant to
enable the oscillator (CH bit=0) during initial configuration.
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DS1307
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (2023 hours).
On a 2-wire START, the current time is transferred to a second set of registers. The time information is
read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case of an update of the main registers during a read.
DS1307 TIMEKEEPER REGISTERS Figure 3
CONTROL REGISTER
The DS1307 Control Register is used to control the operation of the SQW/OUT pin.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OUT X X SQWE X X RS1 RS0
OUT (Output control): This bit controls the output level of the SQW/OUT pin when the square wave
output is disabled. If SQWE=0, the logic level on the SQW/OUT pin is 1 if OUT=1 and is 0 if OUT=0.
SQWE (Square Wave Enable): This bit, when set to a logic 1, will enable the oscillator output. The
frequency of the square wave output depends upon the value of the RS0 and RS1 bits.
RS (Rate Select): These bits control the frequency of the square wave output when the square wave
output has been enabled. Table 1 lists the square wave frequencies that can be selected with the RS bits.
SQUAREWAVE OUTPUT FREQUENCY Table 1
RS1 RS0 SQW OUTPUT
FREQUENCY
00 1 Hz
0 1 4.096 kHz
1 0 8.192 kHz
1 1 32.768 kHz
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DS1307
2-WIRE SERIAL DATA BUS
The DS1307 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that
controls the message is called a master. The devices that are controlled b y the master are referred to as
slaves. The bus must be controlled by a master device which generates the serial clock (SC L), controls
the bus access, and generates the START and STOP conditions. The DS1307 operates as a slav e on the
2-wire bus. A typical bus configuration using this 2-wire protocol is show in Figure 4.
TYPICAL 2-WIRE BUS CONFIGURATION Figure 4
Figures 5, 6, and 7 detail how data is transferred on the 2-wire bus.
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit. Within the 2-wire bus specifications a regular mode (100 kHz clock rate) and a fast mode
(400 kHz clock rate) are defined. The DS1307 operates in the regular mode (100 kHz) only.
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DS1307
Acknowledge: Each receiving device, when add ressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an ex tra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 5
Depending upon the state of the R/ W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
2. Data transfer from a slave transmitter to a master rec eiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. This is followed b y the slave
transmitting a number of data bytes. The master returns an acknowledge bit after all re ceived bytes
other than the last byte. At the end of the last received byte, a ’not acknowledge’ is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred
with the most significant bit (MSB) first.
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DS1307
The DS1307 may operate in the following two modes:
1. Slave receiver mode (DS1307 write mode): Serial data and clock are received through SDA and
SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions
are recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and *direction bit (See Fi gure 6). The address byte is
the first byte received after the start condition is generated by the master. The address byte contains
the 7 bit DS1307 address, which is 1101000, followed by the *direction bit (R/W ) which, for a write,
is a 0. After receiving and decoding the address byte the device outputs an acknowledge on the SDA
line. After the DS1307 acknowledges the slave address + write bit, the master transmits a re gister
address to the DS1307 This will set the register pointer on the DS1307. The master will then begin
transmitting each byte of data with the DS1307 acknowledging each byte received. The master will
generate a stop condition to terminate the data write.
DATA WRITE - SLAVE RECEIVER MODE Figure 6
2. Slave transmitter mode (DS1307 read mode): The first byte is received and handled as in the slave
receiver mode. However, in this mode, the *direction bit will indicate that the transfer dire ction is
reversed. Serial data is transmitted on SDA by the DS1307 while the serial clock is input on SCL.
START and STOP conditions are recognized as the beginning and end of a serial transfer (See
Figure 7). The address byte is the first byte received after the start condition is generated by the
master. The address byte contains the 7-bit DS1307 address, which is 1101000, followed by the
*direction bit (R/ W ) which, for a read, is a 1. After receiving and decoding the address byte the
device inputs an acknowledge on the SDA line. The DS1307 then begins to transmit data starting
with the register address pointed to by the register pointer. If the register pointer is not written to
before the initiation of a read mode the first address that is read is the last one stored in the register
pointer. The DS1307 must receive a Not Acknowledge to end a read.
DATA READ - SLAVE TRANSMITTER M ODE Figure 7
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DS1307
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.5V to +7.0V
Operating Temperature 0°C to 70°C (-40°C to 85°C for industrial)
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds DIP
See JPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
* This is a stress rating only and functional operation of the device at these or a n y other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C or -40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage V
Logic 1 V
Logic 0 V
V
Battery Voltage V
BAT
CC
IH
IL
BAT
4.5 5.0 5.5 V 1
2.2 VCC+0.3 V 1
-0.3 +0.8 V 1
2.0 3.5 V 1
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C or -40°C to +85°C; V
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage I
I/O Leakage I
Logic 0 Output V
Active Supply Current I
Standby Current I
Battery Current (OSC ON);
I
SQW/OUT OFF
Battery Current (OSC ON);
I
SQW/OUT ON (32 kHz)
LI
LO
OL
CCA
CCS
BAT1
BAT2
300 500 nA 4
480 800 nA 4
1
1
0.4 V 2
1.5 mA 9
200
=4.5V to 5.5V)
CC
µA
µA
10
11
µA
3
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AC ELECTRICAL CHARACTERISTICS
DS1307
(0°C to 70°C or -40°C to +85°C; V
=4.5V to 5.5V)
CC
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
SCL Clock Frequency f
Bus Free Time Between a STOP and
SCL
t
BUF
0 100 kHz
4.7
µs
START Condition
Hold Time (Repeated) START Condition t
LOW Period of SCL Clock t
HIGH Period of SCL Clock t
Set-up Time for a Repeated START
t
HD:STA
LOW
HIGH
SU:STA
4.0
4.7
4.0
4.7
µs
µs
µs
µs
5
Condition
Data Hold Time t
Data Set-up Time t
HD:DAT
SU:DAT
Rise Time of Both SDA and SCL Signals t
Fall Time of Both SDA and SCL Signals t
Set-up Time for STOP Condition t
SU:STO
Capacitive Load for each Bus Line C
I/O Capacitance C
R
F
B
I/O
0
µs
250 ns
1000 ns
300 ns
4.7
µs
400 pF 8
10 pF
6, 7
Crystal Specified Load Capacitance 12.5 pF
NOTES:
1. All voltages are referenced to ground.
2. Logic zero voltages are specified at a si nk current of 5 mA at VCC=4.5V, VOL=GND for capacitive
loads.
3. I
4. VCC=0V, V
specified with VCC=5.0V and SDA, SCL=5.0V.
CCS
=3V.
BAT
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
7. The maximum t
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
IHMIN
has only to be met if the device does not stretch the LOW period (t
HD:DAT
LOW
) of the
SCL signal.
8. C
9. I
- total capacitance of one bus line in pF.
B
- SCL clocking at max frequency = 100 kHz.
CCA
10. SCL only.
11. SDA and SQW/OUT
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TIMING DIAGRAM Figure 8
DS1307 64 X 8 SERIAL REAL TIME CLOCK
8-PIN DIP MECHANICAL DIMENSIONS
PKG 8-PIN
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
0.360
9.14
0.240
6.10
0.120
3.05
0.300
7.62
0.015
0.38
0.120
3.04
0.090
2.29
0.320
8.13
0.008
0.20
0.015
0.38
0.400
10.16
0.260
6.60
0.140
3.56
0.325
8.26
0.040
1.02
0.140
3.56
0.110
2.79
0.370
9.40
0.012
0.30
0.021
0.53
DS1307
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DS1307Z 64 X 8 SERIAL REAL TIME CLOCK
8-PIN SOIC (150-MIL) MECHANICAL DIMENSIONS
DS1307
PKG
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
L IN.
MM
phi
8-PIN
(150 MIL)
0.188
4.78
0.150
3.81
0.048
1.22
0.004
0.10
0.053
1.35
0.050 BSC
1.27 BSC
0.230
5.84
0.007
0.18
0.012
0.30
0.016
0.41
0° 8°
56-G2008-001
0.196
4.98
0.158
4.01
0.062
1.57
0.010
0.25
0.069
1.75
0.244
6.20
0.011
0.28
0.020
0.51
0.050
1.27
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