Datasheet DAC8222GP, DAC8222FS, DAC8222FP, DAC8222EW, DAC8222BTC Datasheet (Analog Devices)

Dual 12-Bit Double-Buffered

a

FEATURES
Two Matched 12-Bit DACs on One Chip
Direct Parallel Load of All 12 Bits for High Data

Throughput
Double-Buffered Digital Inputs
12-Bit Endpoint Linearity (ⴞ1/2 LSB) Over Temperature
+5 V to +15 V Single Supply Operation
DACs Matched to 1% Max
Four-Quadrant Multiplication
Improved ESD Resistance
Packaged in a Narrow 0.3" 24-Lead DIP and 0.3"

24- Lead SOL Package
Available in Die Form

APPLICATIONS
Automatic Test Equipment
Robotics/Process Control/Automation
Digital Gain/Attenuation Control
Ideal for Battery-Operated Equipment

Multiplying CMOS D/A Converter

DAC8222

FUNCTIONAL DIAGRAM

GENERAL DESCRIPTION

The DAC8222 is a dual 12-bit, double-buffered, CMOS digital­to-analog converter. It has a 12-bit wide data port that allows a
12-bit word to be loaded directly. This achieves faster through­put time in stand-alone systems or when interfacing to a 16-bit
processor. A common 12-bit input TTL/CMOS compatible
data port is used to load the 12-bit word into either of the two
DACs. This port, whose data loading is similar to that of a RAM’s
write cycle, interfaces directly with most 12-bit and 16-bit bus
systems. (See DAC8248 for a complete 8-bit data bus interface
product.) A common bus allows the DAC8222 to be packaged
in a narrow 24-lead 0.3" DIP and save PCB space.

The DAC is controlled with two signals, WR and LDAC. With
logic low at these inputs, the DAC registers become transparent.
This allows direct unbuffered data to flow directly to either
DAC output selected by DAC A/DAC B. Also, the DAC’s

double-buffered digital inputs will allow both DACs to be
simultaneously updated.

DAC8222’s monolithic construction offers excellent DAC-to­DAC matching and tracking over the full operating tempera­ture range. The chip consists of two thin-film R-2R resistor
ladder networks, four 12-bit registers, and DAC control logic
circuitry. The device has separate reference-input and feedback
resistors for each DAC and operates on a single supply from
+5 V to +15 V. Maximum power dissipation at +5 V using
zero or V

The DAC8222 is manufactured with highly stable thin-film re­sistors on an advanced oxide-isolated, silicon-gate, CMOS
technology. Improved latch-up resistant design eliminates the
need for external protective Schottky diodes.

logic levels is less than 0.5 mW.

DD

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

DAC8222–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VDD = +5 V or +15 V, V

REF A

= V

= +10 V, V

REF B

OUT A

= V

= 0 V; AGND = DGND = 0 V;

OUT B

TA = Full Temperature Range Specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)

Parameter Symbol Conditions Min Typ Max Units

STATIC ACCURACY

Resolution N 12 Bits
Relative Accuracy INL Endpoint Linearity Error DAC8222A/E/G ±1/2 LSB

Differential Nonlinearity DNL All Grades are Guaranteed Monotonic ±1 LSB
Full-Scale Gain Error

1

G

DAC8222A/E ±1 LSB

FSE

DAC8222G ±2 LSB
DAC8222F/H ±4 LSB

Gain Temperature Coefficient

∆Gain/∆Temperature TCG

Output Leakage Current

(Pin 2), I

I

OUT A

(Pin 24) 0000 0000 0000 TA = Full Temp. Range ±50 nA

I

OUT B

Input Resistance

(V

REF A

, V

)R

REF B

Input Resistance Match

LKG

∆R
R

REF

REF

(Notes 2, 7) ±2 ±5 ppm/°C

FS

All Digital Inputs = TA = +25°C ±5 ±10 nA

(Note 9) 8 11 15 kΩ

REF

DIGITAL INPUTS

Digital Input High V

Digital Input Low V

Input Current I

Input Capacitance

2

INH

INL

IN

C

IN

VDD = +5 V 2.4 V

= +15 V 13.5 V

V

DD

VDD = +5 V 0.8 V

= +15 V 1.5 V

V

DD

VIN = 0 V or V
and V

INL

DB0–DB11 10 pF

or V

DD

INH

WR, LDAC, DAC A/DAC B 15 pF

POWER SUPPLY

Supply Current I

DD

All Digital Inputs V
All Digital Inputs 0 V or V

DC Power Supply
Rejection Ratio PSRR ∆V
(∆Gain/∆VDD)

AC PERFORMANCE CHARACTERISTICS

Propagation Delay
Current Settling Time
Output Capacitance C

AC Feedthrough at FT

or I

I

OUT A

SWITCHING CHARACTERISTICS

DAC Select to t
Write Set-Up Time
DAC Select to t
Write Hold Time
LDAC to t
Write Set-Up Time
LDAC to t
Write Hold Time
Data Valid to t
Write Set-Up Time
Data Valid to t
Write Hold Time
Write Pulse Width t
LDAC Pulse Width t

NOTES

11

Measured using internal R

12

Guaranteed and not tested.

13

See timing diagram.

14

From 50% of digital input to 90% of final analog output current.

V

= V

REF A

15

WR, LDAC = 0 V; DB0–DB11 = 0 V to VDD or VDD to 0 V.

REF B

4, 5

5, 6

OUT B

and R

FB A

= +10 V; OUT A, OUT B load = 100 Ω, C

t

PD

t

S

O

A

FT

B

2, 3

AS

AH

LS

LH

DS

DH

WR

LWD

. Both DAC digital inputs = 1111 1111 1111.

FB B

= ±5% 0.002 %/%

DD

2

TA = +25°C 350 ns
TA = +25°C1µs
Digital Inputs = All 0s 90 pF

, C

C

OUT A

OUT A

REF A

REF B

EXT

OUT B

, C

OUT B

to I

OUT A

to I

OUT B

= 13 pF.

; V

; V

REF A

REF B

Digital Inputs = All 1s 120 pF
C
V
f = 100 kHz; TA = +25°C –70 dB
V
f = 100 kHz; TA = +25°C –70 dB

DAC8222F/H ±1 LSB

±0.2 ±1%

TA = +25°C ±0.001 ±1 µA
TA = Full Temp. Range ±10 µA

INL

or V

DD

INH

10 100 µA

2mA

90 pF

120 pF

= 20 V p-p; –70 dB

= 20 V p-p; –70 dB

+25°C–40°C to +85°C

VDD = +5 V VDD = +15 V

8

–55°C to +125°C All Temps

10

150 180 210 60 ns min

0 0 0 0 ns min

80 100 120 60 ns min

20 20 20 20 ns min

220 240 260 100 ns min

00 0 10 ns min

130 160 170 90 ns min
100 120 130 60 ns min

16

Settling time is measured from 50% of the digital input change to where the

output voltage settles within 1/2 LSB of full scale.

17

Gain TC is measured from +25°C to T

18

These limits apply for the commercial and industrial grade products.

19

Absolute temperature coefficient is approximately +50 ppm/°C.

10

These limits also apply as typical values for VDD = +12 V with +5 V CMOS
logic levels and T

Specifications subject to change without notice.

= +25°C.

A

–2–

or from +25°C to T

MIN

MAX

.

REV. C

DAC8222

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C, unless otherwise noted.)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V

V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . –0.3 V, V

Digital Input Voltage to DGND . . . . . . . –0.3 V, V

, I

I

OUTA

V

REFA

V

RFBA

to AGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V

OUTB

, V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V

REFB

, V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V

RFBB

+0.3 V

DD

+0.3 V

DD

Operating Temperature Range

AW Version . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

EW, FW, FP Versions . . . . . . . . . . . . . . . . –40°C to +85°C

GP, HP, HS Versions . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C

Package Type ␪

1

JA

␪

JC

Units

24-Lead Hermetic DIP (W) 69 10 °C/W
24-Lead Plastic DIP (P) 62 32 °C/W
24-Lead SOL (S) 72 24 °C/W

NOTE

1

θJA is specified for worst-case mounting conditions, i.e., qJA is specified for

device in socket for Cerdip, and P-DIP packages; JA is specified for device
soldered to printed circuit board for SO package.

CAUTION

1. Do not apply voltages higher than VDD or less than GND

potential on any terminal except V

and RFB.

REF

2. The digital control inputs are Zener-protected; however,

permanent damage may occur on unprotected units from
high-energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.

3. Do not insert this device into powered sockets; remove

power before insertion or removal.

4. Use proper antistatic handling procedures.

5. Devices can suffer permanent damage and/or reliability deg-

radation if stressed above the limits listed under Absolute
Maximum Ratings for extended periods.

PIN CONNECTIONS

24-Lead 0.3" Cerdip
24-Lead Plastic DIP

24-Lead SOL

28-Terminal LCC

NC = NO CONNECT

ORDERING GUIDE

INL GFSE Temperature Package Package

Model (LSB) (LSB) Range Description Option

DAC8222EW ±1/2 ±1 –40°C to +85°C Cerdip-24 Q-24
DAC8222GP ±1/2 ±20°C to +70°C P-DIP-24 N-24
DAC8222BTC/883* ±1 ± 4 –55°C to +125°C LCC-28 E-28A
DAC8222FW ±1 ± 4 –40°C to +85°C Cerdip-24 Q-24
DAC8222FP ±1 ± 4 –40°C to +85°C P-DIP-24 N-24
DAC8222FS ± 1 ± 4 –40°C to +85°C SOL-24 R-24

*Consult factory for DAC8222/883 MIL-STD data sheet.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8222 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. C

–3–

DAC8222

DICE CHARACTERISTICS

DIE SIZE 0.124 × 0.132 inch, 16,368 sq. mils

×

3.55 mm, 10.56 sq. mm)

(3.15

11. AGND 13. DB4

12. I

13. R

14. V

OUT A

FB A

REF A

14. DB3

15. DB2

16. DB1

15. DGND 17. DB0 (LSB)

16. DB11(MSB) 18. DAC A/DAC B

17. DB10 19.

LDAC

18. DB9 20. WR

19. DB8 21. V

10. DB7 22. V

11. DB6 23. R

12. DB5 24. I

DD

REF B

FB B

OUT B

Substrate (die backside) is internally connected to VDD.

WAFER TEST LIMITS

(@ VDD = +5 V or +15 V, V

REF A

= V

= +10 V, V

REF B

OUT A

= V

= 0 V; AGND = DGND = 0 V; TA = +25ⴗC)

OUT B

DAC8222G

Parameter Symbol Conditions Limit Units

Relative Accuracy INL Endpoint Linearity Error ±1LSB max
Differential Nonlinearity DNL All Grades are Guaranteed Monotonic ± 1LSB max
Full Scale Gain Error

1

G

FSE

Digital Inputs = 1111 1111 1111 ±4LSB max

Output Leakage Digital Inputs = 0000 0000 0000 ±50 nA max

(I

, I

OUT A

)I

OUT B

LKG

Pads 2 and 24

Input Resistance

, V

(V

REF A

Input Resistance Match ∆R

Digital Input High V

Digital Input Low V

Digital Input Current I
Supply Current I

)R

REF B

REF

REF

R

REF

INH

INL

IN

DD

DC Supply Rejection PSR ∆V

Pads 4 and 22 8/15 kΩ max

±1% max

VDD = +5 V 2.4 V min
V

= +15 V 13.5 V min

DD

VDD = +5 V 0.8 V max
V

= +15 V 1.5 V min

DD

VIN = 0 V or VDD; V
All Digital Inputs V
All Digital Inputs 0 V or V

= ±5% 0.002 %/% max

DD

INL

INL

or V

or V

DD

INH

INH

±1 µA max
2

0.1 mA max

(∆Gain/∆VDD)

NOTES

1

Measured using internal R
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

FB A

and R

FB B

.

–4–

REV. C

TYPICAL PERFORMANCE CHARACTERISTICS

DAC8222

Figure 1. Channel-to-Channel Match­ing (DAC A and B are Superimposed)

Figure 4. Nonlinearity vs. V

REF

Figure 2. Differential Nonlinearity
vs. V

REF

Figure 5. Nonlinearity vs. V

REF

Figure 3. Differential Nonlinearity
vs. V

REF

Figure 6. Nonlinearity vs. V

DD

Figure 7. Nonlinearity vs. Code
(DAC A and B are Superimposed)

REV. C

Figure 8. Nonlinearity vs. Code at T

A

= –55°C, +25°C, +125°C for DAC A and
B (All Superimposed)

–5–

Figure 9. Absolute Gain Error
Changes vs. V

REF

DAC8222

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 10. Full-Scale Gain Error vs.
Temperature

Figure 13. Supply Current vs. Logic
Input Voltage

Figure 11. Logic Input Threshold
Voltage vs. Supply Voltage (V

DD

Figure 14. Multiplying Mode Frequency
Response vs. Digital Code

Figure 12. Supply Current vs.

)

Temperature

Figure 15. Output Leakage Current
vs. Temperature

Figure 16. Analog Crosstalk vs.
Frequency

–6–

Figure 17. Interface Timing vs. V

REV. C

DD

Figure 18. Burn-In Circuit

PARAMETER DEFINITIONS

RESOLUTION (n)

The resolution of a DAC is the number of states (2n) into which
the full-scale range (FSR) is divided (or resolved); where n is
equal to the number of bits.

RELATIVE ACCURACY (INL)

Relative accuracy, or integral nonlinearity, is the maximum de­viation of the analog output (from the ideal) from a straight line
drawn between the end points. It is expressed in terms of least
significant bit (LSB), or as a percent of full scale.

DIFFERENTIAL NONLINEARITY (DNL)

Differential nonlinearity is the worst case deviation of any adja­cent analog output from the ideal 1 LSB step size. The devia­tion of the actual “step size” from the ideal step size of 1 LSB is
called the differential nonlinearity error or DNL. DACs with
DNL greater than ±1 LSB may be nonmonotonic ±1/2 LSB
INL guarantees monotonicity and ±1 LSB maximum DNL.

GAIN ERROR (G

FSE

)

Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of full-scale or in
terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.

See Orientation in Digital-to-Analog Converters Section of the
current data book, for additional parameter definitions.

GENERAL CIRCUIT DESCRIPTION

CONVERTER SECTION

The DAC8222 contains four 12-bit registers (two input regis­ters and two DAC registers), two highly stable thin-film R-2R
resistor ladder networks, and interface control logic circuitry.
Also included are 24 single-pole, double-throw, NMOS transis­tor current switches.

DAC8222

Figure 19. Simplified Single DAC Circuit Configuration.
(Switches Are Shown for All Digital Inputs at Zero)

Figure 20. N-Channel Current Steering Switch

Figure 19 shows a simplified circuit for the R-2R ladder network
and transistor switches for one DAC. R is typically 11 kΩ. The
transistor switches are binarily scaled in size to maintain a con­stant voltage drop across each switch. Figure 20 shows a single
NMOS transistor switch.

The binary-weighted currents are switched between I
AGND by the N-channel MOS transistor switches. The selec­tion between I

and AGND is determined by the digital input

OUT

code. It is important to note here that the voltage difference

OUT

and

REV. C

–7–

DAC8222

between I

and AGND terminals be as close to zero as practi-

OUT

cal in order to keep DAC errors to a minimum. This is normally
done by connecting AGND to the noninverting input of an op
amp and I
tor (R

FB

op amp’s output directly to the DAC’s R

to the inverting input. The DAC’s internal resis-

OUT

) can be used for the feedback resistor by connecting the

terminal. The op

FB

amp also provides the current-to-voltage conversion for the
DAC’s output current. The output voltage is dependent on the
DAC’s digital input code and V

V

= –V

OUT

, and is given by:

REF

× D/4096

REF

where D is the digital input code integer number that is between
0 and 4095.

The DAC’s input resistance, V
to a constant value, R. This means that V

(Figure 19), is always equal

REF

can be driven by a

REF

reference voltage or current, ac or dc (positive or negative). It is
recommended that a low-temperature-coefficient external R

FB

resistor be used if a current source is employed.

The DAC’s output capacitance (C

) is code dependent and

OUT

varies from 90 pF (all digital inputs low) to 120 pF (all digital
inputs high).

Figure 19 shows a transistor switch in series with the R-2R lad­der terminating resistor and R

resistor. They were designed

FB

into the DAC to binarily match the ladder leg switches and im­prove power supply rejection and gain error temperature coeffi­cient. The gates of these transistor switches are connected to

, so that an “open-circuit” exists when VDD is not applied.

V

DD

This means that an op amp’s output voltage will go to either
“rail” if powered up before the DAC. Also, R
not be measured without V

being applied.

DD

resistance can-

FB

Figure 21. Digital Input Structure For One Bit

DIGITAL SECTION

The DAC8222’s digital inputs are CMOS inserters. They were
designed to convert TTL and CMOS input logic levels into
voltage levels to drive the internal circuitry. The digital inputs
are TTL compatible at V
V

= +15 V. The DAC8222 can use +5 V CMOS logic levels

DD

with V

= +12 V; however, supply current will rise to approxi-

DD

= +5 V and CMOS compatible at

DD

mately 5 mA–6 mA.

Figure 21 shows the DAC’s digital input register structure for
one bit. This circuit drives the DAC register. Digital controls φ
and φ shown are generated from

DAC A/DAC B and WR con-

trol signals.

As shown in Figure 21, these inputs are electrostatic-discharge
protected with two internal distributed diodes; they are con­nected between V

and DGND. Each digital input has a typi-

DD

cal input current of less than 1 nA.

When the digital inputs are in the region of +1.2 V to +2.8 V
(peaking at +1.8 V) using a +5 V power supply or in the region
of +1.7 V to +12 V (peaking at +3.9 V) with a +15 V power
supply, the input register transistors are operating in their linear
region and draw current from the power supply. It is therefore,
recommended that the digital input voltages be as close to the
supply rails (V

and DGND) as is practically possible to keep

DD

supply currents at a minimum. The DAC8222 may be operated
with any supply voltage between the range of +5 V to +15 V.

INTERFACE CONTROL LOGIC

The DAC8222’s input control logic circuitry is shown in Figure

22. Note how the

WR signal is used in conjunction with DAC

A/ DAC B to load data into either input register. LDAC loads

data from the input registers to the DAC register; the DAC’s
analog output voltage is determined by the data contained in
each DAC register.

The truth table for the DAC registers is shown in the Mode Se­lection Table. Note how the input register is transparent when
WR is low and LDAC is high, and that the DAC register is
transparent when WR is high and LDAC is low (LDAC updates
the DAC’s analog output voltage). The DAC is transparent
from input to output when WR and LDAC are both low, and
the DAC is latched (input and output is not being updated)
when WR and LDAC are both high.

Figure 22. Input Control Logic

–8–

REV. C

DAC8222

Table I. Mode Selection

Digital Inputs Register Status

DAC A/B WR LDAC Input Register DAC Register Input Register DAC Register

L L L WRITE WRITE LATCHED WRITE
H L L LATCHED WRITE WRITE WRITE
L L H WRITE LATCHED LATCHED LATCHED
H L H LATCHED LATCHED WRITE LATCHED
X H L LATCHED WRITE LATCHED WRITE
X H H LATCHED LATCHED LATCHED LATCHED

L = Low, H = High, X = Don’t Care

DAC A

DAC B

INTERFACE CONTROL LOGIC

DAC A/DAC B (Pin 18)–DAC Selection. Active low for

DAC A and active high for DAC B.

WR (Pin 20)–WRITE. Active Low. Used to write data into
either DAC A or DAC B input registers, or active high latches
data into the input registers.

LDAC (Pin 19)–LOAD DAC. Active Low. Used to simulta-
neously transfer data from DAC A and DAC B input registers
to both DAC outputs. The DAC becomes transparent (activity
on the digital inputs appear at the analog output) when both
WR and LDAC are low. Data is latched into the output regis­ters on the rising edge of LDAC.

WRITE TIMING CYCLES

Two timing diagrams are shown and are at the user’s discretion
which to use.

The TWO-CYCLE UPDATE, as the name implies, allows both
DAC registers to be loaded and the outputs updated in two
cycles. Data is first loaded into one DAC’s input register on the
first write cycle, and then new data loaded into the other DAC’s
input register while simultaneously updating both DAC outputs
on the second cycle.

The THREE-CYCLE UPDATE allows DAC A and DAC B
registers to be loaded and analog output to be updated at a later
time. The first two cycles load both DACs as above, and the
third cycle updates the outputs.

The LDAC and DAC A/DAC B control pins can be tied to­gether and controlled with a single strobe. When using the DAC
in this configuration, DAC B must be loaded first.

REV. C

Two-Cycle Update

Three-Cycle Update

Figure 23. Write Cycle Timing Diagram

–9–

DAC8222

* RESISTORS R1 THROUGH R4 ARE ONLY NECESSARY TO TRIM FOR

ABSOLUTE ACCURACY BETTER THAN ⴞ0.01%, SEE TEXT FOR
COMPLETE DETAILS.

** REGISTERS AND CONTROL CIRCUITRY OMITTED FOR SIMPLICITY.

Figure 24. Unipolar Configuration (Two-Quadrant Multiplication)

APPLICATIONS INFORMATION

UNIPOLAR OPERATION

Figure 24 shows a simple unipolar (2-quadrant multiplication)
circuit using the DAC8222 and OP270 dual op amp (use two
OP42s for higher speeds), and Table II the corresponding code
table. Resistors R1, R2, and R3, R4 are used only if full-scale
gain adjustments are required. Low temperature coefficient
(approximately 50 ppm/°C) resistors or trimmers should be
used. Maximum full-scale error without these resistors for the
top grade device and V

= ±10 V is 0.024% and 0.097% for

REF

the low grade. C1 and C2 provide phase compensation to help
reduce overshoot and ringing when high speed op amps are used.

Full-scale adjustment is accomplished by loading the digital
inputs with all 1s and adjusting R1 (or R3) so that

4095



V

OUT

= V

REF

×

Full-scale can also be adjusted by varying V



4096




voltage, thus

REF

eliminating R1, R2, R3 and R4. Zero adjustment is performed
by setting the DAC’s digital inputs to all 0s and adjusting the op
amp’s offset adjust so that V

= 0 V. To maintain monotonic-

OUT

ity and minimize gain and linearity errors, it is recommended
that the op amp offset voltage be adjusted to less than 10% of
1 LSB (244 µV) over the operating temperature range of interest.

Table II. Unipolar Binary Code Table (Refer to Figure 24)

Binary Number in
DAC Register Analog Output, V

OUT

MSB LSB (DAC A or DAC B)

4095





1111 1111 1111 –V

1000 0000 0000 –V

0000 0000 0001 –V

REF

REF

REF





4096

2048










4096

1

4096

= –1/2 V






REF

0000 0000 0000 0 V

NOTE

1 LSB = (2

–12

) (V

REF

) =

1

4096

(V

REF

)

BIPOLAR OPERATION

The bipolar (offset binary) four-quadrant operation configura­tion using the DAC8222 is shown in Figure 25 and the corre­sponding code in Table III. The circuit makes use of the OP470
a quad op amp (use four OP42s for higher speeds).

Resistors R1, R2, R3, and R4 may be omitted and full-scale
output voltage may be adjusted by varying V

or the value

REF

of R5 and R8. If resistors R1, R2, R3, and R4 are omitted,

–10–

REV. C

DAC8222

Figure 25. Bipolar Configuration (Four-Quadrant Multiplication)

Table III. Bipolar (Offset Binary) Code Table
(Refer to Figure 25)

Binary Number in
DAC Register Analog Output, V

OUT

MSB LSB (DAC A or DAC B)

2047



1111 1111 1111 +V

1000 0000 0001 +V

REF

REF



2048




2048




1




1000 0000 0000 0 V

1



0111 1111 1111 –V

0000 0000 0000 –V

NOTE

1 LSB = (2

–11

) (V

REF

) =

1

2048

(V

REF

)

REF

REF







2048

2048









2048

resistors R5, R6, R7, should be ratio-matched to 0.01% so that
gain error meets data sheet specifications. (Corresponding resis­tors, R8, R9, and R10 for DAC B should also be matched to

0.01%). The resistors should have identical temperature coeffi­cients if operating over the full temperature range.

Zero and full-scale are adjusted one of two ways and are at the
user’s discretion. Zero-output can be adjusted by first setting
the digital inputs to 1000 0000 0000 and adjusting R1 (R3 for
DAC B) so that V
R4 for DAC B) are omitted, then V

OUTA

(or V

) equals 0 V. If R1, R2 (R3,

OUT B

= 0 V can be adjusted

OUT

by varying R6, R7 (R9, R10 for DAC B) ratios. Full-scale is ad­justed by setting the digital inputs to 1111 1111 1111 and vary­ing R5 (R8 for DAC B). Full-scale can also be adjusted by
varying V

. Full-scale output is equal to V

REF

minus one LSB.

REF

REV. C

–11–

DAC8222

Figure 26. Single Supply Operation (Current Switching Mode)

SINGLE SUPPLY OPERATION

CURRENT STEERING MODE

Because the DAC8222’s R-2R resistor ladder terminating resis­tor is internally connected to AGND, it lends itself well to single
supply operation in the current steering mode. This means that
AGND can be raised above system ground as shown in Figure 26.
The output voltage range will be from +5 V to +10 V depending
on the digital input code and is given by:

V

= VOS + (n/4096) (VOS)

OUT

where V

= Offset Reference Voltage (+5 V in Figure 26)

OS

where n = Decimal Equivalent of the Digital Input Word

VOLTAGE SWITCHING MODE

Figure 27 shows the DAC8222 in a single supply voltage
switching mode of operation. In this configuration, the DAC’s
R-2R ladder acts as a voltage divider. The output voltage at the

pin exhibits a constant impedance R (typically 11 kΩ) and

V

REF

must be buffered by an op amp. R

pins are not used in this

FB

circuit configuration. The reference input voltage must be main­tained within +1.25 V of AGND and V

from +12 V to +15 V

DD

to preserve device accuracy.

The output voltage expression is given by:

V

= V

OUT

(n/4096)

REF

where n = Decimal Equivalent of the Digital Input Word

APPLICATIONS TIPS

GENERAL GROUND MANAGEMENT

Grounding techniques should be tailored to each individual sys­tem. Ground loops should be avoided, and ground current
paths should be as short as possible and have a low impedance.

The DAC8222’s AGND and DGND pins should be tied to­gether at the device socket to prevent digital transients from ap­pearing at the analog output. This common point then becomes
the single ground point connection. AGND and DGND should
then be brought out separately and tied to their respective power
supply grounds. Ground loops can be created if both grounds
are tied together at more than one location, i.e., tied together at
the device and at the digital and analog power supplies.

A PC board ground plane can be used for the single point
ground connection should the connections not be practical at
the device socket. If neither of these connections is practical or
allowed, the device should be placed as close as possible to the
system’s single point ground connection. Back-to-back Schottky
diodes should then be connected between AGND and DGND.

POWER SUPPLY DECOUPLING

Power supplies used with the DAC8222 should be well filtered
and regulated. Local supply decoupling consisting of a 1 µF to
10 µF tantalum capacitor in parallel with a 0.1 µF ceramic is
highly recommended. The capacitors should be connected be­tween the V

and DGND pins and at the device socket.

DD

–12–

REV. C

Figure 27. Single Supply Operation (Voltage Switching Mode)

DAC8222

Figure 28. Digitally-Programmable Window Detector (Upper/Lower Limit Detector)

BASIC APPLICATIONS

PROGRAMMING WINDOW DETECTOR

Figure 28 shows the DAC8222 used in a programmable window
detector configuration. The required upper and lower limits for
the test are loaded into DAC A and DAC B. If a signal at the
test input is not within the programmed limits, the output will
indicate a logic zero.

REV. C

–13–

MICROPROCESSOR INTERFACE CIRCUITS

The DAC8222’s versatile loading structure greatly simplifies in­terfacing to 16-bit bus systems; it also reduces the number of
“glue” logic components. Data loading into its 12-bit wide data
input is achieved by use of only two control signals, WR and
LDAC. DAC selection is controlled with a single DAC A/DAC B
line.

Figures 29 and 30 show how easily the DAC8222 interfaces
with the 8086 and 68000 16-bit microprocessors.

DAC8222

Figure 29. DAC8222 to 8086 Interface

Figure 30. DAC8222 to 68000 Interface

–14–

REV. C

OUTLINE DIMENSIONS

1

28

5

11

18

BOTTOM

VIEW

19

25

26

4

12

0.028 (0.71)

0.022 (0.56)

45ⴗ TYP

0.015 (0.38)
MIN

0.055 (1.40)

0.045 (1.14)

0.050
(1.27)
BSC

0.075

(1.91)

REF

0.011 (0.28)

0.007 (0.18)
R TYP

0.095 (2.41)

0.075 (1.90)

0.150
(3.51)

BSC

0.300 (7.62)
BSC

0.200
(5.08)
BSC

0.075

(1.91)

REF

0.458 (11.63)

0.442 (11.23)
SQ

0.458

(11.63)

MAX

SQ

0.100 (2.54)

0.064 (1.63)

0.088 (2.24)

0.054 (1.37)

Dimensions shown in inches and (mm).

24-Lead Cerdip

(Q-24)

0.005 (0.13) MIN 0.098 (2.49) MAX

24

1

PIN 1

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

1.280 (32.51) MAX

0.100 (2.54)
BSC

0.070 (1.78)

0.030 (0.76)

24-Lead Plastic DIP

(N-24)

1.275 (32.30)

1.125 (28.60)

24

112

PIN 1

0.210

(5.33)

MAX

0.200 (5.05)

0.125 (3.18)

0.022 (0.558)

0.014 (0.356)

0.100

(2.54)

BSC

0.070 (1.77)

0.045 (1.15)

13

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

13

0.310 (7.87)

0.220 (5.59)

12

0.060 (1.52)

0.015 (0.38)

SEATING
PLANE

0.150
(3.81)
MIN

SEATING
PLANE

0.150
(3.81)
MIN

0.325 (8.25)

0.300 (7.62)

0.320 (8.13)

0.290 (7.37)

15°

0°

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.015 (0.38)

0.008 (0.20)

28-Terminal Leadless Ceramic Chip Carrier

(E-28A)

24-Lead Wide-Body SOL

(R-24)

0.6141 (15.60)

0.5985 (15.20)

24 13

1

PIN 1

0.2992 (7.60)

0.2914 (7.40)

12

0.1043 (2.65)

0.0926 (2.35)

0.4193 (10.65)

0.3937 (10.00)

0.0291 (0.74)

0.0098 (0.25)

C3123–0–5/00 (rev. C) 00459

ⴛ 45ⴗ

REV. C

–15–

0.0118 (0.30)

0.0040 (0.10)

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING
PLANE

0.0125 (0.32)

0.0091 (0.23)

8ⴗ
0ⴗ

0.0500 (1.27)

0.0157 (0.40)

PRINTED IN U.S.A.