Analog Devices DAC8043 d Datasheet

12-Bit Serial Input

Multiplying CMOS D/A Converter

DAC8043

FEATURES
12-Bit Accuracy in an 8-Lead PDIP Package
Fast Serial Data Input
Double Data Buffers

±

1/2 LSB Max INL and DNL

Low
Max Gain Error: ±1 LSB

°

Low 5 ppm/
ESD Resistant
Low Cost
Available in Die Form

APPLICATIONS
Autocalibration Systems
Process Control and Industrial Automation
Programmable Amplifiers and Attenuators
Digitally Controlled Filters

GENERAL DESCRIPTION

The DAC8043 is a high accuracy 12-bit CMOS multiplying DAC
in a space-saving 8-lead PDIP package. Featuring serial data
input, double buffering, and excellent analog performance, the
DAC8043 is ideal for applications where PC board space is at a
premium. In addition, improved linearity and gain error perfor­mance permit reduced parts count through the elimination of
trimming components. Separate input clock and load DAC
control lines allow full user control of data loading and analog
output.

The circuit consists of a 12-bit serial-in, parallel-out shift register,
a 12-bit DAC register, a 12-bit CMOS DAC, and control logic.
Serial data is clocked into the input register on the rising edge of
the CLOCK pulse. When the new data word has been clocked
in, it is loaded into the DAC register with the LD input pin.
Data in the DAC register is converted to an output current by
the D/A converter.

The DAC8043’s fast interface timing may reduce timing design
considerations while minimizing microprocessor wait states. For
applications requiring an asynchronous CLEAR function or more
versatile microprocessor interface logic, refer to the PM-7543.

Operating from a single 5 V power supply, the DAC8043 is the
ideal low power, small size, high performance solution to many
application problems. It is available in a PDIP package that is
compatible with auto-insertion equipment.

C Max Tempco

FUNCTIONAL BLOCK DIAGRAM

PIN CONNECTIONS

8-Lead PDIP

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

DAC8043–SPECIFICATIONS

(@ VDD = +5 V; V

ELECTRICAL CHARACTERISTICS

under Absolute Maximum Ratings, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

STATIC ACCURACY

Resolution N 12 Bits
Nonlinearity

Differential Nonlinearity
Gain Error

Gain Tempco

(∆ Gain/∆ Temp)

Power Supply

Rejection Ratio PSRR ∆V
(∆ Gain/∆ V

Output Leakage Current

Zero Scale Error

Input Resistance

AC PERFORMANCE

Output Current

Settling Time

Digital to Analog I

Glitch Energy

Feedthrough Error V

(V

Total Harmonic Distortion

Output Noise Voltage Density

DIGITAL INPUTS

Digital Input

HIGH V

Digital Input

LOW V
Input Leakage Current
Input Capacitance

ANALOG OUTPUTS

Output Capacitance

REF

to I

3

1

OUT

DD

6, 7

8

4, 9

4, 10

)

)

4, 11

4, 11

INL DAC8043G ±1/2 LSB

2

DNL DAC8043F/G ±1 LSB
G

FSE

DAC8043F 1 LSB

TA = 25°C

DAC8043F/G 2 LSB

= Full Temperature Range

T

A

All Grades 2 LSB

4

5

TC

I

LKG

GFS

= ±5% ±0.0006 ±0.002 %/%

DD

TA = 25°C ±5 nA

= Full Temperature Range

T

A

DAC8043F/G ±25 nA

I

ZSE

TA = 25°C 0.03 LSB

= Full Temperature Range

T

A

DAC8043F/G 0.15 LSB

R

IN

t

S

QC

TA = 25°C 0.25 1 µs

= 0 V

V

REF

Load = 100 Ω

OUT

= 13 pF 2 20 nVs

EXT

DAC Register Loaded Alternately with
All 0s and All 1s

= 20 V p-p @ f = 10 kHz

REF

FT Digital Input = 0000 0000 0000 0.7 1 mV p-p

T

= 25°C

4

13

4

4, 12

THD V

e

n

IN

IL

I

IL

C

IN

C

OUT

A

= 6 V rms @ 1 kHz –85 dB

REF

DAC Register Loaded with All 1s
10 Hz to 100 kHz between RFB and I

VIN = 0 V to +5 V ±1 µA
VIN = 0 V 8 pF

Digital Inputs = V
Digital Inputs = V

= +10 V; I

REF

IH

IL

= GND = 0 V; TA = Full Temperature Range specified

OUT

DAC8043

±5 ppm/°C

71115kΩ

OUT

2.4 V

17 nV/√Hz

0.8 V

110 pF
80 pF

REV. D–2–

DAC8043

ELECTRICAL CHARACTERISTICS

(continued)

DAC8043

Parameter Symbol Conditions Min Typ Max Unit

TIMING CHARACTERISTICS

Data Setup Time t
Data Hold Time t
Clock Pulsewidth High t
Clock Pulsewidth Low t
Load Pulsewidth t
LSB Clock Into Input Register

to Load DAC Register Time t

POWER SUPPLY

Supply Voltage V
Supply Current I

NOTES

1 1

±1/2 LSB = ±0.012% of full scale.

1 2

All grades are monotonic to 12 bits over temperature.

1 3

Using internal feedback resistor.

1 4

Guaranteed by design and not tested.

1 5

Applies to I

1 6

V

= 10 V; all digital inputs = 0 V.

REF

1 7

Calculated from worst-case R

1 8

Absolute temperature coefficient is less than 300 ppm/°C.

1 9

I

load = 100 Ω, C

OUT

constant of the final RC decay.

10

V

= 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.

REF

11

All digit inputs = 0 V.

12

Calculations from en = √4K TRB where: K = Boltzmann constant, J/°K, R = resistance, Ω, T = resistor temperature, °K, B = bandwidth, Hz.

13

Digital inputs are CMOS gates; IIN is typically 1 nA at 25°C.

14

Tested at VIN = 0 V or VDD.

Specifications subject to change without notice.

; all digital inputs = 0 V.

OUT

EXT

4, 14

DS

DH

CH

CL

LD

ASB

DD

DD

: I

(in LSBs) = (R

REF

ZSE

= 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB; tS = propagation delay (tPD) + 9τ where τ = measured time

TA = Full Temperature Range 40 ns
TA = Full Temperature Range 80 ns
TA = Full Temperature Range 90 ns
TA = Full Temperature Range 120 ns
TA = Full Temperature Range 120 ns

TA = Full Temperature Range 0 ns

4.75 5 5.25 V
Digital Inputs = VIH or V
Digital Inputs = 0 V or V

× I

REF

× 4096)/V

LKG

REF

IL

DD

.

500 µA max
100 µA max

WAFER TEST LIMITS

(@ VDD = 5 V, V

= 10 V; I

REF

= GND = 0 V, TA = 25ⴗC.)

OUT

DAC8043GBC

Parameter Symbol Conditions Limit Unit

STATIC ACCURACY

Resolution N 12 Bits min
Integral Nonlinearity INL ±1 LSB max
Differential Nonlinearity DNL ±1 LSB max
Gain Error G

FSE

Power Supply Rejection Ratio PSRR ∆V
Output Leakage Current (I

)I

OUT

LKG

Using Internal Feedback Resistor ±2 LSB max

= ±5% ±0.002 %/% max

DD

Digital Inputs = V

IL

±5 nA max

REFERENCE INPUT

Input Resistance R

IN

7/15 kΩ min/max

DIGITAL INPUTS

Digital Input HIGH V
Digital Input LOW V
Input Leakage Current I

IH

IL

IL

VIN = 0 V to V

DD

2.4 V min

0.8 V max
±1 µA max

POWER SUPPLY

Supply Current I

NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

DD

Digital Inputs = VIN or V
Digital Inputs = 0 V or V

IL

DD

500 µA max
100 µA max

REV. D

–3–

DAC8043

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V

V

REF

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V

V

RFB

Digital Input Voltage Range . . . . . . . . . –0.3 V to V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V

V

IOUT

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

FP Versions . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

GP Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C

Package Type ␪

2

JA

␪

JC

Unit

8-Lead PDIP 96 37 °C/W

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability. Only one absolute maxi­mum rating may be applied at any one time.

2

␪JA is specified for worst-case mounting conditions, i. e., ␪JA is specified for device

in socket for PDIP package.

CAUTION

1. Do not apply voltages higher than VDD or less than GND
potential on any terminal except V

(Pin 1) and RFB (Pin 2).

REF

2. The digital control inputs are Zener-protected; however,
permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.

3. Use proper antistatic handling procedures.

4. Absolute Maximum Ratings apply to both packaged devices
and DICE. Stresses above those listed under Absolute Maxi­mum Ratings may cause permanent damage to the device.

ORDERING GUIDE*

Model Accuracy Range Option

Relative Temperature Package

DAC8043FP ±1 LSB –40°C to +85°C 8-Lead PDIP
DAC8043GP ±1/2 LSB 0°C to +70°C 8-Lead PDIP

*All commercial and industrial temperature range parts are available with burn-in.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
DAC8043 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. D–4–

Typical Performance Characteristics–DAC8043

TPC 1. Gain vs. Frequency
(Output Amplifier: OP42)

TPC 4. Linearity Error vs.
Digital Code

TPC 2. Total Harmonic
Distortion vs. Frequency
(Multiplying Mode)

TPC 5. Linearity Error vs.
Reference Voltage

TPC 3. Supply Current vs.
Logic Input Voltage

ºS

TPC 6. Logic Threshold
Voltage vs. Supply Voltage

TPC 7. DNL Error vs. Reference
Voltage

REV. D

–5–

DAC8043

PARAMETER DEFINITIONS
Integral Nonlinearity (INL)

This is the single most important DAC specification. ADI mea­sures INL as the maximum deviation of the analog output (from
the ideal) from a straight line drawn between the end points. It
is expressed as a percent of full-scale range or in terms of LSBs.

Refer to PMI 1988 Data Book Section 11 for additional digital­to-analog converter definitions.

Interface Logic Information

The DAC8043 has been designed for ease of operation. The
timing diagram illustrates the input register loading sequence.
Note that the most significant bit (MSB) is loaded first.

Once the input register is full, the data is transferred to the
DAC register by taking LD momentarily low.

DIGITAL SECTION

The DAC8043’s digital inputs, SRI, LD, and CLK, are TTL
compatible. The input voltage levels affect the amount of cur­rent drawn from the supply; peak supply current occurs as the
digital input (V
TPC 3). Maintaining the digital input voltage levels as close as
possible to the supplies, V
rent consumption.

The DAC8043’s digital inputs have been designed with ESD
resistance incorporated through careful layout and the inclusion
of input protection circuitry. Figure 1 shows the input protection
diodes and series resistor; this input structure is duplicated on
each digital input. High voltage static charges applied to the
inputs are shunted to the supply and ground rails through forward
biased diodes. These protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.

GENERAL CIRCUIT INFORMATION

The DAC8043 is a 12-bit multiplying D/A converter with a very
low temperature coefficient. It contains an R-2R resistor ladder
network, data input, control logic, and two data registers.

) passes through the transition region (see

IN

and GND, minimizes supply cur-

DD

Figure 1. Digital Input Protection

The digital circuitry forms an interface in which serial data can be
loaded under microprocessor control into a 12-bit shift register
and then transferred, in parallel, to the 12-bit DAC register.

A simplified circuit of the DAC8043 is shown in Figure 3, which
has an inverted R-2R ladder network consisting of silicon-chrome,
highly stable (50 ppm/°C) thin-film resistors, and twelve pairs of
NMOS current-steering switches.

These switches steer binarily weighted currents into either I

OUT

or
GND; this yields a constant current in each ladder leg, regardless
of digital input code. This constant current results in a constant
input resistance at V

equal to R. The V

REF

input may be driven

REF

by any reference voltage or current, ac or dc, that is within the
limits stated in the Absolute Maximum Ratings.

The twelve output current-steering NMOS FET switches are in
series with each R-2R resistor; they can introduce bit errors if all
are of the same R

resistance value. They were designed so that

ON

the switch ON resistance is binarily scaled so that the voltage
drop across each switch remains constant. If, for example,
Switch 1 of Figure 3 were designed with an ON resistance of
10 Ω, Switch 2 for 20 Ω, and so on, a constant 5 mV drop would
be maintained across each switch.

Figure 2. Write Cycle Timing Diagram

REV. D–6–

DAC8043

To further ensure accuracy across the full temperature range,
permanently ON MOS switches were included in series with the
feedback resistor and the R-2R ladder’s terminating resistor.
The simplified DAC circuit, Figure 3, shows the location of the
series switches. These series switches are equivalently scaled to
two times Switch 1 (MSB) and to Switch 12 (LSB), respectively,
to maintain constant relative voltage drops with varying tempera­ture. During any testing of the resistor ladder or R

FEEDBACK

(such as incoming inspection), VDD must be present to turn
ON these series switches.

DYNAMIC PERFORMANCE
Output Impedance

The DAC8043’s output resistance, as in the case of the output
capacitance, varies with the digital input code. This resistance,
looking back into the I

terminal, may be between 10 kΩ (the

OUT

feedback resistor alone when all digital inputs are low) and

7.5 kΩ (the feedback resistor in parallel with approximately 30 kΩ
of the R-2R ladder network resistance when any single bit logic
is high). Static accuracy and dynamic performance will be
affected by these variations. This variation is best illustrated by
using the circuit of Figure 5 and the equation

VV

ERROR OS



=+

1






R

FB



R



O

where RO is a function of the digital code and

R

= 10 kΩ for more than four bits of Logic 1

O

= 30 kΩ for any single bit of Logic 1

R

O

Therefore, the offset gain varies as follows:

at code 0011 1111 1111,

VV

ERROR1 OS OS



=+




10
10



Ω

k

=1

2

V



Ω

k



at code 0100 0000 0000,

Figure 3. Simplified DAC Circuit

EQUIVALENT CIRCUIT ANALYSIS

Figure 4 shows an equivalent analog circuit for the DAC8043.
The (D × V
current generated by the DAC. The current source I

)/R current source is code dependent and is the

REF

LKG

consists
of surface and junction leakages and doubles approximately
every 10°C. C

is the output capacitance; it is the result of

OUT

the N-channel MOS switches and varies from 80 pF to 110 pF,
depending on the digital input code. R

is the equivalent output

O

resistance that also varies with digital input code. R is the nominal
R-2R resistor ladder resistance.

Figure 4. Equivalent Analog Circuit

VV

ERROR2 OS OS



=+




10
30



Ω

k

=1

43

V



Ω

k



The error difference is 2/3 VOS.

Since one LSB has a weight (for V
DAC8043, it is clearly important that V

= 10 V) of 2.4 mV for the

REF

be minimized,

OS

either by using the amplifier’s nulling pins or an external nulling
network or by selecting an amplifier with inherently low V
Amplifiers with sufficiently low V

include ADI’s OP77, OP07,

OS

OS

.

OP27, and OP42.

Figure 5. Simplified Circuit

REV. D

–7–

DAC8043

The gain and phase stability of the output amplifier, board
layout, and power supply decoupling all affect the dynamic
performance. The use of a small compensation capacitor may be
required when high speed operational amplifiers are used. It
may be connected across the amplifier’s feedback resistor to
provide the necessary phase compensation to critically damp the
output. The DAC8043’s output capacitance and the R
resistor form a pole that must be outside the amplifier’s unity gain
crossover frequency.

The considerations when using high speed amplifiers are:

1. Phase compensation (see Figures 6 and 7).

2. Power supply decoupling at the device socket and the use of
proper grounding techniques.

APPLICATIONS INFORMATION
Application Tips

In most applications, linearity depends upon the potential of
I

and GND (Pins 3 and 4) being equal to each other. In

OUT

most applications, the DAC is connected to an external op amp
with its noninverting input tied to ground (see Figures 6 and 7).
The amplifier selected should have a low input bias current and
low drift over temperature. The amplifier’s input offset voltage
should be nulled to less than 200 µV (less than 10% of 1 LSB).

The operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias current
compensation resistor should not be used. This resistor can cause
a variable offset voltage appearing as a varying output error. All
grounded pins should tie to a single common ground point, avoid­ing ground loops. The V

power supply should have a low noise

DD

level with no transients greater than 17 V.

Unipolar Operation (2-Quadrant)

The circuit shown in Figures 6 and 7 may be used with an ac or
dc reference voltage. The circuit’s output will range between
0 V and approximately –V

(4095/4096), depending upon the

REF

digital input code. The relationship between the digital input
and the analog output is shown in Table I. The limiting
parameters for the V

range are the maximum input voltage

REF

range of the op amp or ±25 V, whichever is lowest.

Figure 6. Unipolar Operation with High Accuracy
Op Amp (2-Quadrant)

FB

Figure 7. Unipolar Operation with Fast Op Amp
and Gain Error Trimming (2-Quadrant)

Gain error may be trimmed by adjusting R1, as shown in Figure 7.
The DAC register must first be loaded with all 1s. R1 may then
be adjusted until V
adjustable V

, R1 and R2 may be omitted, with V

REF

OUT

= –V

(4095/4096). In the case of an

REF

adjusted to

REF

yield the desired full-scale output.

In most applications, the DAC8043’s negligible zero-scale error
and very low gain error permit the elimination of the trimming
components (R

and the external R2) without adversely affecting

1

on circuit performance.

Table I. Unipolar Code Table

Digital Input Nominal Analog Output
MSB LSB (V

1111 1111 1111

1000 0000 0001

1000 0000 0000

0111 1111 1111

0000 0000 0001

0000 0000 0000

NOTES

1. Nominal full scale for Figures 6 and 7 circuits is given by

FS V

2. Nominal LSB magnitude for Figures 6 and 7 circuits is given by

LSB V or V

=

as Shown in Figures 6 and 7)

OUT





V

REF

V

REF

REF

V

REF

V

REF

REF

=−






4096

4095





4096









2049





4096









2048


















REF

1

=−V



4096 2




2047



4096




1



4096




0

=V



4096





4095



4096








V

REF

0






−

2

()

−

−

−

−

−

−

REF REF

n

REV. D–8–

DAC8043

Table II. Bipolar (Offset Binary) Code Table

Digital Input Nominal Analog Output
MSB LSB (V

1111 1111 1111

1000 0000 0001

as Shown in Figure 8)

OUT





+

+

2047

V

REF





2048









REF



2048



1




V

1000 0000 0000 0





REF

REF

REF














2047




2048








1

2048

2047
2048

2048
2048

1

2048
























−

0111 1111 1111

V

−

0000 0000 0001

V

−

0000 0000 0000

V

NOTES

1. Nominal full scale for Figure 8 circuit is given by

FS V

=

REF

2. Nominal LSB magnitude for Figure 8 circuit is given by

LSB V

=

REF

Bipolar Operation (4-Quadrant)

Figure 8 details a suggested circuit for bipolar, or offset binary,
operation. Table II shows the digital input to analog output rela­tionship. The circuit uses offset binary coding. Twos complement
code can be converted to offset binary by software inversion of the
MSB or by the addition of an external inverter to the MSB input.

Resistors R3, R4, and R5 must be selected to match within 0.01%,
and they all must be of the same (preferably metal foil) type to
ensure temperature coefficient matching. Mismatching between

and R4 causes offset and full-scale errors, while an R5 to R

R

3

4

and R3 mismatch will result in full-scale error.

Calibration is performed by loading the DAC register with
1000 0000 0000 and adjusting R
may be omitted, adjusting the ratio of R3 to R4 to yield V

until V

1

= 0 V. R1 and R

OUT

OUT

2

=
0 V. Full scale can be adjusted by loading the DAC register with
1111 1111 1111 and either adjusting the amplitude of V
the value of R

until the desired V

5

is achieved.

OUT

REF

or

Analog/Digital Division

The transfer function for the DAC8043 connected in the multi­plying mode, as shown in Figures 6, 7, and 8, is



AA A A

VV

=− +++

OIN

11223




22 2 2

3

...



12



12



where AX assumes a value of 1 for an ON bit and 0 for an OFF
bit.

The transfer function is modified when the DAC is connected in
the feedback of an operational amplifier, as shown in Figure 9
and becomes




V

=

O



AA A A

112



+++



233

22 2 2

V

−

IN

...






12



4



The above transfer function is the division of an analog voltage

) by a digital word. The amplifier goes to the rails with all

(V

REF

bits OFF since division by zero is infinity. With all bits ON the
gain is 1 (±1 LSB). The gain becomes 4096 with the LSB, bit
12, ON.

REV. D

Figure 8. Bipolar Operation (4-Quadrant, Offset Binary)

–9–

DAC8043

Figure 9. Analog/Digital Divider

Interfacing to the MC6800

As shown in Figure 10, the DAC8043 may be interfaced to the
6800 by successively executing memory WRITE instructions
while manipulating the data between WRITEs, so that each
WRITE presents the next bit.

In this example the most significant bits are found in memory
location 0000 and 0001. The four MSBs are found in the lower
half of 0000, the eight LSBs in 0001. The data is taken from the
DB

line.

7

The serial data loading is triggered by the CLK pulse, which is
asserted by a decoded memory WRITE to memory location
2000, R/W, and φ2. A WRITE to address 4000 transfers data
from the input register to the DAC register.

DAC8043 Interface to the 8085

The DAC8043’s interface to the 8085 microprocessor is shown
in Figure 11. Note that the microprocessor’s SOD line is used
to present data serially to the DAC.

Data is clocked into the DAC8043 by executing memory WRITE
instructions. The clock input is generated by decoding address
8000 and WR. Data is loaded into the DAC register with a
memory write instruction to address A000.

Serial data supplied to the DAC8043 must be present in the right
justified format in Registers H and L of the microprocessor.

Figure 11. DAC8043 to 8085 Interface

DAC8043 to the 68000 Interface

The DAC8043 interfacing to the 68000 microprocessor is shown
in Figure 12. Again, serial data to the DAC is taken from one of
the microprocessor’s data bus lines.

Figure 10. DAC8043 to MC6800 Interface

Figure 12. DAC8043 to 68000 µP Interface

REV. D–10–

OUTLINE DIMENSIONS

8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

Dimensions shown in inches and (millimeters)

0.375 (9.53)

0.365 (9.27)

0.355 (9.02)

8

1

0.100 (2.54)

0.180
(4.57)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AA

BSC

5

4

0.295 (7.49)

0.285 (7.24)

0.275 (6.98)

0.015
(0.38)
MIN

SEATING
PLANE

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

DAC8043

REV. D

–11–

DAC8043

Revision History

Location Page

3/03—Data Sheet changed from REV. C to REV. D.

Deleted 8-Lead CIRDIP and 16-Lead Wide-Body SOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Figures renumbered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Deleted to DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

C00271–0–3/03(D)

–12–

REV. D