Datasheet DAC8043 Datasheet (Analog Devices)

12-Bit Serial Input
a
FEATURES 12-Bit Accuracy in an 8-Pin Mini-DIP Fast Serial Data Input Double Data Buffers Low 61/2 LSB Max INL and DNL Max Gain Error: 61 LSB Low 5 ppm/8C Max Tempco ESD Resistant Low Cost Available in Die Form
APPLICATIONS Autocalibration Systems Process Control and Industrial Automation Programmable Amplifiers and Attenuators Digitally-Controlled Filters
GENERAL DESCRIPTION
The DAC8043 is a high accuracy 12-bit CMOS multiplying DAC in a space-saving 8-pin mini-DIP package. Featuring serial data input, double buffering, and excellent analog performance, the DAC8043 is ideal for applications where PC board space is at a premium. Also, improved linearity and gain error performance permit reduced parts count through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output.
The circuit consists of a 12-bit serial-in, parallel-out shift regis­ter, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the pin. Data in the DAC register is converted to an output current by the D/A converter.
The DAC8043’s fast interface timing may reduce timing design considerations while minimizing microprocessor wait states. For applications requiring an asynchronous CLEAR function or more versatile microprocessor interface logic, refer to the PM-7543.
Operating from a single +5 V power supply, the DAC8043 is the ideal low power, small size, high performance solution to many application problems. It is available in plastic and cerdip packages that are compatible with auto-insertion equipment.
LD input
DAC8043
FUNCTIONAL BLOCK DIAGRAM
PIN CONNECTIONS
8-Pin Epoxy DIP
(P-Suffix)
8-Pin Cerdip
(Z-Suffix)
16-Lead Wide-Body SOL
(S-Suffix)
1
N.C.
2
N.C.
V
3
REF
R
4
FB
I
5
OUT
(Not to Scale)
6
GND
7
GND
8
N.C.
NC = NO CONNECT
DAC8043
TOP VIEW
16
N.C.
15
N.C.
14
V
DD
13
CLK
12
SRI
11
LD N.C.
10
9
N.C.
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
DAC8043–SPECIFICA TIONS
(@ VDD = +5 V; V
ELECTRICAL CHARACTERISTICS
specified under Absolute Maximum Ratings unless otherwise noted).
Parameter Symbol Conditions Min Typ Max Units
STATIC ACCURACY
Resolution N 12 Bits Nonlinearity INL DAC8043A/E/G ±1/2 LSB
(Note 1) DAC8043F 1 LSB
Differential Nonlinearity DNL DAC8043A/E ±1/2 LSB
(Note 2) DAC8043F/G ±1 LSB
Gain Error G
FSE
(Note 3) DAC8043A/E 1 LSB
Gain Tempco
( Gain/ Temp) TC
GFS
(Note 5)
Power Supply
Rejection Ratio PSRR V ( Gain/ V
Output Leakage Current I
DD
)
LKG
(Note 4) T
Zero Scale Error I
ZSE
(Notes 7, 12) T
Input Resistance
(Note 8) R
IN
AC PERFORMANCE
Output Current
Settling Time t
S
(Notes 5, 6)
Digital to Analog I
Glitch Energy Q C (Note 5, 10) DAC Register Loaded Alternately with
Feedthrough Error V
to I
(V
REF
) FT Digital Input = 0000 0000 0000 0.7 1 mV p-p
OUT
(Note 5, 11) T
Total Harmonic Distortion THD V
(Note 5) DAC Register Loaded with All 1s
Output Noise Voltage Density e
n
(Note 5, 13)
DIGITAL INPUTS
Digital Input
HIGH V
IN
Digital Input
LOW V
Input Leakage Current I
IL
IL
(Note 9)
Input Capacitance C
IN
(Note 5, 11)
ANALOG OUTPUTS
Output Capacitance C
OUT
(Note 5) Digital Inputs = V
TA = +25°C
DAC8043F/G 2 LSB
= Full Temperature Range
T
A
All Grades 2 LSB
= ±5% ±0.0006 ±0.002 %/%
DD
TA = +25°C ± 5nA
= Full Temperature Range
A
DAC8043A ±100 nA DAC8043E/F/G ±25 nA
TA = +25°C 0.03 LSB
= Full Temperature Range
A
DAC8043A 0.61 LSB DAC8043E/F/G 0.15 LSB
TA = +25°C 0.25 1 µs
= 0 V
V
REF
Load = 100
OUT
= 13 pF 2 20 nVs
EXT
All 0s and All 1s
= 20 V p-p @ f = 10 kHz
REF
= +25°C
A
= 6 V rms @ 1 kHz –85 dB
REF
10 Hz to 100 kHz between RFB and I
VIN = 0 V to +5 V ±1 µA
VIN = 0 V 8 pF
Digital Inputs = V
= +10 V; I
REF
IH IL
= GND = 0 V; TA = Full Temperature Range
OUT
DAC8043
±5 ppm/°C
71115k
OUT
2.4 V
17 nV/Hz
0.8 V
110 pF 80 pF
–2–
REV. C
DAC8043
DAC8043
Parameter Symbol Conditions Min Typ Max Units
TIMING CHARACTERISTICS (NOTES 5, 14)
Data Setup Time t Data Hold Time t Clock Pulse Width High t Clock Pulse Width Low t Load Pulse Width t
DS DH CH CL LD
LSB Clock Into Input Register
to Load DAC Register Time t
ASB
POWER SUPPLY
Supply Voltage V Supply Current I
NOTES
11
±1/2 LSB = ± 0.012% of full scale.
12
All grades are monotonic to 12-bits over temperature.
13
Using internal feedback resistor.
14
Applies to I
15
Guaranteed by design and not tested.
16
I
Load = 100 , C
OUT
constant of the final RC decay.
17
V
= +10 V, all digital inputs = 0 V.
REF
18
Absolute temperature coefficient is less than +300 ppm/ °C.
19
Digital inputs are CMOS gates; IIN is typically 1 nA at +25°C.
10
V
= 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.
REF
11
All digit inputs = 0 V.
12
Calculated from worst case R
13
Calculations from en = 4K TRB where: K = Boltzmann constant, J/ °K, R = resistance, , T = resistor temperature, °K, B = bandwidth, Hz.
14
Tested at VIN = 0 V or VDD.
Specifications subject to change without notice.
; All digital inputs = 0 V.
OUT
= 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to 1/2 LSB; tS = propagation delay (tPD) + 9τ where τ = measured time
EXT
REF
: I
DD
DD
(in LSBs) = (R
ZSE
TA = Full Temperature Range 40 ns TA = Full Temperature Range 80 ns TA = Full Temperature Range 90 ns TA = Full Temperature Range 120 ns TA = Full Temperature Range 120 ns
TA = Full Temperature Range 0 ns
4.75 5 5.25 V Digital Inputs = VIH or V Digital Inputs = 0 V or V
× I
REF
× 4096)/V
LKG
REF
IL DD
.
500 µA max 100 µA max
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+17 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
REF
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
RFB
Digital Input Voltage Range . . . . . . . . . . . . . . . –0.3 V to V
Output Voltage (Pin 3) . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD DD
Operating Temperature Range
AZ Versions . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
EZ/FZ/FP Versions . . . . . . . . . . . . . . . . . . .–40°C to +85°C
GP Version . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
Package Type uJA* u
JC
Units
8-Pin Hermetic DIP (Z) 134 12 °C/W 8-Pin Plastic DIP (P) 96 37 °C/W
*uJA is specified for worst case mounting conditions, i. e., uJA is specified for device
in socket for cerdip and P-DIP packages.
CAUTION
1. Do not apply voltages higher than VDD or less than GND po­tential on any terminal except V
(Pin 1) and RFB (Pin 2).
REF
2. The digital control inputs are Zener-protected; however, per­manent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use.
3. Use proper antistatic handling procedures.
4. Absolute Maximum Ratings apply to both packaged devices and DICE. Stresses above those listed under Absolute Maxi­mum Ratings may cause permanent damage to the device.
ORDERING GUIDE
Model Accuracy Range Option
DAC8043AZ2±1/2 LSB –55°C to +125°C 8-Pin Cerdip DAC8043AZ/8832± 1/2 LSB –55°C to +125°C 8-Pin Cerdip DAC8043EZ ± 1/2 LSB –40°C to +125°C 8-Pin Cerdip DAC8043FS ±1 LSB –40°C to +85°C 16-Lead (Wide) SOL DAC8043FZ ±1 LSB –40°C to +85°C 8-Pin Cerdip DAC8043FP ±1 LSB –40°C to +85°C 8-Pin Epoxy DIP DAC8043GP ±1/2 LSB 0°C to +70°C 8-Pin Epoxy DIP DAC8043HP ± 1 LSB 0°C to +70°C 8-Pin Epoxy DIP
NOTES
1
All commercial and industrial temperature range parts are available with burn-in.
2
For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet.
Relative Temperature Package
1
REV. C
–3–
DAC8043
WARNING!
ESD SENSITIVE DEVICE
W AFER TEST LIMITS
@ VDD = +5 V, V
= +10 V; I
REF
= GND = 0 V, TA = +258C.
OUT
DAC8043GBC
Parameter Symbol Conditions Limit Units
STATIC ACCURACY
Resolution N 12 Bits min Integral Nonlinearity INL ±1 LSB max Differential Nonlinearity DNL ±1 LSB max Gain Error G
FSE
Power Supply Rejection Ratio PSRR V Output Leakage Current (I
)I
OUT
LKG
Using Internal Feedback Resistor ±2 LSB max
= ±5% ±0.002 %/% max
DD
Digital Inputs = V
IL
±5 nA max
REFERENCE INPUT
Input Resistance R
IN
7/15 k min/max
DIGITAL INPUTS
Digital Input HIGH V Digital Input LOW V Input Leakage Current I
IH IL
IL
VIN = 0 V to V
DD
2.4 V min
0.8 V max ±1 µA max
POWER SUPPLY
Supply Current I
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
DD
Digital Inputs = VIN or V Digital Inputs = 0 V or V
IL DD
500 µA max 100 µA max
DICE CHARACTERISTICS
1. V
REF
2. R
FB
3. I
OUT
4. GND
LD
5.
6. SRI
7. CLK
8. V
DD
Substate (die backside) is internally connected to VDD.
DIE SIZE 0.116 × 0.109 inch, 12,644 sq. mils (2.95 × 2.77 mm, 8.17 sq. mm)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8043 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. C
TYPICAL PERFORMANCE CHARACTERISTICS
DAC8043
Gain vs. Frequency (Output Amplifier: OP42)
Supply Current vs. Logic Input Voltage
Total Harmonic Distortion vs. Frequency (Multiplying Mode)
Linearity Error vs. Digital Code
Linearity Error vs. Reference Voltage
REV. C
Logic Threshold Voltage vs. Supply Voltage
DNL Error vs. Reference Voltage
–5–
DAC8043
PARAMETER DEFINITIONS
INTEGRAL NONLINEARITY (INL)
This is the single most important DAC specification. ADI mea­sures INL as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed as a percent of full-scale range or in terms of LSBs.
Refer to PMI 1988 Data Book section 11 for additional digital­to-analog converter definitions.
INTERFACE LOGIC INFORMATION
The DAC8043 has been designed for ease of operation. The timing diagram illustrates the input register loading sequence. Note that the most significant bit (MSB) is loaded first.
Once the input register is full, the data is transferred to the DAC register by taking
DIGITAL SECTION
The DAC8043’s digital inputs, SRI, LD, and CLK, are TTL compatible. The input voltage levels affect the amount of cur­rent drawn from the supply; peak supply current occurs as the digital input (V
IN
Supply Current vs. Logic Input Voltage graph located under the typical performance characteristics curves. Maintaining the digi­tal input voltage levels as close as possible to the supplies, V and GND, minimizes supply current consumption.
The DAC8043’s digital inputs have been designed with ESD re­sistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 1 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. High voltage static charges applied to the in­puts are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions.
GENERAL CIRCUIT INFORMATION
The DAC8043 is a 12-bit multiplying D/A converter with a very low temperature coefficient. It contains an R-2R resistor ladder network, data input and control logic, and two data registers.
LD momentarily low.
) passes through the transition region. See the
DD
Figure 1. Digital Input Protection
The digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift regis­ter and then transferred, in parallel, to the 12-bit DAC register.
A simplified circuit of the DAC8043 is shown in Figure 2. An inverted R-2R ladder network consisting of silicon-chrome, highly-stable (+50 ppm/°C) thin-film resistors, and twelve pairs of NMOS current-steering switches.
These switches steer binarily weighted currents into either I
OUT
or GND; this yields a constant current in each ladder leg, regard­less of digital input code. This constant current results in a con­stant input resistance at V
equal to R. The V
REF
input may
REF
be driven by any reference voltage or current, ac or dc that is within the limits stated in the Absolute Maximum Ratings.
The twelve output current-steering NMOS FET switches are in series with each R-2R resistor, they can introduce bit errors if all are of the same R
resistance value. They were designed such
ON
that the switch “ON” resistance be binarily scaled so that the voltage drop across each switch remains constant. If, for ex­ample, switch 1 of Figure 2 was designed with an “ON” resis­tance of 10 , switch 2 for 20 , etc., a constant 5 mV drop will then be maintained across each switch.
Write Cycle Timing Diagram
–6–
REV. C
DAC8043
1+
10k 10k
 
 
To further insure accuracy across the full temperature range, permanently “ON” MOS switches were included in series with the feedback resistor and the R-2R ladder’s terminating resistor. The “Simplified DAC Circuit,” Figure 2, shows the location of the series switches. These series switches are equivalently scaled to two times switch 1 (MSB) and to switch 12 (LSB) respec­tively to maintain constant relative voltage drops with varying temperature. During any testing of the resistor ladder or R
FEEDBACK
(such as incoming inspection), VDD must be present
to turn “ON” these series switches.
DYNAMIC PERFORMANCE
OUTPUT IMPEDANCE
The DAC8043’s output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the I
terminal, may be between 10 k (the
OUT
feedback resistor alone when all digital inputs are LOW) and
7.5 k (the feedback resistor in parallel with approximate 30 k of the R-2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be af­fected by these variations.
This variation is best illustrated by using the circuit of Figure 4 and the equation:
R
FB
V
ERROR
= V
OS
1+
R
O
where RO is a function of the digital code, and:
= 10 k for more than four bits of logic 1.
R
O
R
= 30 k for any single bit of logic 1.
O
Therefore, the offset gain varies as follows:
at code 0011 1111 1111,
V
ERROR1
= VOS
= 2 V
OS
at code 0100 0000 0000,
Figure 2. Simplified DAC Circuit
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows an equivalent analog circuit for the DAC8043. The (D × V current generated by the DAC. The current source I
)/R current source is code dependent and is the
REF
consists
LKG
of surface and junction leakages and doubles approximately ev­ery 10°C. C
is the output capacitance; it is the result of the
OUT
N-channel MOS switches and varies from 80 pF to 110 pF depending on the digital input code. R
is the equivalent output
O
resistance that also varies with digital input code. R is the nomi­nal R-2R resistor ladder resistance.
Figure 3. Equivalent Analog Circuit
V
ERROR2
= V
OS
1+
10k 30k
= 4/3 V
OS
The error difference is 2/3 VOS. Since one LSB has a weight (for V
the DAC8043, it is clearly important that V
= +10 V) of 2.4 mV for
REF
be minimized,
OS
either using the amplifier’s nulling pins, an external nulling net­work, or by selection of an amplifier with inherently low V Amplifiers with sufficiently low V
include ADI’s OP77, OP07,
OS
OS
.
OP27, and OP42.
Figure 4. Simplified Circuit
REV. C
–7–
DAC8043
The gain and phase stability of the output amplifier, board lay­out, and power supply decoupling will all affect the dynamic performance. The use of a small compensation capacitor may be required when high-speed operational amplifiers are used. It may be connected across the amplifier’s feedback resistor to provide the necessary phase compensation to critically damp the output. The DAC8043’s output capacitance and the R tor form a pole that must be outside the amplifier’s unity gain crossover frequency.
The considerations when using high-speed amplifiers are:
1. Phase compensation (see Figures 5 and 6).
2. Power supply decoupling at the device socket and use of proper grounding techniques.
resis-
FB
Figure 6. Unipolar Operation with Fast Op Amp and Gain Error Trimming (2-Quadrant)
APPLICATIONS INFORMATION
APPLICATION TIPS
In most applications, linearity depends upon the potential of I
and GND (pins 3 and 4) being exactly equal to each other.
OUT
In most applications, the DAC is connected to an external op amp with its noninverting input tied to ground (see Figures 5 and 6). The amplifier selected should have a low input bias cur­rent and low drift over temperature. The amplifier’s input offset voltage should be nulled to less than +200 µV (less than 10% of 1 LSB).
The operational amplifier’s noninverting input should have a minimum resistance connection to ground; the usual bias cur­rent compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output er­ror. All grounded pins should tie to a single common ground point, avoiding ground loops. The V
power supply should
DD
have a low noise level with no transients greater than +17 V.
UNIPOLAR OPERATION (2-QUADRANT)
The circuit shown in Figures 5 and 6 may be used with an ac or dc reference voltage. The circuit’s output will range between 0 V and approximately –V
(4095/4096) depending upon the digital
REF
input code. The relationship between the digital input and
the analog output is shown in Table I. The limiting parameters for the V
range are the maximum input voltage range of the
REF
op amp or ±25 V, whichever is lowest. Gain error may be trimmed by adjusting R
6. The DAC register must first be loaded with all 1s. R then be adjusted until V an adjustable V
, R1 and R2 may be omitted, with V
REF
OUT
= –V
REF
as shown in Figure
1
may
1
(4095/4096). In the case of
ad-
REF
justed to yield the desired full-scale output. In most applications the DAC8043’s negligible zero scale error
and very low gain error permit the elimination of the trimming components (R
and the external R2) without adverse effects on
1
circuit performance.
Table I. Unipolar Code Table
Digital Input Nominal Analog Output MSB LSB (V
1111 1111 1111 –V
1000 0000 0001 –V
1000 0000 0000 –V
0111 1111 1111 –V
0000 0000 0001 –V
0000 0000 0000 –V
NOTES
1
Nominal full scale for the circuits of Figures 5 and 6 is given by
as shown in Figures 5 and 6)
OUT
4095
4096
2049
4096
2048
4096
 
2047
4096
 
4096
 
4096
 
V
REF
= –
2
 
1
 
0
= 0
REF
REF
REF
REF
REF
REF
Figure 5. Unipolar Operation with High Accuracy Op Amp (2-Quadrant)
REF
REF
4095 4096
 
1
4096
 
or V
REF
(2–n).
FS = –V
2
Nominal LSB magnitude for the circuits of Figures 5 and 6 is given by
LSB = V
–8–
REV. C
DAC8043
Table II. Bipolar (Offset Binary) Code Table
Digital Input Nominal Analog Output MSB LSB (V
1111 1111 1111 +V
1000 0000 0001 +V
as Shown in Figure 7)
OUT
2047
 
2048
1
2048
 
REF
REF
1000 0000 0000 0
1
0111 1111 1111 –V
0000 0000 0001 –V
0000 0000 0000 –V
NOTES
1
Nominal full scale for the circuit of Figure 7 is given by
2047
REF
REF

2048

2048
.
1
.
FS = V
2
Nominal LSB magnitude for the circuit of Figure 7 is given by
LSB = V
REF
REF
REF
 
 
2048
2047 2048
2048 2048
 
 
BIPOLAR OPERATION (4-QUADRANT)
Figure 7 details a suggested circuit for bipolar, or offset binary operation. Table II shows the digital input to analog output re­lationship. The circuit uses offset binary coding. Two’s comple­ment code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input.
Resistors R3, R4, and R5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient matching. Mismatching between R R
causes offset and full scale errors while an R5 to R4 and R
4
and
3
3
mismatch will result in full-scale error. Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R be omitted, adjusting the ratio of R
until V
1
= 0 V. R1 and R2 may
OUT
to R4 to yield V
3
OUT
= 0 V. Full scale can be adjusted by loading the DAC register with 1111 1111 1111 and either adjusting the amplitude of V the value of R
until the desired V
5
is achieved.
OUT
REF
or
ANALOG/DIGITAL DIVISION
The transfer function for the DAC8043 connected in the multi­plying mode as shown in Figures 5, 6 and 7 is:
V
= –V
O
A
A
A
1
2
+
IN
+
1
2
2
3
2
2
A
3
12
+...
12
2
where AX assumes a value of 1 for an “ON” bit and 0 for an “OFF” bit.
The transfer function is modified when the DAC is connected in the feedback of an operational amplifier as shown in Figure 8 and becomes:
V
V
=
A
O
1
1
2
IN
A
A
2
+
3
+
2
3
2
2
+...
 
A
12
4
2
The above transfer function is the division of an analog voltage (V
) by a digital word. The amplifier goes to the rails with all
REF
bits “OFF” since division by zero is infinity. With all bits “ON,” the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB, bit 12 “ON.”
REV. C
Figure 7. Bipolar Operation (4-Quadrant, Offset Binary)
–9–
DAC8043
Figure 8. Analog/Digital Divider
INTERFACING TO THE MC6800
As shown in Figure 9, the DAC8043 may be interfaced to the 6800 by successively executing memory WRITE instructions while manipulating the data between WRITEs, so that each WRITE presents the next bit.
In this example the most significant bits are found in memory location 0000 and 0001. The four MSBs are found in the lower half of 0000, the eight LSBs in 0001. The data is taken from the DB
line.
7
The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to memory location 2000, R/ from input register to DAC register.
W, and φ2. A WRITE to address 4000 transfers data
DAC8043 INTERFACE TO THE 8085
The DAC8043’s interface to the 8085 microprocessor is shown in Figure 10. Note that the microprocessor’s SOD line is used to present data serially to the DAC.
Data is clocked into the DAC8043 by executing memory write instructions. The clock input is generated by decoding address 8000 and WR. Data is loaded into the DAC register with a memory write instruction to address A000.
Serial data supplied to the DAC8043 must be present in the right justified format in registers H and L of the microprocessor.
Figure 10. DAC8043-8085 Interface
DAC8043 TO 68000 INTERFACING
The DAC8043 interfacing to the 68000 microprocessor is shown in Figure 11. Again, serial data to the DAC is taken from one of the microprocessor’s data bus lines.
Figure 9. DAC8043–MC6800 Interface
–10–
Figure 11. DAC8043–68000 µP Interface
REV. C
–11–
000000000
–12–
PRINTED IN U.S.A.
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