Datasheet DAC08RC-883C, DAC08Q-883C, DAC08ES, DAC08EQ, DAC08CQ Datasheet (Analog Devices)

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

DAC08

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

8-Bit, High-Speed, Multiplying D/A Converter

(Universal Digital Logic Interface)

FUNCTIONAL BLOCK DIAGRAM

V+

BIAS
NETWORK

CURRENT
SWITCHES

V

REF

(+)

V

REF

(–)

14

15

REFERENCE
AMPLIFIER

V

LC

MSB

B1

B2 B3 B4 B5 B6 B7

LSB

B8

13 1 5 6 7 8 9 10 11 12

V–

3

COMP

16

4
2

I

OUT

I

OUT

DAC08

FEATURES
Fast Settling Output Current: 85 ns
Full-Scale Current Prematched to ⴞ1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% Maximum over

Temperature Range

High Output Impedance and Compliance:

–10 V to +18 V
Complementary Current Outputs
Wide Range Multiplying Capability: 1 MHz Bandwidth
Low FS Current Drift: ⴞ10 ppm/ⴗC
Wide Power Supply Range: ⴞ4.5 V to ⴞ18 V
Low Power Consumption: 33 mW @ ⴞ5 V
Low Cost
Available in Die Form

GENERAL DESCRIPTION

The DAC08 series of 8-bit monolithic digital-to-analog convert­ers provide very high-speed performance coupled with low cost
and outstanding applications flexibility.

Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20-to-1 reference
current range. Matching to within 1 LSB between reference and

full-scale currents eliminates the need for full-scale trimming in
most applications. Direct interface to all popular logic families
with full noise immunity is provided by the high swing, adjust­able threshold logic input.

High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential opera­tion to effectively double the peak-to-peak output swing. In
many applications, the outputs can be directly converted to
voltage without the need for an external op amp.

All DAC08 series models guarantee full 8-bit monotonicity,
and nonlinearities as tight as ± 0.1% over the entire operating
temperature range are available. Device performance is essen­tially unchanged over the ±4.5 V to ±18 V power supply range,
with 33 mW power consumption attainable at ±5 V supplies.

The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.

DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
applications where low cost, high speed and complete input/
output versatility are required.

REV. B

–2–

DAC08–SPECIFICATIONS

DAC08A/H DAC08E DAC08C

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit

Resolution 8 8 8 Bits
Monotonicity 8 8 8 Bits
Nonlinearity NL ± 0.1 ± 0.19 ± 0.39 % FS
Settling Time t

S

To ± 1/2 LSB, 85 135 85 150 85 150 ns
All Bits Switched ON
or OFF, T

A

= 25°C

1

Propagation Delay

Each Bit t

PLH

TA = 25°C

1

35 60 35 60 35 60 ns

All Bits Switched t

PHL

35 60 35 60 35 60 ns

Full-Scale Tempco

1

TCI

FS

± 10 ± 50 ± 10 ± 80 ±10 ± 80 ppm/°C

DAC08E ± 50

Output Voltage

Compliance V

OC

Full-Scale Current

(True Compliance) Change <1/2 LSB, –10 +18 –10 +18 –10 +18 V

R

OUT

> 20 MΩ typ

Full Range Current I

FR4

V

REF

= 10.000 V 1.984 1.992 2.000 1.94 1.99 2.04 1.94 1.99 2.04 mA
R14, R15 = 5.000 kΩ
T

A

= 25°C

Full Range Symmetry I

FRS

I

FR4

– I

FR2

± 0.5 ± 4 ± 1 ± 8 ±2 ± 16 µA

Zero-Scale Current I

ZS

0.1 1 0.2 2 0.2 4 µA

Output Current Range I

OR1

R14, R15 = 5.000 kΩ 2.1 2.1 2.1 mA

I

OR2

V

REF

= +15.0 V,
V– = –10 V
V

REF

= +25.0 V, 4.2 4.2 4.2 mA
V– = –12 V

Output Current Noise I

REF

= 2 mA 25 25 25 nA

Logic Input Levels

Logic “0” V

IL

VLC = 0 V 0.8 0.8 0.8 V

Logic Input “1” V

IL

22 2 V

Logic Input Current V

LC

= 0 V

Logic “0” I

IL

VIN = –10 V to +0.8 V –2 –10 –2 –10 –2 –10 µA

Logic Input “1” I

IH

VIN = 2.0 V to 18 V 0.002 10 0.002 10 0.002 10 µA

Logic Input Swing V

IS

V– = –15 V –10 +18 –10 +18 –10 +18 V

Logic Threshold Range V

THR

VS = ± 15 V

1

–10 +13.5 –10 +13.5 –10 +13.5 V

Reference Bias Current I

15

–1 –3 –1 –3 –1 –3 µA

Reference Input dI/dt R

EQ

= 200 Ω 4 8 4 8 4 8 mA/µs

Slew Rate R

L

= 100 Ω

C

C

= 0 pF See Fast Pulsed Ref. Info Following.

1

Power Supply Sensitivity PSSI

FS+

V+ = 4.5 V to 18 V ± 0.0003 ± 0.01 ± 0.0003 ± 0.01 ± 0.0003 ± 0.01 %∆IO/%∆V+

PSSI

FS–

V– = –4.5 V to –18 V ± 0.002 ± 0.01 ± 0.002 ±0.01 ± 0.002 ± 0.01 %∆IO/%∆V–
I

REF

= 1.0 mA

Power Supply Current I+ VS = ± 5 V, I

REF

= 1.0 mA 2.3 3.8 2.3 3.8 2.3 3.8 mA
I– –4.3 –5.8 –4.3 –5.8 –4.3 –5.8 mA
I+ V

S

= +5 V, –15 V, 2.4 3.8 2.4 3.8 2.4 3.8 mA

I– I

REF

= 2.0 mA –6.4 –7.8 –6.4 –7.8 –6.4 –7.8 mA

I+ V

S

= ±15 V, 2.5 3.8 2.5 3.8 2.5 3.8 mA

I– I

REF

= 2.0 mA –6.5 –7.8 –6.5 –7.8 –6.5 –7.8 mA

Power Dissipation P

D

± 5 V, I

REF

= 1.0 mA 33 48 33 48 33 48 mW
+5 V, –15 V,
I

REF

= 2.0 mA 108 136 103 136 108 136 mW

± 15 V, I

REF

= 2.0 mA 135 174 135 174 135 174 mW

NOTES

1

Guaranteed by design.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

(@ VS = ⴞ15 V, I

REF

= 2.0 mA, –55ⴗC  TA  +125ⴗC for DAC08/08A, 0ⴗC  TA  +70ⴗC

for DAC08E and DAC08H, –40ⴗC to +85ⴗC for DAC08C, unless otherwise noted. Output characteristics refer to both I

OUT

and

I

OUT

.)

REV. B

DAC08

–3–

Package Type ␪

JA

2

␪

JC

Unit

16-Lead Cerdip (Q) 100 16 °C/W
16-Lead Plastic DIP (P) 82 39 °C/W
20-Terminal LCC (RC) 76 36 °C/W
16-Lead SO (S) 111 35 °C/W

NOTES

1

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

2

θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device

in socket for cerdip, Plastic DIP, and LCC packages; θJA is specified for device
soldered to printed circuit board for SO package.

ABSOLUTE MAXIMUM RATINGS

1

Operating Temperature

DAC08AQ, Q . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

DAC08HQ, EQ, CQ, HP, EP . . . . . . . . . . . . 0°C to +70°C

DAC08CP, CS . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature (T

J

) . . . . . . . . . . . . . –65°C to +150°C

Storage Temperature Q Package . . . . . . . . . –65°C to +150°C

Storage Temperature P Package . . . . . . . . . –65°C to +125°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C

V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . V– to V– plus 36 V

V

LC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to V+

Analog Current Outputs (at V

S

– = 15 V) . . . . . . . . . . 4.25 mA

Reference Input (V

14

to V15) . . . . . . . . . . . . . . . . . . . V– to V+

Reference Input Differential Voltage

(V

14

to V15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

Reference Input Current (I

14

) . . . . . . . . . . . . . . . . . . . 5.0 mA

(@ VS = ⴞ15 V, and I

REF

= 2.0 mA, unless otherwise noted. Output

characteristics apply to both I

OUT

and

I

OUT

.)

All Grades

Parameter Symbol Conditions Typical Unit

Reference Input Slew Rate dI/dt 8 mA/µs
Propagation Delay t

PLH

, t

PHL

TA = 25°C, Any Bit 35 ns

Settling Time t

S

To ± 1/2 LSB, All Bits
Switched ON or OFF, 85 ns
TA = 25°C

Specifications subject to change without notice.

TYPICAL ELECTRICAL CHARACTERISTICS

ORDERING GUIDE

1

Temperature Package Package # Parts Per

Model NL Range Description Option Container

DAC08AQ ± 0.10% –55°C to +125°C Cerdip-16 Q-16 25
DAC08AQ

2

/883C ±0.10% –55°C to +125°C Cerdip-16 Q-16 25
DAC08HP ± 0.10% 0°C to 70°C P-DIP-16 N-16 25
DAC08HQ ± 0.10% 0°C to 70°C Cerdip-16 Q-16 25
DAC08Q ± 0.19% –55°C to +125°C Cerdip-16 Q-16 25
DAC08Q

2

/883C ± 0.19% –55°C to +125°C Cerdip-16 Q-16 25
DAC08RC/883C ± 0.19% –55°C to +125°C LCC-20 E-20 55
DAC08EP ± 0.19% 0°C to 70°C P-DIP-16 N-16 25
DAC08EQ ± 0.19% 0°C to 70°C Cerdip-16 Q-16 25
DAC08ES ±0.19% 0°C to 70°C SO-16 R-16A (Narrow Body) 47
DAC08ES-REEL ±0.19% 0°C to 70°C SO-16 R-16A (Narrow Body) 2500
DAC08CP ± 0.39% –40°C to +85°C P-DIP-16 N-16 25
DAC08CQ ± 0.39% 0°C to 70°C Cerdip-16 Q-16 25
DAC08CS ± 0.39% –40°C to +85°C SO-16 R-16A (Narrow Body) 47
DAC08CS-REEL ± 0.39% –40°C to +85°C SO-16 R-16A (Narrow Body) 2500
DAC08NBC ± 0.10% 25°C DICE
DAC08GBC ± 0.19% 25°C DICE
DAC08GRBC ± 0.39% 25°C DICE

NOTES

1

Devices processed in total compliance to MIL-STD-883. Consult factory for 883 data sheet.

2

For availability and burn-in information on SO and PLCC packages, contact your local sales office.

The DAC08 contains 84 transistors. Die size 63 mil x 87 mil = 5,481 square mils.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the DAC08 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

DAC08

–4–

16-Lead Dual-In-Line Package

(Q and P Suffix)

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

V

LC

I

OUT

V–

I

OUT

MSB B1

B2

B3

B4

COMPENSATION

V

REF

(–)

V

REF

(+)

V+

B8 LSB

B7

B6

B5

DAC08RC/883 20-Lead LCC

(RC Suffix)

4

5

6

7

8

18

17

16

15

14

20 19123

9

10 11 12 13

V–

V

REF

(+)

B3

B4NCB5

B6

I

OUT

V

LC

NC

V

REF

(–)

NC = NO CONNECT

COMP

V+

NC

B8 LSB

B7

I

OUT

NC

MSB B1

B2

PIN CONNECTIONS

DICE CHARACTERISTICS

(125°C Tested Dice Available)

1. V

LC

2. I

OUT

3. V–

4. I

OUT

5. BIT 1 (MSB)

6. BIT 2

7. BIT 3

8. BIT 4

9. BIT 5

10. BIT 6

11. BIT 7

12. BIT 8 (LSB)

13. V+

14. V

REF

(+)

15. V

REF

(–)

16. COMP

DIE SIZE 0.087 ⴛ 0.063 inch, 5,270 sq. mils
(2.209 ⴛ 1.60 mm, 3.54 sq. mm)

16-Lead SO

(S Suffix)

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

V+

V

REF

(+)

V

REF

(–)

COMP

V

LC

I

OUT

V–

I

OUT

B8 LSB

B7

B6

B5

B4

B3

B2

B1 MSB

REV. B

DAC08

–5–

DAC08N DAC08G DAC08GR

Parameter Symbol Conditions Limit Limit Limit Unit

Resolution 8 8 8 Bits min
Monotonicity 8 8 8 Bits min
Nonlinearity NL ± 0.1 ± 0.19 ± 0.39 % FS max
Output Voltage V

OC

Full-Scale Current +18 +18 +18 V max

Compliance Change < 1/2 LSB –10 –10 –10 V min

Full-Scale Current I

FS4

or V

REF

= 10.000 V 2.04 2.04 2.04 mA max

I

FS2

R14, R15 = 5.000 kΩ 1.94 1.94 1.94 mA min

Full-Scale Symmetry I

FSS

± 8 ± 8 ± 16 µA max

Zero-Scale Current I

ZS

244µA max

Output Current Range I

FS1

or V– = –10 V,

V

REF

= +15 V 2.1 2.1 2.1 mA min

V– = –12 V,

I

FS2

V

REF

= +25 V 4.2 4.2 4.2 mA min

R

14

, R15 = 5.000 kΩ

Logic Input “0” V

IL

0.8 0.8 0.8 V max

Logic Input “1” V

IH

222V min

Logic Input Current V

LC

= 0 V

Logic “0” I

IL

VIN = –10 V to +0.8 V ± 10 ± 10 ± 10 µA max

Logic “1” I

IH

VIN = +2.0 V to +18 V ± 10 ± 10 ± 10 µA max

Logic Input Swing V

IS

V– = –15 V +18 +18 +18 V max

–10 –10 –10 V min

Reference Bias Current I

15

–3 –3 –3 µA max

Power Supply PSSI

FS+

V+ = +4.5 V to +18 V 0.01 0.01 0.01 % FS/% V max

Sensitivity PSSI

FS–

V– = –4.5 V to –18 V
I

REF

= 1.0 mA

Power Supply Current I+ V

S

= ± 15 V 3.8 3.8 3.8 mA max

I

REF

≤ 2.0 mA –7.8 –7.8 –7.8 µA max

Power Dissipation P

D

VS = ± 15 V 174 174 174 mW max
I

REF

≤ 2.0 mA

NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

(@ VS = ⴞ15 V, I

REF

= 2.0 mA; TA = 25ⴗC, unless otherwise noted. Output characteristics apply to both

I

OUT

and

I

OUT

.)

WAFER TEST LIMITS

REV. B

DAC08

–6–

0V

TYPICAL VALUES:
R

IN

= 5k⍀

+V

IN

= 10V

4

2

14

15 16

OPTIONAL RESISTOR
FOR OFFSET INPUTS

R

L

R

L

R

REF

+V

REF

R

IN

R

EQ

200⍀

R

P

NO CAP

Figure 1. Pulsed Reference Operation

16 15 14 13 12 11 10 9

12345 678

DAC08

C1 R1

C2

+18V

C3

R1 = 9k⍀
C1 = 0.001␮F
C2, C3 = 0.01␮F

–18V MIN

Figure 2. Burn-in Circuit

100mV

1V

200ns

2.5V

0.5V

–0.5mA

I

OUT

–2.5mA

R

EQ

200⍀

R

L

= 100⍀

C

C

= 0

200ns/DIVISION

Figure 3. Fast Pulsed Reference Operation

0mA

1.0mA

2.0mA

(0000|0000) I

REF

= 2mA (1111|1111)

I

OUT

I

OUT

Figure 4. True and Complementary Output Operation

100mV

2V

50ns

50ns/DIVISION

2.4V

0.4V
0V

8␮A

0

5mV

Figure 5. LSB Switching

10mV

50ns

1V

2.4V

LOGIC INPUT

0.4V

OUTPUT –1/2LSB
SETTLING 0V

+1/2LSB

SETTLING TIME FIXTURE
I

FS

= 2mA, RL = 1k⍀

1/2LSB = 4␮A

50ns/DIVISION

ALL BITS SWITCHED ON

Figure 6. Full-Scale Settling Time

REV. B

–7–

Typical Performance Characteristics–DAC08

I

REF

, REFERENCE CURRENT – mA

I

FS

, OUTPUT CURRENT – mA

5.0

0.0

4.0

3.0

2.0

1.0

0.0

1.0 2.0 3.0 4.0 5.0

LIMIT FOR
V– = –15V

TA = T

MIN

TO T

MAX

ALL BITS “HIGH”

LIMIT FOR
V– = –5V

TPC 1. Full-Scale Current vs.
Reference Current

V15, REFERENCE COMMON-MODE VOLTAGE – V

OUTPUT CURRENT – mA

4.0

–14

3.6

3.2

2.8

2.4

0.0
18

2.0

1.6

1.2

0.8

0.4

–10 –6 –22 61014

TA = T

MIN

TO T

MAX

NOTE: POSITIVE COMMON-MODE
RANGE IS ALWAYS (V+) –1.5V

I

REF

= 0.2mA

I

REF

= 1mA

I

REF

= 2mA

V– = –15V V– = –5V V+ = +15V

ALL BITS ON

TPC 4. Reference Amp Common­Mode Range

OUTPUT VOLTAGE – V

OUTPUT CURRENT – mA

4.0

–14

3.6

3.2

2.8

2.4

0.0
18

2.0

1.6

1.2

0.8

0.4

–10 –6 –22 61014

TA = T

MIN

TO T

MAX

I

REF

= 0.2mA

I

REF

= 1mA

I

REF

= 2mA

V– = –15V V– = –5V

ALL BITS ON

TPC 7. Output Current vs. Output
Voltage (Output Voltage Compliance)

IFS, OUTPUT FULL SCALE CURRENT – mA

PROPAGATION DELAY – ns

500

400

300

200

100

0

0.05 0.02 0.1 0.5 2.0

1LSB = 7.8␮A

1LSB = 61nA

10

0.01 0.05 0.2 1.0 5.0

TPC 2. LSB Propagation Delay vs. I

FS

LOGIC INPUT VOLTAGE – V

LOGIC INPUT – ␮A

10.0

–12.0

8.0

6.0

0

4.0

2.0

–8.0 –4.0 0 4.0 8.0 12.0 16.0

TPC 5. Logic Input Current vs. Input
Voltage

TEMPERATURE – ⴗC

OUTPUT VOLTAGE – V

28

24

20

16

12

12

8

4

0

4

8

–50 0 50 100 150

SHADED AREA INDICATES
PERMISSIBLE OUTPUT VOLTAGE
RANGE FOR V– = –15V. I

REF

2.0mA.

FOR OTHER V– OR I

REF

.

SEE OUTPUT CURRENT VS. OUTPUT
VOLTAGE CURVE.

TPC 8. Output Voltage Compliance
vs. Temperature

FREQUENCY – MHz

RELATIVE OUTPUT – dB

10

0.1

8

6

4

2

–14

0.2 0.5 1.0 2.0 10

2

0

–2

–4

–6

–8

–10

–12

1

5.0

CC = 15pF, V

IN

= 2.0V p–p

CENTERED AT +1.0V
LARGE SIGNAL
C

C

= 15pF, V

IN

= 50mV p–p

CENTERED AT +200mV
SMALL SIGNAL

1.

2.

R14 = R15 = 1k⍀
R

L

 500⍀

ALL BITS “ON”
V

R15

= 0V

TPC 3. Reference Input Frequency
Response

TEMPERATURE – ⴗC

V

TH

– V

LC

– V

2.0

–50

1.6

1.2

0

0.8

0.4

0 50 100 150

TPC 6. V

TH

– VLC vs. Temperature

LOGIC INPUT VOLTAGE – V

OUTPUT CURRENT – mA

1.8

1.6

1.4

1.2

0

1.0

0.8

0.6

0.4

0.2

–12 0 4 8 16–8 –412

B1

B3B4

B5

B2

V– = –15V

V– = –5V

I

REF

= 2.0mA

NOTE: B1 THROUGH B8 HAVE IDENTICAL
TRANSFER CHARACTERISTICS. BITS ARE FULLY
SWITCHED WITH LESS THAN 1/2 LSB ERROR, AT
LESS THAN

100mV FROM ACTUAL THRESHOLD.
THESE SWITCHING POINTS ARE GUARANTEED
TO LIE BETWEEN 0.8V AND 2.0V OVER THE
OPERATING TEMPERATURE RANGE

(V

LC

= 0.0V).

TPC 9. Bit Transfer Characteristics

REV. B

DAC08

–8–

V+, POSITIVE POWER SUPPLY – V dc

POWER SUPPLY CURRENT – mA

10

8

7

6

0

5

4

3

2

1

020294 6 8 10 12 14 16 18

I–

I+

ALL BITS “HIGH” OR “LOW”

TPC 10. Power Supply Current vs. V+

V–, NEGATIVE POWER SUPPLY – V dc

POWER SUPPLY CURRENT – mA

10

8

7

6

0

5

4

3

2

1

–0 –20–29–4 –6 –8 –10 –12 –14 –16 –18

BITS MAY BE “HIGH” OR “LOW”

I– WITH I

REF

= 2mA

I– WITH I

REF

= 0.2mA

I+

I– WITH I

REF

= 1mA

TPC 11. Power Supply Current vs. V–

14

15

+V

REF

I

REF

R

REF

I

IN

R

IN

V

IN

V

IN

14

15

R15

(OPTIONAL)

R

REF

+V

REF

HIGH INPUT

IMPEDANCE

+V

REF

MUST BE ABOVE PEAK POSITIVE SWING OF V

IN

R

REF

R15

I

REF

PEAK NEGATIVE SWING OF I

IN

Figure 7. Accommodating Bipolar References

14

15

R

REF

(R14)

R15

I

REF

+V

REF

6789101112

4

2

FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:

V

REF

= 10.000V

R

REF

= 5.000k⍀

R15 = R

REF

CC = 0.01␮F
V

LC

= 0V (GROUND)

5

MSB

B1

B2 B3B4 B5 B6B7

LSB

B8

V

REF

(+)

V

REF

(–)

316131

V–

C

C

COMP

0.1␮F

0.1␮F

V– V+ V

LC

I

O

I

O

IFR =

+V

REF

R

REF

255
256

ⴛ

I

O

+ IO = I

FR

FOR

ALL LOGIC STATES

V+

Figure 8. Basic Positive Reference Operation

BASIC CONNECTIONS

TEMPERATURE – ⴗC

POWER SUPPLY CURRENT – mA

10

9

8

7

6

0

5

4

3

2

1

–50 0 50 100 150

I–

I+

ALL BITS “HIGH” OR “LOW”

I

REF

= 2.0mA

V– = –15V

V+ = +15V

TPC 12. Power Supply Current vs.
Temperature

14

I

REF

= 2.000mA

4

2

MSB

B1

B2 B3B4 B5 B6 B7

LSB

B8

I

O

I

O

5.000k⍀

5.000k⍀

E

O

E

O

FULL RANGE
HALF-SCALE +LSB
HALF-SCALE
HALF-SCALE –LSB
ZERO-SCALE +LSB
ZERO-SCALE

B1

1
1
1
0
0
0

B2

1
0
0
1
0
0

B3

1
0
0
1
0
0

B4

1
0
0
1
0
0

B5

1
0
0
1
0
0

B6

1
0
0
1
0
0

B7

1
0
0
1
0
0

B8

1
1
0
1
1
0

I

O

mA

1.992

1.008

1.000

0.992

0.008

0.000

IOmA

0.000

0.984

0.992

1.000

1.984

1.992

E

O

–9.960
–5.040
–5.000
–4.960
–0.040

0.000

E

O

–0.000
–4.920
–4.960
–5.000
–9.920
–9.860

Figure 9. Basic Unipolar Negative Operation

REV. B

DAC08

–9–

14

15

LOW T.C.

4.5k

⍀

39k

⍀

V

REF

10V

APPROX

5k

⍀

I

REF

(+)

2mA

10k

⍀

POT

1V

Figure 11. Recommended Full-Scale Adjustment Circuit

14

15

R

REF

4

2

I

O

I

O

NOTE
R

REF

SETS IFS; R15 IS FOR

BIAS CURRENT CANCELLATION.

R15

–V

REF

–V

REF

R

REF

I

FS

Figure 12. Basic Negative Reference Operation

14

I

REF

(+) = 2.000mA

4

2

MSB

B1

B2 B3B4 B5 B6 B7

LSB

B8

I

O

I

O

E

O

E

O

10.000k⍀

10.000k⍀

10.000V

POS. FULL RANGE
POS. FULL RANGE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
ZERO-SCALE –LSB
NEG. FULL-SCALE +LSB
NEG. FULL-SCALE

B1

1
1
1
1
0
0
0

B2

1
1
0
0
1
0
0

B3

1
1
0
0
1
0
0

B4

1
1
0
0
1
0
0

B5

1
1
0
0
1
0
0

B6

1
1
0
0
1
0
0

B7

1
1
0
0
1
0
0

B8

1
0
1
0
1
1
0

E

O

–9.920
–9.840
–0.080

0.000
+0.080
+9.920
+10.000

E

O

+10.000
+9.920
+0.160
+0.080

0.000

–9.840
–9.920

Figure 10. Basic Bipolar Output Operation

MSB

B1

B2 B3 B4 B5 B6

LSB

B8

4

2

B7

I

O

I

O

E

O

5.000k⍀

5.0k⍀

10V

REF01*

*OR ADR01

4

2

6

5

V+ V– CCV

LC

10k⍀

+15V –15V

–15V

OP711

+15V

5.0k⍀

15V

V

O

POS. FULL RANGE
ZERO-SCALE
NEG. FULL-SCALE +1 LSB
NEG. FULL-SCALE

B1

1
1
0
0

B2

1
0
0
0

B3

1
0
0
0

B4

1
0
0
0

B5

1
0
0
0

B6

1
0
0
0

B7

1
0
0
0

B8

1
0
1
0

E

O

+4.960

0.000

–4.960
–5.000

Figure 13. Offset Binary Operation

4

2

I

O

I

O

E

O

0 TO +IFR ⴛ R

L

R

L

OP711

IFR = I

REF

255
256

FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4) TO
GROUND.

Figure 14. Positive Low Impedance Output Operation

4

2

I

O

I

O

E

O

0 TO –IFR ⴛ R

L

OP711

I

FR

= I

REF

255
256

R

L

FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4)
TO GROUND.

Figure 15. Negative Low Impedance Output Operation

V

LC

1

TTL, DTL

V

TH

= 1.4V

15V

9.1k⍀

6.2k⍀ 0.1␮F

V

TH

= VLC 1.4V
15V CMOS
V

TH

= 7.6V

V

LC

13k⍀

39k⍀

ECL

“A”

2N3904

3k⍀

2N3904

TO PIN 1

V

LC

6.2k⍀

–5.2V

20k⍀

20k⍀

V+

“A”

2N3904

3k⍀

2N3904

TO PIN 1

V

LC

R3
400␮A

CMOS, HTL, NMOS

TEMPERATURE COMPENSATING VLC CIRCUITS

Figure 16. Interfacing with Various Logic Families

REV. B

DAC08

–10–

APPLICATION INFORMATION
REFERENCE AMPLIFIER SETUP

The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input refer­ence current. The reference current may be fixed or may vary
from nearly zero to 4.0 mA. The full-scale output current is a
linear function of the reference current and is given by:

II

FR REF

=×

255

256

, where I

REF

= I

14

In positive reference applications, an external positive reference
voltage forces current through R14 into the V

REF(+)

terminal
(Pin 14) of the reference amplifier. Alternatively, a negative
reference may be applied to V

REF(–)

at Pin 15; reference current

flows from ground through R14 into V

REF(+)

as in the positive
reference case. This negative reference connection has the advan­tage of a very high impedance presented at Pin 15. The voltage
at Pin 14 is equal to and tracks the voltage at Pin 15 due to the
high gain of the internal reference amplifier. R15 (nominally equal
to R14) is used to cancel bias current errors; R15 may be elimi­nated with only a minor increase in error.

Bipolar references may be accommodated by offsetting V

REF

or
Pin 15. The negative common-mode range of the reference
amplifier is given by: V

CM

– = V– plus (I

REF

× 1 kΩ) plus 2.5 V.

The positive common-mode range is V+ less 1.5 V.

When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction bypassed to
ground with a 0.1 µF capacitor.

For most applications the tight relationship between I

REF

and I

FS

will eliminate the need for trimming I

REF

. If required, full-scale
trimming may be accomplished by adjusting the value of R14, or
by using a potentiometer for R14. An improved method of
full-scale trimming which eliminates potentiometer T.C. effects
is shown in the recommended full-scale adjustment circuit.

Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative com­mon-mode range. The recommended range for operation with
a dc reference current is 0.2 mA to 4.0 mA.

REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS

AC reference applications will require the reference amplifier to
be compensated using a capacitor from Pin 16 to V–. The value
of this capacitor depends on the impedance presented to Pin 14:
for R14 values of 1.0, 2.5 and 5.0 kΩ, minimum values of C

C

are 15, 37 and 75 pF. Larger values of R14 require proportion­ately increased values of C

C

for proper phase margin, so the

ratio of C

C

(pF) to R14 (kΩ) = 15.

For fastest response to a pulse, low values of R14 enabling
small C

C

values should be used. If Pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and slew
rate. For R14 = 1 kΩ and C

C

= 15 pF, the reference amplifier

slews at 4 mA/µs enabling a transition from I

REF

= 0 to I

REF

=

2 mA in 500 ns.

Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This

technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (I

REF

= 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 14 is
200 Ω and C

C

= 0. This yields a reference slew rate of 16 mA/µs,

which is relatively independent of R

IN

and VIN values.

LOGIC INPUTS

The DAC08 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made pos­sible by the large input swing capability, 2 µA logic input
current and completely adjustable logic threshold voltage.
For V– = –15 V, the logic inputs may swing between –10 V
and +18 V. This enables direct interface with 15 V CMOS
logic, even when the DAC08 is powered from a 5 V supply.
Minimum input logic swing and minimum logic threshold
voltage are given by: V– plus (I

REF

× 1 kΩ) plus 2.5 V. The
logic threshold may be adjusted over a wide range by placing
an appropriate voltage at the logic threshold control pin (Pin 1,
V

LC

). The appropriate graph shows the relationship between

V

LC

and VTH over the temperature range, with VTH nominally

1.4 above V

LC

. For TTL and DTL interface, simply ground pin

1. When interfacing ECL, an I

REF

= 1 mA is recommended. For
interfacing other logic families, see preceding page. For general
set-up of the logic control circuit, it should be noted that Pin 1
will source 100 µA typical; external circuitry should be designed
to accommodate this current.

Fastest settling times are obtained when Pin 1 sees a low imped­ance. If Pin 1 is connected to a 1 kΩ divider, for example, it
should be bypassed to ground by a 0.01 µF capacitor.

ANALOG OUTPUT CURRENTS

Both true and complemented output sink currents are provided
where I

O

+

I

O

= IFS. Current appears at the “true” (IO) output
when a “1” (logic high) is applied to each logic input. As the
binary count increases, the sink current at pin 4 increases pro­portionally, in the fashion of a “positive logic” D/A converter.
When a “0” is applied to any input bit, that current is turned
off at Pin 4 and turned on at Pin 2. A decreasing logic count
increases

I

O

as in a negative or inverted logic D/A converter.
Both outputs may be used simultaneously. If one of the outputs
is not required, it must be connected to ground or to a point
capable of sourcing I

FS

; do not leave an unused output pin open.

Both outputs have an extremely wide voltage compliance enabling
fast direct current-to-voltage conversion through a resistor tied
to ground or other voltage source. Positive compliance is 36 V
above V– and is independent of the positive supply. Negative
compliance is given by V– plus (I

REF

× 1 kΩ) plus 2.5 V.

The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.

POWER SUPPLIES

The DAC08 operates over a wide range of power supply voltages
from a total supply of 9 V to 36 V. When operating at supplies
of ± 5 V or less, I

REF

≤ 1 mA is recommended. Low reference
current operation decreases power consumption and increases
negative compliance, reference amplifier negative common-mode

REV. B

DAC08

–11–

range, negative logic input range and negative logic threshold
range; consult the various figures for guidance. For example,
operation at –4.5 V with I

REF

= 2 mA is not recommended
because negative output compliance would be reduced to near
zero. Operation from lower supplies is possible; however, at
least 8 V total must be applied to ensure turn-on of the internal
bias network.

Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required: however, an artificial
ground may be used to ensure logic swings, etc., remain
between acceptable limits.

Power consumption may be calculated as follows:

P

D

= (I+) (V+) + (I–) (V–)

A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states; this is useful in
cryptographic applications and further serves to reduce the size
of the power supply bypass capacitors.

TEMPERATURE PERFORMANCE

The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is low, typically ±10 ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2 LSB.

The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approxi­mately 10% at –55°C; at +125°C an increase of about 15%
is typical.

The reference amplifier must be compensated by using a capacitor
from pin 16 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see “Reference Amplifier Compensation for Multiplying Applica­tions” section.

MULTIPLYING OPERATION

The DAC08 provides excellent multiplying performance with an
extremely linear relationship between I

FS

and I

REF

over a range
of 4 µA to 4 mA. Monotonic operation is maintained over a
typical range of I

REF

from 100 µA to 4.0 mA.

SETTLING TIME

The DAC08 is capable of extremely fast settling times, typically
85 ns at I

REF

= 2.0 mA. Judicious circuit design and careful
board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 35 ns for each of the 8 bits.
Settling time to within 1/2 LSB of the LSB is therefore 35 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 85 ns, thus determining the overall settling time
of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08 including the package is
approximately 15 pF, therefore the output RC time constant
dominates settling time if R

L

> 500 Ω.

Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for I

REF

values. The principal advantage of higher I

REF

values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.

Measurement of settling time requires the ability to accurately
resolve ± 4 µA, therefore a 1 kΩ load is needed to provide
adequate drive for most oscilloscopes. The settling time fix­ture shown in schematic labelled “Settling Time Measurement”
uses a cascade design to permit driving a 1 kΩ load with less
than 5 pF of parasitic capacitance at the measurement node. At
I

REF

values of less than 1.0 mA, excessive RC damping of the
output is difficult to prevent while maintaining adequate sensi­tivity. However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code change
does not require the normal 6.2 time constants to settle to
within ± 0.2% of the final value, and thus settling times may be
observed at lower values of I

REF

.

DAC08 switching transients or “glitches” are very low and may
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time.

Fastest operation can be obtained by using short leads, minimizing
output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and V

LC

terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capacitors
at the supply pins provide full transient protection.

14

15

6789101112

4

2

5

R

REF

13

0.1␮F

+15V

316

I

OUT

V

IN

R15

+V

REF

0.01␮F

–15V

0.1␮F

DAC08

100k⍀ 2k⍀

1k⍀

1␮F

15k⍀

–15V

V

OUT

1X

PROBE

1k⍀

1␮F50␮F

V

L

MINIMUM

CAPACITANCE

+5V

0.1␮F

0V

0V

+0.4V

–0.4V

Q2

FOR TURN-ON, V

L

= 2.7V

FOR TURN-OFF, VL = 0.7V

0.1␮F

V

CL

0.7V

Q1

Figure 17. Settling Time Measurement

REV. B

–12–

C00268–0–2/02(B)

PRINTED IN U.S.A.

DAC08

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edit to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Edits to Figures 14 and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Replacement of SO-16 with R-16A Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

20-Terminal Leadless Chip Carrier (E-20)

TOP

VIEW

0.358 (9.09)

0.342 (8.69)
SQ

1

20

4

9

8

13

19

14

3

18

BOTTOM

VIEW

0.028 (0.71)

0.022 (0.56)

45° TYP

0.015 (0.38)
MIN

0.055 (1.40)

0.045 (1.14)

0.050 (1.27)
BSC

0.075 (1.91)
REF

0.011 (0.28)

0.007 (0.18)
R TYP

0.095 (2.41)

0.075 (1.90)

0.100 (2.54) BSC

0.200 (5.08)
BSC

0.150 (3.81)
BSC

0.075

(1.91)

REF

0.358

(9.09)

MAX

SQ

0.100 (2.54)

0.064 (1.63)

0.088 (2.24)

0.054 (1.37)

16-Lead SO (R-16A)

16 9

81

0.1574 (4.00)

0.1497 (3.80)

0.3937 (10.00)

0.3859 (9.80)

0.050 (1.27)
BSC

PIN 1

0.2440 (6.20)

0.2284 (5.80)

SEATING
PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

8ⴗ
0ⴗ

0.0196 (0.50)

0.0099 (0.25)

ⴛ 45ⴗ

0.0500 (1.27)

0.0160 (0.41)

0.0099 (0.25)

0.0075 (0.19)

16-Lead Cerdip (Q-16)

16

18

9

0.310 (7.87)

0.220 (5.59)

PIN 1

0.005 (0.13) MIN

0.080 (2.03) MAX

15°

0°

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

SEATING
PLANE

0.200 (5.08)
MAX

0.840 (21.34) MAX

0.150
(3.81)
MIN

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.100
(2.54)

BSC

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

16-Lead Plastic DIP (N-16)

16

18

9

PIN 1

0.840 (21.34)

0.745 (18.92)

0.280 (7.11)

0.240 (6.10)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)
MAX

0.022 (0.558)

0.014 (0.356)

0.160 (4.06)

0.115 (2.93)

0.100
(2.54)

BSC

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

0.195 (4.95)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.325 (8.25)

0.300 (7.62)