ANALOG DEVICES AN-799 Service Manual

AN-799

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: [phone] • Fax: [phone] • www.analog.com

ADV202 Test Modes

by Christine Bako

INTRODUCTION

This application note applies to ADV202 engineering
samples that are 0.2 (ES3) or higher, and are branded
as follows:

ADV202xxx

®

SURF

xxxxxx 0.2 or RevE

This application note outlines a series of recommended
procedures and critical information to confi rm correct
hardware confi guration and initialization of the ADV202.
It provides test procedures for direct accesses and
indirect accesses, tests to confi rm correct DMA interface
and JDATA mode operation, and addresses common
problems the user may encounter. Performing these
specifi c register access tests facilitates debugging sys­tems for hardware and software errors.

DIRECT REGISTER ACCESS FUNCTIONALITY/PLL SETTINGS

Direct Register Access Functionality

Correct direct reg iste r ac cess confi rms functionality and
correct timing on the following pins:

HDATA

ACK
RD or WR
CS

ADDR

Note that direct register timing is specifi ed differently
from indirect register accesses. Refer to Figure 3 and
Figure 4 in the ADV202 data sheet.

To p e r f o rm direct register accesses:

• Properly connect the target system to the following
pins on the ADV202:

ADDR<3:0> (up to 16 addresses).
CS (Chip Select).
WE (Write Enable).
RD (Read Enable).
ACK (Acknowledge).

HDATA<15: 0> (read/write 16 -bit data).

HDATA<31:16> (optional extended data bus for 32- bit

accesses).

CFG [2:1] are shared with DREQ0 and DREQ1. The

hardware boot mode as set by the state of the CFG
pins is ignored on present ADV202s. Refer to Figure 3
and Figure 4 in the ADV202 data sheet for correct tim­ing specifi cations in normal host mode operation.

• IRQ
Connecting IRQ to the host is recommended.

• DACK0 and DACK1 must be held high during

confi guration.

• MCLK must be supplied. The PLL registers and
MMODE and BUSMODE do not require a clock input
to be read or written to, but it is recommended to
power up with an MCLK running, otherwise the state
of the HDATA pins is in an unknown state and might
cause contention with other devices connected to
HDATA.

• The target system must hold the state of the input
pins (ADDR, CS, WE, RD, DAC K , and HDATA for
writes) until the ADV202 asserts the ACK signal (goes
LOW). The access is not completed until the ACK is
asserted. Thus, for read operations, the HDATA
should not be sampled until after ACK is asserted.
This is necessary only for asynchronous reads of
the direct registers (normal host mode), and is not
needed for DMA accesses. Refer to Figure 3 and
Figure 4 in the ADV202 data sheet for normal host
mode timing.

PLL Settings

The internal PLL of the ADV202 is extremely fl exible, but
there are rules on what settings are allowed for JCLK
given the external MCLK frequency (for details see
Page 30 of the ADV202 data sheet). JCLK is the internal
frequency derived from the clock input on MCLK pin and
set by the PLL registers.

To e n s ure p roper functionality for specifi c applications,
the internal JCLK frequency needs to be in a certain
range. The following table summarizes the proper PLL
settings for the target application.

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For the tests described in this application note, the set­tings in Table I can be used.

Once the PLL registers are programmed, a delay of
approximately 20 s is needed after which the ADV202
should undergo a reboot procedure as described later
in this document.

Direct Register Read Test

Direct register access is required for all applications.
Use the following procedure to check for correct direct
register access:

1. Apply MCLK input.

2. Power up the ADV202.

3. Undergo a hard reset by asserting the RESET pin
(holding LOW) for several cycles while still applying
MCLK input.

4. Read the direct registers for their correct default value
using normal host mode access. (See Figure 3 in the
ADV202 data sheet.)

Table I. PLL Settings

Video MCLK PLL_HI PLL_LO
Standard Frequency [address = 0xEh] [address = 0xFh]

NTSC/PAL 27 0x0008 0x0004
ITU.R.BT656

525p 27 0x0008 0x0004
SMPTE293M

625p 27 0x0008 0x0004
ITU.R.BT1358

1080i 25 0x0008 0x0006
SMPTE274M

1080i 74.25 0x0008 0x0084
SMPTE274M

1080i 37.125 0x0008 0x0004
SMPTE274M

Direct Register Error States

Common problems encountered at this stage.

Problem: Direct register read does not come up with
correct default values.

Possible cause:

1. DACK0 or DACK1 is no t he ld hig h, and therefore some

contention on the HDATA bus might occur.

2. Use MCLK input on power-up to prevent HDATA b ein g
in an unknown state.

3. Check for the correct PLL settings.

Problem: ACK is never asserted.

Possible cause:

1. Incorrect timing. Refer to Figure 3 in the data sheet.

2. Check for the correct PLL settings.

Table II. Direct Register Reset Values

Direct Address Register Name Register Value Writeable

0x5 EIRQIE 0x0000 yes

0x6 EIRQFLG 0x000F no

0x8 BUSMODE 0x0005 yes

0x9 MMODE 0x0009 yes

0xA STAGE undef yes

0xB IADDR undef yes

0xC IDATA undef yes

0xE PLL_HI 0x0008 yes

0xF PLL_LO 0x0006 yes
0x0003 [for ES3 samples]

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Direct Register Read/Write and Indirect Register Read/ Write

Testing will verify correct functionality of the following:

• Correct direct register reset values

• Correct direct register write accesses

• Correct indirect memory read/write accesses using
indirect registers IDATA, IADDR, STAGE.

The following test procedure checks the reset values
of the direct registers, performs some direct register
writes, and p er forms some simple indirect regis ter
accesses to verify that this interface is functioning prop­erly. These processes are necessary to function correctly
before starting any application - specic conguration.

Register Test Procedure (32-bit)

Using HDATA [31:0] with a 32- bit host processor:

1. Write to PLL_HI and PLL_LO the values specied in

Table I.

2. Wait for 20  s to allow PLL to settle.

3. Initiate a reboot to no boot mode by writing 0x008A

to the BOOT register (address 0xD).

4. Check that the reset values from Registers 5, 6, 8, 9,

E, and F are correct.

5. Write 0x000A to BUSMODE (address 0x8) to enable

32- bit host interface.

6. Write 0x000A to MMODE (address 0x9) to enable

32- bit indirect access capability.

7. Write 0x001B0000 to IADDR (address 0xB) to set

indirect address to internal RAM.

8. Write 0x12345678 to IDATA (address 0xC) to write

data to address 0x001B0000.

9. Write 0x9ABCDEF0 to IDATA (address 0xC) to write

data to address 0x001B0004.

10. Write 0x0F0F0F0F to IDATA (address 0xC) to write

data to address 0x001B0008.

11. Write 0xF0F0F0F0 to IDATA (address 0xC) to write

data to address 0x001B000C.

12. Write 0x001B0000 to IADDR (address 0xB) to set

indirect address to internal RAM.

13. Read 0x12345678 from IDATA (address 0xC) to read

data from address 0x001B0000.

14. Read 0x9ABCDEF0 from IDATA (address 0xC) to

read data from address 0x001B0004.

15. Read 0x0F0F0F0F from IDATA (address 0xC) to read

data from address 0x001B0008.

16. Read 0xF0F0F0F0 from IDATA (address 0xC) to read

data from address 0x001B000C.

REGISTER TEST PROCEDURE (16-BIT)

Using HDATA [15:0] for Data Transfers

In this 16-bit mode, the data readback is half word
swapped. This is due to an auto-increment indirect read
anomaly on the ADV202. The data is written as expected
in big-endian half word order, however the sequence of
the read data is in little -endian half word order.

Another method around this anomaly is to always load
the IADDR register with the desired address before
reading from the IDATA register. Or, the STAGE register
could be used during the reads of the IDATA register.

1. Write to PLL_HI and PLL_LO the values specied in
Table I.

2. Wait for 20  s to allow PLL to settle.

3. Initiate a reboot to no boot mode by writing 0x008A
to the BOOT register (address 0xD).

4. Check that the reset values from Registers 5, 6, 8, 9,
E, and F are correct.

5. Write 0x0015 to BUSMODE (address 0x8) to enable
16- bit host interface (and JDATA).

6. Write 0x0005 to MMODE (address 0x9) to enable
16- bit indirect access capability.

7. Write 0x001B to STAGE (address 0xA).

8. Write 0x0000 to IADDR (address 0xB) to set indirect
address to internal RAM.

9. Write 0x1234 to IDATA (address 0xC) to write data
to address 0x001B0000.

10. Write 0x5678 to IDATA (address 0xC) to write data
to address 0x001B0002.

11. Write 0x9ABC to IDATA (address 0xC) to write data
to address 0x001B0004.

12. Write 0xDEF0 to IDATA (address 0xC) to write data
to address 0x001B0006.

13. Write 0x0F0F to IDATA (address 0xC) to write data
to address 0x001B0008.

14. Write 0x0F0F to IDATA (address 0xC) to write data
to address 0x001B000A.

15. Write 0xF0F0 to IDATA (address 0xC) to write data
to address 0x001B000C.

16. Write 0xF0F0 to IDATA (address 0xC) to write data
to address 0x001B000E.

17. Write 0x001B to STAGE (address 0xA).

18. Write 0x0000 to IADDR (address 0xB) to set indirect
address to RAM location.

19. Read 0x5678 from IDATA (address 0xC) to read data
from address 0x001B0002.

20. Read 0x1234 from IDATA (address 0xC) to read data
from address 0x001B0000.

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