Analog Devices AN-703-pra Application Notes

AN-703

Preliminary Technical Data

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: [phone] • Fax: [phone] • www.analog.com

Driving High Power LEDs

by Yuxin Li, Gang Liu, and Alan Li

INTRODUCTION

The ADP3806 is a switching mode power supply (SMPS)
controller featuring dual loop constant-voltage and
constant-current control; remote and accurate current
sensing; and shutdown and programmable, synchro­nizable switching frequency. For different application
requirements, it can be confi gured in a variety of topologies:
buck, boost, buck-boost, SEPIC, and CUK. This application
note guides the designs of controller circuits for driving
high power LEDs (light emitting diodes) by using the
ADP3806 to achieve an effi ciency of up to 95%.

Before using this application note for designing the cir­cuits, download the ADP3806 data sheet from the ADI
website.

POWERING UP THE ADP3806

The minimum VCC is 6.25 V (undervoltage lockout UVLO
voltage) and the maximum VCC should not exceed 23 V,
which brings the switch driver voltage BST to 30 V, the
junction breakdown voltage. The recommended VCC
range is from 6.5 V to 20 V.

To e n s u r e a clean voltage source at the VCC pin, an RC
bypass network is used between the input source and
the IC. The decoupling capacitor can be in the value
range of 0.1 ␮F to 22 ␮F. The sh u tdown control pin SD
accepts external control logic input. If automatic startup
is preferred, a voltage divider from VCC can be used to
ensure that the voltage at this pin is below its limit, 10 V,
and above its logic high, 2.0 V.

A capacitor connected to the CT pin sets the switching
frequency. Recommended switching frequency is from
300 kHz to 750 kHz for the optimized trade-off between
the overall system physical size and the efficiency.
Higher switching frequency of up to 1 MHz demands
more gate-driving power and generates more switching
losses, resulting in lower effi ciency, while the inductors’
inductance can be scaled down to reduce the system’s
physical size and cost. Another drawback of using a
higher switching frequency is that the duty cycle range is
reduced so that the output voltage range is narrowed.

REG, REF, and BSTREG pins are output pins of three in­ternal low dropout (LDO) regulators. Decouple them with
the recommended capacitors to ensure the stability of
the regulators.

The current sensing resistor along with the voltage at
the ISET pin determines the output current. The required
voltage at the ISET pin should be generated from the

2.5 V precision reference source REF pin. The maximum
output current from the REF pin is 500 ␮A. To generate
a higher setting voltage, the voltage divider can run off
the REG pin (6 V). Note that the accuracy for REF is 1%,
and the accuracy for REG is 3%.

Across CS+ and CS– pins, a fi lter capacitor of about 220 nF
should be placed right next to the pins in the PCB layout
to fi lter out noise.

BUCK CONFIGURATION

To d rive L EDs w ith an output voltage lower than the input
power source voltage, a step-down topology Buck can
be used.

Figure 1 shows the Buck configuration circuit. This
scheme utilizes the synchronous rectification func­tionality of the controller to provide the highest power
conversion effi ciency. The controller and the power
stage can be powered up by either the same or differ­ent power sources. Using the same power source, the
input voltage range should be within the range of 6.5 V
to 20 V. With different power sources, the power stage
input voltage can be as low as 6.5 V, while the maximum
should not exceed 20 V.

Using proper MOSFETs, the output current can go up to
4 A, the sense resistor value, and the ISET voltage. The
output voltage can go from zero up to the power stage
input voltage.

The current sensing resistor, R
to minimize its power loss but high enough to provide
suffi cient signal for the control. The voltage across the
CS+ and CS– pins should be higher than 50 mV to activate
the synchronous rectifi cation function, that is, to switch
the lower MOSFET on and off. When (CS+ – CS–) voltage
is lower than 50 mV, the low-side MOSFET is not turned
on so its body diode conducts, causing extra conduction
loss. At the same time, the energy for driving the lower
MOSFET is saved. When the output current is lowered
far enough, turning off the lower MOSFET may result in
higher overall system effi ciency.

, should be low enough

CS

REV. PrA

AN-703 Preliminary Technical Data

By using the circuit shown in Figure 1, the output current
equals

V

I

LED

ISET

=

R

25

CS

If the current sensing signal in the design is lower than
50 mV, a bias circuit, shown in Figure 2, is needed to fully
activate the synchronous functionality. By using a voltage
divider composed of RB1 and RB2, a bias voltage, V

BIAS

, is
generated at the CS+ pin. Thus, the sensing signal needed
to activate the synchronous rectifi cation function is V
lower than the 50 mV. If V

equals 50 mV, the synchro-

BIAS

BIAS

nous function is effective all the time. With this bias, the
output current is

VV

- 25

LED

=

ISET BIAS

R

25

CS

I

The current limit setting accuracy is obviously a little
lower with this added offset term. Also, the biasing
circuitry should draw minimum current from the VREF
pin, and fi ltering capacitor C4 should now be designed
to make a small enough time constant (recommend 0.3/
f

) with RB2 instead of RCS. Thus, C4 is much smaller

SW

than 200 nF.

The output capacitor, C

, is optional. It smoothes the

OUT

voltage and current across the LEDs.

The input capacitor, C

, is needed to absorb the input ripple

IN

current. Normally, two 10 ␮F/25 V ceramic capacitors are
enough.

The inductor, L, determines the ripple current. It is recom­mended that the ripple current be about one-third of the
nominal output current to optimize both the system size
and the effi ciency. The peak inductor current is there

II

= 115.

LPEAK LEDM

fore,

where:

is the peak current of the inductor.

I

LPEAK

is the maximum average current in the LEDs.

I

LEDM

The inductor should be chosen based on two criteria.
First, the inductor saturation current should be larger
than the maximum peak current, I

, in the inductor.

LPEAK

Second, the inductor’s maximum dc current rating should
be larger than the load dc average current, I

LED

.

The recommended bootstrap capacitance is 10 nF. A

0.5 A Schottky diode is recommended as the bootstrap
diode. This diode must be placed on the PCB as close to
the BST and BSTREG pins as possible.

C

, CCL, and RC compose the loop compensation net-

CH

work of the closed loop. They need to be designed
carefully to ensure system stability and control speed.

The control (duty cycle, d) to inductor current (i

) transfer

L

function is a constant given by

iS

()

L

d

=

25

DV

IN

Rf L

CS SW

where:

D is the duty cycle of the steady state.

is the switching frequency of the power stage.

f

SW

This is valid below half of the switching frequency and
with the assumption that the output voltage is constant.

It is obvious that a simple integrator is adequate to com­pensate the loop with infi nite dc gain. To set a bandwidth
of f

), the compensation component CCL needs to be

C(␻C

gDV

C

CL

MIN

=

Rf L

25 w

CS SW C

where:

= 0.002 is the transconductance of the current loop

g

M

error amplifi er.

R

can be set to zero.

C

can be set to be open.

C

CH

LEDs are not critical to the driving transition, so the sys­tem loop bandwidth can be low. It is recommended that
the bandwidth is designed to be 1/30th of the switching
frequency for the buck confi guration.

MOSFETs can be chosen based on their dc voltage/
current ratings, switching speed (gate charges), and
thermal capability.

Note that the BSTREG regulator needs to provide the
entire gate-driving energy to drive both the high-side
MOSFET and the high- side driver itself. Because the
maximum output current, I
lator is ⱕ 3 mA, the gate charge, Q

, of the BSTREG regu -

BSTREG

, of the high-side

G

MOSFET and the switching frequency should satisfy

IQf

>

BSTREG G SW

If more gate-driving capability is needed, use an external
NPN transistor, QBST, in the emitter follower confi gura­tion (see Figure 2) to deliver more current.

–2–

REV. PrA

Preliminary Technical Data AN-703

VIN7V–20V

C1

R1

22␮F

10⍀

124

VCC

2

R2

100k⍀

CT

C2
100nF

C3
200pF

R3

51k⍀

C

CL

R

C

C

CH

SYS–

3

SYS+

4

ISYS

5

LIMIT

6

CT

7

8

9

10

11

12

ADP3806

SYNC

REG

REF

SD

COMP

LC AGND

SW

DRVH

BST

BSTREG

DRVL

PGND

CS+

CS–

ISET

BATSEL

BAT

C6

23

22

21

20

19

18

17

16

15

14

13

10nF

D1
MBR052

C5
1␮F

C4
200nF

TO SET THE OUTPUT CURRENT

R

CLBRCLT

SW1

SW2

C

IN

L

V

OUT

=0TOV

IN

LED1

C

OUT

LED2

R

CS

Figure 1. Driving LEDs with the ADP3806 in Buck Confi guration

VIN7V–20V

C1

R1

22␮F

10⍀

124

VCC

2

R2

100k⍀

CT

C2
100nF

C3
200pF

R3

51k⍀

C

CL

R

C

C

CH

SYS–

3

SYS+

4

ISYS

5

LIMIT

6

CT

7

8

9

10

11

12

ADP3806

SYNC

REG

REF

SD

COMP

LC AGND

SW

DRVH

BST

BSTREG

DRVL

PGND

CS+

CS–

ISET

BATSEL

BAT

C6

23

22

21

20

19

18

17

16

15

14

13

10nF

QBST

BBMT6428

C5

1␮F

OUTPUT

CURRENT BOOSTER

C4
??

TO SET THE

OUTPUT CURRENT

D1
MBR052

R

CLBRCLT

C

IN

SW1

L

SW2

C

RB2

RB3

RB1

CURRENT SENSING BIAS

OUT

V

OUT

=0TOV

R

CS

IN

LED1

LED2

REV. PrA

Figure 2. Biasing the Current Sensing Input to Accommodate Low Input Signal

–3–