Analog Devices AN-698 Application Notes

AN-698

CLOSED LOOP
MARGINING SYSTEM

DU

AL

FUNCTION

INPUTS

(LOGIC
INPUTS

OR SFDs)

PROGRAMMABLE

RESET

GENERA

TORS

(SFDs)

CONFIGURABLE

OUTPUT

DRIVERS

(HV-CAPABLE

OF DRIVING

GATE OF

N-CHANNEL

FET)

CONFIGURABLE

OUTPUT

DRIVERS

(L

V-CAPABLE

OF DRIVING

LOGIC

SIGNALS)

V

OUT

DAC

V

OUT

DAC

V

OUT

DAC

V

OUT

DAC

V

OUT

DAC

V

OUT

DAC

ADM1066

EEPROM

VDD

ARBITRATO

R

SEQUENCING

ENGINE

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

VH

SFDGND

DAC

1 DAC2 DAC3 DAC4 DAC5 DAC6 GND

VDDCAP

PDOGND

PDO10

PDO9

PDO8

PDO7

PDO6

PDO5

PDO4

PDO3

PDO2

PDO1

AUX1 AUX2 REFIN REFGND SD

A SCL A1 A0REFOUT

MUX

12-BIT

SAR ADC

SMBUS

INTERFAC

E

V

REF

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: [phone] • Fax: [phone] • www.analog.com

Conguration Registers of ADM106x

by Peter Canty

INTRODUCTION

The ADM106x family of fully programmable supply
sequencers and supervisors can be used as complete
supply management solutions in systems using multiple
voltage supplies. Such applications include line cards in
telecommunications infrastructure equipment (central
ofce, base stations) and blade cards in servers.

All of the features of the ADM106x are programmable
through an SMBus interface. The devices also contain
nonvolatile memory (EEPROM) so that the conguration
of these features can be stored on-chip and downloaded
each time on power-up.

This application note briefly outlines the func tions of
the ADM106x, and provides details of the registers
required to set up the conguration of the ADM106x.
The programming windows of the ADM106x graphical
user interface (GUI) based software provided by ADI to
congure these devices is also shown.

For more information on the features and functions of
the ADM106x, please refer to the relevant data sheet.

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Figure 1. ADM1066 Functional Block Diagram

Figure 2. Top Level Menu of ADM106x Software

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POWER-UP

VCC >2.5V

EEPROM

E
E
P

R
O
M

L

D

DEVICE

CONTROLLER

SMBus

LATCH A

D
A
T
A

LATCH B

R
A
M
L
D

U
P
D

FUNCTION (eg)

OV

THRESHOLD

ON VP 1

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UPDATING THE ADM106x

The following pages contain all of the register infor­mation required to congure the many features of the
ADM106x. The ADM106x contains both volatile and non­volatile memory, which must be set up correctly if any
alterations to the conguration are to be updated prop ­erly in the device. The volatile memory of the ADM106x is
constructed with double buffered latches. For information
on this construction, please refer to the data sheet.

The register/bit map detail below shows the congura ­tion required to

• Update volatile memory in real time.

• Update volatile memory off line then update
all at once.

• Enable block erase.

• Download EEPROM contents to RAM.

The sequencing engine also has a number of conguration
bits that are used to update it and are detailed below.

Figure 3. Conguration Update Flow Diagram

Table I.

Reg. Reg. Name Bits Bit Name R/W Description

90H UPDCFG 7:3 Cannot be used.

2 EEBLKERS R/W Enable conguration EEPROM Block Erase.

1 CFGUPD W Update conguration registers from holding registers (self clears).

0 CONTUPD R/W Enable continuous update of conguration registers.

D8H UDOWNLD 7:1 Cannot be used.

0 EEDWNLD W

Download conguration data from EEPROM. This also happens automatically
at power-up. Self clears on completion.

F4 MANID 7:0 R Manufacturer’s ID, returns 0x41. Good method of verifying communication.

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AN-698

ADM106x INPUTS

The ADM106x devices have 10 inputs. Five of these are
dedicated supply fault detectors—highly programmable
reset generators whose inputs can detect overvoltage,
undervoltage, or out- of- window faults. With these ve
inputs, voltages from 0.573 V to 14.4 V can be super­vised. The undervoltage and overvoltage thresholds can
all be programmed to 8- bit resolution. The comparators
used to detect faults on the inputs have digitally pro ­grammable hysteresis to provide immunity to supply
bounce. Each of these inputs also has a glitch lter
whose timeout is programmable up to 100 µs.

The other ve inputs have dual functionality. They can
be used as analog inputs, like the rst ve channels
de

scribed above, or as general - purpose logic inputs. As
analog inputs, these channels function exactly the same
as those described above. The major difference is that
these inputs do not have internal potentiometer resistors
and present a true high impedance to the input pin. Their

input range is thus limited to 0.573 V to 1.375 V, but the
high impedance means that an external resistor divide
network can be used to divide down any out- of-range
sup

ply

to a value within range. Thus, +48 V, +24 V, –5 V,
and –12 V can all be supervised by these channels with
the appropriate ex ternal resistor network.

As digital inputs, these pins can be used to detect enable
signals, PWRGD, POWRON, and so on. They are TTL and
CMOS compatible. When used in this mode, the analog
circuitry of these pins can be mapped to its sister input
pin (one of the rst ve inputs described above). Thus,
VX1 can be used as a second detector on VP1, VX2 can
be used with VP2, and so on. VX5 is mapped to VH.
With a second detector available, the user can program
ALARM as well as fault functions.

Figure 4 shows the GUI window for conguring the
inputs. Table II details all of the registers used to con-

gure the inputs to perform the functions described
above.

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Figure 4. ADM106x Inputs Window

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Table II.

Input Reg. Reg. Name Bits Bit Name R/W Description

VP1 00H PS1OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on PS1 SFD.

01H PS1OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from PS1OVTH when OV is true.

02H PS1UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on PS1 SFD.

03H PS1UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from PS1UVTH when UV is true.

04H SFDV1CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0

0 0 1 5
0 1 0 10
0 1 1 20

1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

05H SFDV1SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Range Select
0 0 Midrange (2.5 V to 6 V)
0 1 Low Range (1.25 V to 3 V)

1 0 Ultralow Range (0.573 V to 1.375 V)
1 1 Ultralow Range (0.573 V to 1.375 V)

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VP2 08H PS2OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on PS2 SFD.

09H PS2OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from PS2OVTH when OV is true.

0AH PS2UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on PS2 SFD.

0BH PS2UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from PS2UVTH when UV is true.

0CH SFDV2CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

0DH SFDV2SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Range Select
0 0 Mid Range (2.5 V to 6 V)
0 1 Low Range (1.25 V to 3 V)
1 0 Ultralow Range (0.573 V to 1.375 V)
1

1 Ultralow Range (0.573 V to 1.375 V)

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VP3 10H PS3OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on PS3 SFD.

11H PS3OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from PS3OVTH when OV is true.

12H PS3UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on PS3 SFD.

13H PS3UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from PS3UVTH when UV is true.

14H SFDV3CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20

1 0 0 30
1 0 1 50

1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select

0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

15H SFDV3SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Range Select
0 0 Midrange (2.5 V to 6 V)
0 1 Low Range (1.25 V to 3V)
1 0 Ultralow Range (0.573 V to 1.375 V)
1 1 Ultralow Range (0.573 V to 1.375 V)

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VP4 18H PS4OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on PS4 SFD.

19H PS4OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from PS4OVTH when OV is true.

1AH PS4UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on PS4 SFD.

1BH PS4UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from PS4UVTH when UV is true.

1CH SFDV4CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0

0 0 1 5
0 1 0 10

0 1 1 20

1 0 0 30
1 0 1 50
1 1 0 75

1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

1DH SFDV4SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Range Select
0 0 Midrange (2.5 V to 6 V)
0 1 Low Range (1.25 V to 3 V)
1 0 Ultralow Range (0.573 V to 1.375 V)
1 1 Ultralow Range (0.573 V to 1.375 V)

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VH 20H PSVHOVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on PSVH SFD.

21H PSVHOVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W
when OV is true.

22H PSVHUVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on PSVH SFD.

23H PSVHUVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from PSVHUVTH
when UV is true.

24H SFDVHCFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

25H SFDVHSEL 7:1 Cannot be used.

0 SEL0 R/W SEL0 Range Select
0 High Range (6.0 V to 14.4 V)
1 Medium Range (2.5 V to 6.0 V)

5-bit hysteresis to be subtracted from PSVHOVTH

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VX1 28H X1OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on X1 SFD.

29H X1OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from X1OVTH when OV is true.

2AH X1UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on X1 SFD.

2BH X1UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from X1UVTH when UV is true.

2CH SFDX1CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

2DH SFDVX1SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Function Select
0 0 SFD (Fault) only
0 1 GPI (Fault) only
1 0 GPI (Fault) + SFD (Warning)
1 1 No Function (input can still

2EH GPIX1CFG 7 Cannot be used.

6 INVIN R/W If High, invert input.

5 INTYP R/W Determines whether a level or an edge is detected on the pin.

INTYP Level/Edge
0 Detect Level
1 Detect Edge

4:3 PULS1–0 R/W

Length of pulse output once an edge has been detected on input.

PULS1 PULS0 Pulse Length (µs)
0 0 10
0 1 100
1 0 1000
1 1 10000

2:0 GF2–GF0 R/W Glitch lter—length of time for which a pulse is ignored.

GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

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be used as ADC input)

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VX2 30H X2OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on X2 SFD.

31H X2OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from X2OVTH when OV is true.
32H X2UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on X2 SFD.

33H X2UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from X2UVTH when UV is true.

34H SFDX2CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

35H SFDVX2SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Function Select
0 0 SFD (Fault) only
0 1 GPI (Fault) only
1 0 GPI (Fault) + SFD (Warning)
1 1 No Function (input can still be used as ADC input)

36H GPIX2CFG 7 Cannot be used.

6 INVIN R/W If High, invert input.

5 INTYP R/W Determines whether a level or an edge is detected on the pin.

INTYP Level/Edge
0 Detect Level
1 Detect Edge

4:3 PULS1–0 R/W Length of pulse output once an edge has been detected on input.

PULS1 PULS0 Pulse Length (µs)
0 0 10
0 1 100
1 0 1000
1 1 10000

2:0 GF2–GF0 R/W Glitch Filter—length of time for which a pulse is ignored.

GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VX3 38H X3OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on X3 SFD.

39H X3OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from X3OVTH when OV is true.

3AH X3UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on X3 SFD.

3BH X3UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from X3UVTH when UV is true.

3CH SFDX3CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

3DH SFDVX3SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Function Select
0 0 SFD (Fault) only
0 1 GPI (Fault) only
1 0 GPI (Fault) + SFD (Warning)
1 1 No Function (input can still

3EH GPIX3CFG 7 Cannot be used.

6 INVIN R/W If High, invert input.

5 INTYP R/W Determines whether a level or an edge is detected on the pin.

INTYP Level/Edge
0 Detect Level
1 Detect Edge

4:3 PULS1–0 R/W

Length of pulse output once an edge has been detected on

PULS1 PULS0 Pulse Length (µs)
0 0 10
0 1 100
1 0 1000
1 1 10000

2:0 GF2–GF0 R/W Glitch lter—length of time for which a pulse is ignored.

GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

be used as ADC input)

input.

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VX4 40H X4OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on X4 SFD.

41H X4OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from X4OVTH when OV is true.

42H X4UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on X4 SFD.

43H X4UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from X4UVTH when UV is true.

44H SFDX4CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

45H SFDVX4SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Function Select
0 0 SFD (Fault) only
0 1 GPI (Fault) only
1 0 GPI (Fault) + SFD (Warning)
1 1 No Function (input can still be used as ADC input)

46H GPIX4CFG 7 Cannot be used.

6 INVIN R/W If High, invert input.

5 INTYP R/W Determines whether a level or an edge is detected on the pin.

INTYP Level/Edge
0 Detect Level
1 Detect Edge

4:3 PULS1–0 R/W Length of pulse output once an edge has been detected on input.

PULS1 PULS0 Pulse Length (µs)
0 0 10
0 1 100
1 0 1000
1 1 10000

2:0 GF2–GF0 R/W Glitch lter—length of time for which a pulse is ignored.

GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

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Table II. (continued)

Input Reg. Reg. Name Bits Bit Name R/W Description

VX5 48H X5OVTH 7:0 OV7–OV0 R/W 8-bit digital value for OV threshold on X5 SFD.

49H X5OVHYST 7:5 Cannot be used.

4:0 HY4–HY0 R/W 5-bit hysteresis to be subtracted from X5OVTH when OV is true.

4AH X5UVTH 7:0 UV7–UV0 R/W 8-bit digital value for UV threshold on X5 SFD.

4BH X5UVHYST 7:5 Cannot be used.

4:0 5-bit hysteresis to be added from X5UVTH when UV is true.

4CH SFDX5CFG 7:5 Cannot be used.

4:2 GF2–GF0 R/W GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20

1 0 0 30
1 0 1 50
1 1 0 75

1 1 1 100

1:0 RS1–RS0 R/W RS1 RS0 Fault Type Select
0 0 OV
0 1 UV or OV
1 0 UV
1 1 Off

4DH SFDVX5SEL 7:2 Cannot be used.

1:0 SEL1–SEL0 R/W SEL1 SEL0 Function Select
0 0 SFD (Fault) only
0 1 GPI (Fault) only
1 0 GPI (Fault) + SFD (Warning)
1 1 No Function (input can still be used as ADC input)

4EH GPIX5CFG 7 Cannot be used.

6 INVIN R/W If High, invert input.

5 INTYP R/W Determines whether a level or an edge is detected on the pin.

INTYP Level/Edge
0 Detect Level
1 Detect Edge

4:3 PULS1–0 R/W Length of pulse output once an edge has been detected on input.

PULS1 PULS0 Pulse Length (µs)
0 0 10
0 1 100
1 0 1000
1 1 10000

2:0 GF2–GF0 R/W Glitch Filter—length of time for which a pulse is ignored.

GF2 GF1 GF0 Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100

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ADM106x OUTPUTS

The ADM106x devices have 10 programmable driver out­puts. Supply sequencing is achieved with the ADM106x
by using the PDOs as control signals for supplies. The
output drivers can either be used as logic enables or
FET drivers.

The PDOs can be used for a number of functions; the
primary function is to provide enable signals for LDOs
or dc /dc convertors which generate supplies locally
on a board. The PDOs can also be used to provide a
POW

ER_GOOD signal when all of the SFDs are in toler­ance, or to provide a RESET output if one of the SFDs
goes out of spec (this can be used as a status signal for
a DSP, FPGA, or other microcontroller).

The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as

• Open drain (allowing the user to connect an
exter

• Open drain with weak pull-up to V

• Push- pull to V

• Open drain with weak pull-up to VPn

• Push- pull to VPn

• Strong pull-down to GND

•

nal pull-up resistor)

DD

DD

Internally charge-pumped high drive (12 V-PDO 1–

6)

The last option (available only on PDOs 1 to 6) allows
the user to directly drive a voltage high enough to fully
enhance an external N-fet, which is used to isolate, for
example, a card - side voltage from a backplane supply (a
PDO sustains greater than 10.5 V into a 1 µA load). The
pull-down switches may be used to drive status LEDs.

The data driving each of the PDOs can come from one of
three sources. The source can be enabled in the PnPDOCFG
conguration register. The data sources are

• An output from the SE.

• Directly from the SMBus. A PDO can be congured
so that the SMBus has direct control over it. This
enables soft ware control of the PDOs. Thus, a
mi

crocontroller could be used to initiate a software

power- up/power-down sequence.

• An On- Chip Clock. A 100 kHz clock is generated on
the device. This clock can be made available on any
of the PDOs. It could be used to clock an external
device such as an LED, for example.

Figure 5 shows the GUI window for conguring the in
Table III details all of the registers used to congure the
outputs to perform the functions described above.

puts.

Figure 5. ADM106x Outputs Window

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