Analog Devices AN626 Application Notes

AN-626
APPLICATION NOTE
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Using the AD7732/AD7734/AD7738/AD7739 Checksum Register

by To m Meany
This application note refers solely to the AD7738 but is fully applicable to the AD7732, AD7734, and AD7739.
MICRO-
CONTROLLER
Figure 1. An ADC in a Noisy Environment
The checksum register is a 16-bit register and is read by writing 0x45 to the communications register. After a 32 ones reset or a reset using the RESET pin, the register should read back 0xE45E. If the register is read again, it will contain 0x4691 and again reads 0x9AEB before the sequence eventually repeats after 65,535 reads. What is going on?
The checksum register is actually an LFSR (linear feedback shift register). In fact, it’s a maximal length LFSR, which is why it takes 65,535 cycles before the data repeats.
ON-CHIP
REGISTERS
ADC
CORE
ADC
SENSOR
X
QDQDQD
CLOCK
Figure 2. Simple LFSR Circuit Showing a 3-Bit LFSR. (AD7738 contains a 16-bit LFSR. See the C code for exact feedback.)
For the AD7738 checksum register, there are 16 fl ip-fl ops, and the feedback is from the 15th bit to Bits 0, 1, 2, and 5. The feedback positions for a given length LFSR are gen­erally read from standard tables such as those found in the references.
On power-up, the checksum register input is connected to the DIN pin and the clock to the SCLK pin. Each time a bit of data is written to the AD7738, the content of the LFSR updates in a predictable way, depending on whether that bit of data is a 0 or a 1. In this way, the interface data writ­ten to the AD7738 changes the contents of the checksum register. A system controller can use this feature to con­fi rm that the data written to an AD7738 has been correctly received. For instance, writing all eight sets of channel calibration registers would involve writing 8  2  3 = 48 bytes of data to the AD7738. Without a checksum register, the user would have to read back all 48 bytes to confi rm that the data was correctly received. With the checksum register, the user can precompute an expected value for the compression register and confi rm that the 48 bytes arrived uncorrupted by reading back just two bytes from the checksum register.
DIN
REV. 0
Similarly the checksum register can monitor DOUT. If reading back ADC conversion results, the system con­troller could read the checksum register every 10, 100, or 1000 conversions to confi rm that the contents of the checksum register match the expected value, where the expected value is updated on every data transfer by a simulated checksum register within the controller.
AN-626
Writing 0x0000 to the compression register resets the checksum register to 0xFFFF and sets it to monitor DIN. If 0xFF00 is written to the checksum register, then the checksum register is reset to 0xFFFF and it monitors DOUT.
DO 32 ONES RESET
WRITE 0x0000 TO DATA CHECKSUM REGISTER
WRITE TO REGISTERS TO CONFIGURE AD7738
READ CHECKSUM REGISTER AND VERIFY AS EXPECTED
If 0x0000 is written to the checksum register and the checksum register is then read, the user will read back 0xE45E because the write to the communications register to select the read of the checksum register will change the contents of the register (in a predictable way). However, if 0xFF00 is written, then 0xFFFF will be read back since there is no read between setting up the checksum register and reading its contents.
WRITE 0xFF00 TO CHECKSUM REGISTER
READ N CONVERSION RESULTS AND SEND TO CONTROLLER
CONTROLLER VERIFIES CHECKSUM REGISTER = CALCULATED CHECKSUM
–2–
REV. 0
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