Analog Devices AN-551 Application Notes

AN-551

a

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com

Power Management of the ADV7172/ADV7173 Video Encoder

INTRODUCTION

This application note describes the different power op­erating modes of the ADV7172/ADV7173 and how the
device should be configured or used in order to use
power as efficiently as possible.

THE THREE POWER OPERATING MODES AVAILABLE ON
THE ADV7172/ADV7173

The ADV7172/ADV7173 has three power operating
modes:

Normal Power Mode at 5 V or 3.3 V

When all DACs are switched on, the current consumed is
set by R
small DACs (DAC D, E, F) and V
the different current settings.

Low Power Mode

Low Power Mode is only available at an operating volt­age of 5 V. It only takes effect when the large DACs (A, B,
C) are switched on. This facility will reduce the average
current consumed by each large DAC (which is powered
on) by approximately 40%.

How Does Low Power Mode Work?

Considering each DAC as a group of current sources, when
any current source has a DAC code of zero (i.e., off), the
DAC current is switched to ground and current is con­sumed unnecessarily. If the current source is then
switched off instead of being switched to ground, the
current consumed can be reduced by approximately 40%.

Sleep Mode

Sleep Mode is available at 5 V and 3.3 V operation. The
current consumed by the ADV7172/ADV7173 is typi-

cally less than 20 µA. This mode can be used while

powering up or while configuring the registers.

Two Mode Registers allow control over Sleep Mode:
Mode Register 2, “Sleep Mode Control” and Mode Reg­ister 6, “Power Up Sleep Mode.” In Mode Register 2,
Sleep Mode is enabled when the according bit (MR27)
“Sleep Mode Control” is set to Logic 1 and disabled
when it is set to Logic 0.

When enabled, the current consumption of the

ADV7172/ADV7173 is typically less than 20 µA. If the de-

vice is set to operate in Sleep Mode and if Sleep Mode is
disabled in setting the according bit (MR27) to Logic 0,

for the large DACs (DAC A, B, C), R

SET1

. See Tables I and II for

REF

SET2

for the

the device will come out of Sleep Mode and resume nor­mal operation.

Also, if the device is set to operate in Sleep Mode and a
reset is applied, the device will come out of Sleep Mode
and resume normal operation. This mode will only oper­ate when Mode Register 6, “Power-Up Sleep Mode” is
disabled (set to Logic 1), otherwise Sleep Mode is con­trolled by the PAL_NTSC and SCRESET/RTC pin.

Note that the I

Mode Register 6

MR60 “Power-Up in Sleep Mode” allows the user to
control powering up the device in Sleep Mode to facili­tate low power consumption before the I
The device will power up in Sleep Mode if the SCRESET/
RTC pin and the NTSC_PAL pin are tied high and the
“Power-Up Sleep Mode” control (MR60) is set to En­abled (set to a Logic 0). This bit is always set to 0 after
powering up or after applying a reset.

When “Power-Up Sleep Mode” is disabled or set to a
Logic 1, Sleep Mode control passes to Mode Register 2,
“Sleep Mode Enable” control.

THERE ARE SEVERAL METHODS TO REDUCE POWER
CONSUMPTION OF THE ADV7172/ADV7173

1. Operating Voltage: 5 V Low Power Mode

2. Operating Voltage: 3.3 V

3. Sleep Mode

4. Turn Off Unused DACs

5. External Buffering

6. TV Autodetect

Operating Voltage: 5 V Low Power Mode

Mode Register 1, Bit 6, “Low Power Mode Control” al­lows the Low Power Mode to be selected. Note, that Low
Power Mode is only available at 5 V operation.

Low Power Mode will reduce the average current con­sumed by each DAC by approximately 40%.

In normal mode the current consumed is set by R
R

and V

SET2

reduced by approximately 40%. For each DAC the rela­tionship between R
put current is unchanged by this.

2

C interface still operates in Sleep Mode.

2

C is initialized.

. In Low Power Mode this set current is

REF

SET1/VREF

and R

SET2/VREF

and the out-

SET1

,

AN-551

Operating Voltage: 3.3 V

Ideal or optimum performance is achieved when the de­vice is operated at 3.3 V and DAC A, B, C (large DACs) are
set to an output current of:

I

= 18

OUT

mA

where

R

= 300 Ω

SET

1

R

= 600 Ω

SET

2

R

= 75 Ω (Single Terminated Load)

LOAD

Sleep Mode

Is available at 5 V and 3.3 V operation.

The current consumption of the ADV7172/ADV7173 is

typically less than 20 µA.

As mentioned before, this mode can be used while
powering up the device or while configuring the regis­ters. See Sleep Mode section for details on how to oper­ate Sleep Mode.

Turn Off Unused DACs

It is recommended that whenever a DAC is not used, it
should be switched off.

This is done in Mode Register 1, where each DAC can be
individually powered off. Refer to Table I and Table II for
further details.

External Buffering

External buffering is another way to reduce power con­sumption. Whereas DAC D, E, F (small DACs) always
need buffering, buffering on DACs A, B, C is optional
(when DAC D, E, F are not used). In the shown configura­tion the DACs A, B, C are running at 18 mA, which is half
of their full current capability. This allows a reduction in
power dissipation by 50% in the current that these DACs
consume.

V

AA

ADV7172/ADV7173

OUTPUT
BUFFER

OUTPUT
BUFFER

OUTPUT
BUFFER

OUTPUT
BUFFER

OUTPUT
BUFFER

OUTPUT
BUFFER

CVBS

LUMA

CHROMA

G

B

R

300V

PIXEL

600V

PORT

V

R

SET1

DIGITAL

R

SET2

REF

CORE

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

The resistors are given the following values:

R

= 300 Ω

SET1

R

= 600 Ω

SET2

R

= 75 Ω Single Terminated

LOAD

It is further recommended to use this configuration at an
operating voltage of 3.3 V. This allows optimum DAC
performance and adds extra isolation on the video
outputs.

1kV

V

CC+

1kV

75V

OUTPUT TO
OUTPUT FILTER/
TV MONITOR

INPUT

300V

AD847

V

CC–

Figure 2. Recommended DAC Output Buffer Using an
Op Amp

TV Autodetect

This feature allows the user to determine whether or not
the DACs are correctly terminated. This facility is avail­able for DACs A, B, C since unconnected (not used)
DACs increase power consumption.

Mode Register 6 allows automatic detection of untermi­nated DACs:

1. The “DAC Termination Mode” control allows to select

between correct 75 Ω or 150 Ω termination.

Note that double terminated 75 Ω becomes 37.5 Ω (i.e.,
75 Ω on the DAC end and 75 Ω on the TV end) and 150 Ω
becomes 75 Ω. For this reason the Autodetect facility

cannot operate if the large DACs are buffered, since
buffering results in a fixed termination, regardless if cor­rectly or incorrectly terminated at the buffer output.

Mode Register 6 “DAC Termination Mode” control (Bit

4) allows the user to select between two Autodetect
Termination modes:

1 × Mode = 75 Ω Termination (Single-Terminated)
2 × Mode = 150 Ω Termination (Single-Terminated)

Mode Register 6 “Comp Autodetect Mode” control (Bit

3) and “Luma Autodetect” control (Bit 2) allow the
choice between two functions:

Mode0

Correct termination of the DAC is checked and indicated
with the according Status bit set to “1” or when using
the Evaluation Software, Mode Register 6 (Autodetect
Status) a green button indicates correct termination.

Figure 1. Output DAC Buffering Configuration

If not correctly terminated, the user has the choice to
power down the DAC or not. This can be done by using
Mode Register 1.

–2–