AN-551
a
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com
Power Management of the ADV7172/ADV7173 Video Encoder
INTRODUCTION
This application note describes the different power operating modes of the ADV7172/ADV7173 and how the
device should be configured or used in order to use
power as efficiently as possible.
THE THREE POWER OPERATING MODES AVAILABLE ON
THE ADV7172/ADV7173
The ADV7172/ADV7173 has three power operating
modes:
Normal Power Mode at 5 V or 3.3 V
When all DACs are switched on, the current consumed is
set by R
small DACs (DAC D, E, F) and V
the different current settings.
Low Power Mode
Low Power Mode is only available at an operating voltage of 5 V. It only takes effect when the large DACs (A, B,
C) are switched on. This facility will reduce the average
current consumed by each large DAC (which is powered
on) by approximately 40%.
How Does Low Power Mode Work?
Considering each DAC as a group of current sources, when
any current source has a DAC code of zero (i.e., off), the
DAC current is switched to ground and current is consumed unnecessarily. If the current source is then
switched off instead of being switched to ground, the
current consumed can be reduced by approximately 40%.
Sleep Mode
Sleep Mode is available at 5 V and 3.3 V operation. The
current consumed by the ADV7172/ADV7173 is typi-
cally less than 20 µA. This mode can be used while
powering up or while configuring the registers.
Two Mode Registers allow control over Sleep Mode:
Mode Register 2, “Sleep Mode Control” and Mode Register 6, “Power Up Sleep Mode.” In Mode Register 2,
Sleep Mode is enabled when the according bit (MR27)
“Sleep Mode Control” is set to Logic 1 and disabled
when it is set to Logic 0.
When enabled, the current consumption of the
ADV7172/ADV7173 is typically less than 20 µA. If the de-
vice is set to operate in Sleep Mode and if Sleep Mode is
disabled in setting the according bit (MR27) to Logic 0,
for the large DACs (DAC A, B, C), R
SET1
. See Tables I and II for
REF
SET2
for the
the device will come out of Sleep Mode and resume normal operation.
Also, if the device is set to operate in Sleep Mode and a
reset is applied, the device will come out of Sleep Mode
and resume normal operation. This mode will only operate when Mode Register 6, “Power-Up Sleep Mode” is
disabled (set to Logic 1), otherwise Sleep Mode is controlled by the PAL_NTSC and SCRESET/RTC pin.
Note that the I
Mode Register 6
MR60 “Power-Up in Sleep Mode” allows the user to
control powering up the device in Sleep Mode to facilitate low power consumption before the I
The device will power up in Sleep Mode if the SCRESET/
RTC pin and the NTSC_PAL pin are tied high and the
“Power-Up Sleep Mode” control (MR60) is set to Enabled (set to a Logic 0). This bit is always set to 0 after
powering up or after applying a reset.
When “Power-Up Sleep Mode” is disabled or set to a
Logic 1, Sleep Mode control passes to Mode Register 2,
“Sleep Mode Enable” control.
THERE ARE SEVERAL METHODS TO REDUCE POWER
CONSUMPTION OF THE ADV7172/ADV7173
1. Operating Voltage: 5 V Low Power Mode
2. Operating Voltage: 3.3 V
3. Sleep Mode
4. Turn Off Unused DACs
5. External Buffering
6. TV Autodetect
Operating Voltage: 5 V Low Power Mode
Mode Register 1, Bit 6, “Low Power Mode Control” allows the Low Power Mode to be selected. Note, that Low
Power Mode is only available at 5 V operation.
Low Power Mode will reduce the average current consumed by each DAC by approximately 40%.
In normal mode the current consumed is set by R
R
and V
SET2
reduced by approximately 40%. For each DAC the relationship between R
put current is unchanged by this.
2
C interface still operates in Sleep Mode.
2
C is initialized.
. In Low Power Mode this set current is
REF
SET1/VREF
and R
SET2/VREF
and the out-
SET1
,
AN-551
Operating Voltage: 3.3 V
Ideal or optimum performance is achieved when the device is operated at 3.3 V and DAC A, B, C (large DACs) are
set to an output current of:
I
= 18
OUT
mA
where
R
= 300 Ω
SET
1
R
= 600 Ω
SET
2
R
= 75 Ω (Single Terminated Load)
LOAD
Sleep Mode
Is available at 5 V and 3.3 V operation.
The current consumption of the ADV7172/ADV7173 is
typically less than 20 µA.
As mentioned before, this mode can be used while
powering up the device or while configuring the registers. See Sleep Mode section for details on how to operate Sleep Mode.
Turn Off Unused DACs
It is recommended that whenever a DAC is not used, it
should be switched off.
This is done in Mode Register 1, where each DAC can be
individually powered off. Refer to Table I and Table II for
further details.
External Buffering
External buffering is another way to reduce power consumption. Whereas DAC D, E, F (small DACs) always
need buffering, buffering on DACs A, B, C is optional
(when DAC D, E, F are not used). In the shown configuration the DACs A, B, C are running at 18 mA, which is half
of their full current capability. This allows a reduction in
power dissipation by 50% in the current that these DACs
consume.
V
AA
ADV7172/ADV7173
OUTPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
BUFFER
OUTPUT
BUFFER
CVBS
LUMA
CHROMA
G
B
R
300V
PIXEL
600V
PORT
V
R
SET1
DIGITAL
R
SET2
REF
CORE
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
The resistors are given the following values:
R
= 300 Ω
SET1
R
= 600 Ω
SET2
R
= 75 Ω Single Terminated
LOAD
It is further recommended to use this configuration at an
operating voltage of 3.3 V. This allows optimum DAC
performance and adds extra isolation on the video
outputs.
1kV
V
CC+
1kV
75V
OUTPUT TO
OUTPUT FILTER/
TV MONITOR
INPUT
300V
AD847
V
CC–
Figure 2. Recommended DAC Output Buffer Using an
Op Amp
TV Autodetect
This feature allows the user to determine whether or not
the DACs are correctly terminated. This facility is available for DACs A, B, C since unconnected (not used)
DACs increase power consumption.
Mode Register 6 allows automatic detection of unterminated DACs:
1. The “DAC Termination Mode” control allows to select
between correct 75 Ω or 150 Ω termination.
Note that double terminated 75 Ω becomes 37.5 Ω (i.e.,
75 Ω on the DAC end and 75 Ω on the TV end) and 150 Ω
becomes 75 Ω. For this reason the Autodetect facility
cannot operate if the large DACs are buffered, since
buffering results in a fixed termination, regardless if correctly or incorrectly terminated at the buffer output.
Mode Register 6 “DAC Termination Mode” control (Bit
4) allows the user to select between two Autodetect
Termination modes:
1 × Mode = 75 Ω Termination (Single-Terminated)
2 × Mode = 150 Ω Termination (Single-Terminated)
Mode Register 6 “Comp Autodetect Mode” control (Bit
3) and “Luma Autodetect” control (Bit 2) allow the
choice between two functions:
Mode0
Correct termination of the DAC is checked and indicated
with the according Status bit set to “1” or when using
the Evaluation Software, Mode Register 6 (Autodetect
Status) a green button indicates correct termination.
Figure 1. Output DAC Buffering Configuration
If not correctly terminated, the user has the choice to
power down the DAC or not. This can be done by using
Mode Register 1.
–2–
AN-551
Mode1
Correct termination of the DAC is checked and indicated
with the according Status bit set to “1” or when using
the Evaluation Software, Mode Register 6 (Autodetect
Status) a green button indicates correct termination.
If not correctly terminated, the DAC is automatically
powered down.
Correct termination is checked at intervals of one frame
to decide whether or not the DACs are to be powered
down.
SETTINGS FOR R
SET1
, R
SET2
, R
LOAD
Operating Voltage: 5 V/Normal Mode
The values for R
SET1
and R
determine what current
SET2
will be consumed by each DAC and, therefore, what
power will be consumed.
The current consumed is calculated as:
I
= (
V
×
K
)/
×
V
R
LOAD
R
SET
OUT
V
OUT
V
= 1.235
REF
K
= 4.2146
=
I
REF
OUT
DAC A, B, C (Large DACs)
R
is used for the small DACs and has no effect on the
SET2
output current of the large DACs.
I
= 34.7 mA R
OUT
I
= 5 mA R
OUT
= 150 Ω
SET1
R
= 75 Ω (Single-Terminated)
LOAD
= 1041 Ω
SET1
R
= 262.5 Ω
LOAD
(Buffered, Scaled Output Load)
Operating Voltage: 3.3 V/Normal Mode
The same settings for R
SET1
and R
apply for 3.3 V op-
SET2
eration as shown above for 5 V operation.
3.3 V operation will reduce the power dissipation due to
the V × I = P formula, i.e., the current is unchanged while
the voltage decreases from 5 V to 3.3 V.
JUNCTION TEMPERATURE
It is important to keep in mind that at no time the maxi-
mum junction temperature of 110°C should be exceeded:
Junction Temperature = [V
(Σ of I
AA
OUT
+ I
CCT
) × θ
JA
+70°C
I
= Circuit Current or Digital Supply Current
CCT
= Continuous Current Required to Drive the
Device
I
= 78 mA at VAA = 5 V
CCT
I
= 40 mA at VAA = 3.3 V
CCT
I
= Total Current to Drive All DACs
DAC
= 10 mA + (Σ of the Average Currents Con-
sumed by Each DAC)
= 10 mA + (Σ of I
I
= Average Current Consumed by DAC
OUT
= Junction-to-Ambient Thermal Resistance 54.6°C/W
θ
JA
of Each DAC)
OUT
in Still Air On a Four-Layer PCB
θ
= Junction-to-Case Thermal Resistance 16.7°C/W
JC
in Still Air On a Four-Layer PCB
V
= Supply Voltage
AA
=V
P
TOTAL
I
TOTAL=ICCT
× I
AA
+ Σ of I
Total
OUT
]
See Table I and Table II for further details.
DAC D, E, F (Small DACs)
R
is used for the large DACs and has no effect on the
SET1
output current of the small DACs.
I
= 8.66 mA R
OUT
I
= 5 mA R
OUT
R
R
SET2
LOAD
SET2
LOAD
= 600 Ω
= 150 Ω
= 1041 Ω
= 262.5 Ω
(Buffered, Scaled Output Load)
See Table I and Table II for further details
–3–
AN-551
Table I. DAC Current Consumption
Supply DAC Power DAC A DAC B DAC C DAC D DAC E DAC F Degrees Output I
Voltage Buffering ON (mA) (mA) (mA) (mA) (mA) (mA) Celsius Configuration (mA) (mA) (mA) (mW)
5 V
No No 34.7 34.7 34.7 8.66 8.66 8.66 126.8
No Yes 20.82 20.82 20.82 OFF OFF OFF 108.3 Allowed 78 72.46 140.46 702.3
Yes No 5 5 5 5 5 5 99.5 Allowed 78 40 108 540
Yes Yes 3 3 3 OFF OFF OFF 93.8 Allowed 78 19 87 435
No No OFF 34.7 34.7 8.66 8.66 8.66 117.3
No Yes OFF 20.82 20.82 OFF OFF OFF 102.7 Allowed 78 51.64 119.64 598.2
Yes No OFF 5 5 5 5 5 98.1 Allowed 78 35 103 515
Yes Yes OFF 3 3 OFF OFF OFF 92.9 Allowed 78 16 84 420
No No OFF OFF 34.7 8.66 8.66 8.66 107.9 Allowed 78 70.68 138.68 693.4
No Yes OFF OFF 20.82 OFF OFF OFF 97 Allowed 78 30.82 98.82 494.1
Yes No OFF OFF 5 5 5 5 96.8 Allowed 78 30 98 490
Yes Yes OFF OFF 3 OFF OFF OFF 92.1 Allowed 78 13 81 405
No No OFF OFF OFF 8.66 8.66 8.66 98.3 Allowed 78 35.98 103.98 519.9
No Yes OFF OFF OFF OFF OFF OFF
Yes No OFF OFF OFF 5 5 5 95.4 Allowed 78 25 93 465
Yes Yes OFF OFF OFF OFF OFF OFF
No No OFF OFF OFF OFF 8.66 8.66 96 Allowed 78 27.32 95.32 476.6
No Yes OFF OFF OFF OFF OFF OFF
Yes No OFF OFF OFF OFF 5 5 94 Allowed 78 20 88 440
Yes Yes OFF OFF OFF OFF OFF OFF
No No OFF OFF OFF OFF OFF 8.66 93.7 Allowed 78 18 86.66 433.3
No Yes OFF OFF OFF OFF OFF OFF
Yes No OFF OFF OFF OFF OFF 5 92.7 Allowed 78 15 83 415
Yes Yes OFF OFF OFF OFF OFF OFF
No No 34.7 34.7 34.7 8.66 8.66 OFF 124.4
No Yes 20.82 20.82 20.82 OFF OFF OFF 108.3 Allowed 78 72.46 140.46 702.3
Yes No 5 5 5 5 5 OFF 98.1 Allowed 78 35 103 515
Yes Yes 3 3 3 OFF OFF OFF 93.8 Allowed 78 19 87 435
No No 34.7 34.7 34.7 8.66 OFF OFF 122.1
No Yes 20.82 20.82 20.82 OFF OFF OFF 102.7 Allowed 78 51.64 119.64 598.2
Yes No 5 5 5 5 OFF OFF 96.8 Allowed 78 30 98 490
Yes Yes 3 3 3 OFF OFF OFF 93.8 Allowed 78 19 87 435
No No 34.7 34.7 34.7 OFF OFF OFF 119.7
No Yes 20.82 20.82 20.82 OFF OFF OFF 108.3 Allowed 78 72.46 140.46 702.3
Yes No 5 5 5 OFF OFF OFF 95.4 Allowed 78 25 93 465
Yes Yes 3 3 3 OFF OFF OFF 93.8 Allowed 78 19 87 435
No No 34.7 34.7 OFF OFF OFF OFF 110.2 Allowed 78 79.4 147.4 737
No Yes 20.82 20.82 OFF OFF OFF OFF 102.7 Allowed 78 51.64 119.64 598.2
Yes No 5 5 OFF OFF OFF OFF 94 Allowed 78 20 88 440
Yes Yes 3 3 OFF OFF OFF OFF 92.9 Allowed 78 16 84 420
No No 34.7 OFF OFF OFF OFF OFF 100.8 Allowed 78 44.7 112.7 563.5
No Yes 20.82 OFF OFF OFF OFF OFF 96.9 Allowed 78 30.82 98.82 494.1
Yes No 5 OFF OFF OFF OFF OFF 92.7 Allowed 78 15 83 415
Yes Yes 3 OFF OFF OFF OFF OFF 92.1 Allowed 78 13 81 405
Low I
OUTIOUTIOUTIOUTIOUTIOUT
Junction
Temp DAC
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
CCTIDAC
78 140.08 208.08 1040.4
78 105.38 173.38 866.9
78 131.42 199.42 997.1
78 122.76 190.76 953.8
78 114.1 182.1 910.5
I
TOTALPTOTAL
–4–
Table II. DAC Current Consumption
AN-551
I
Supply DAC DAC A DAC B DAC C DAC D DAC E DAC F Junction Temp I
OUT
Voltage Buffering (mA) (mA) (mA) (mA) (mA) (mA) Degrees Celsius (mA) (mA) (mA) (mW)
3.3 V
No 34.7 34.7 34.7 8.66 8.66 8.66 100.6 40 140.08 170.08 561.3
I
OUT
I
OUT
I
OUT
I
OUT
I
OUT
CCT
I
DAC
I
TOTAL
P
TOTAL
Yes5555 5582.6 40 40 70 231
No OFF 34.7 34.7 8.66 8.66 8.66 94.4 40 105.38 135.4 446.8
Yes OFF 5 5 5 5 5 81.7 40 35 65 214.5
No OFF OFF 34.7 8.66 8.66 8.66 88.1 40 70.68 100.7 332.3
Yes OFF OFF 5 5 5 5 80.8 40 30 60 198
No OFF OFF OFF 8.66 8.66 8.66 81.9 40 35.98 65.9 217.5
Yes OFF OFF OFF 5 5 5 79.9 40 25 55 181.5
No OFF OFF OFF OFF 8.66 8.66 80.3 40 27.32 57.32 189.2
Yes OFF OFF OFF OFF 5 5 79 40 20 50 165
No OFF OFF OFF OFF OFF 8.66 78.8 40 18.66 48.66 160.6
Yes OFF OFF OFF OFF OFF 5 78.1 40 15 45 148.5
No 34.7 34.7 34.7 8.66 8.66 OFF 99.1 40 131.42 161.42 532.7
Yes5555 5OFF81.7 40 35 65 214.5
No 34.7 34.7 34.7 8.66 OFF OFF 97.5 40 122.76 152.8 504.2
Yes5555 OFFOFF80.8 40 30 60 198
No 34.7 34.7 34.7 OFF OFF OFF 95.9 40 114.1 144.1 475.5
Yes 5 5 5 OFF OFF OFF 79.9 40 25 55 181.5
No 34.7 34.7 OFF OFF OFF OFF 89.7 40 79.4 109.4 361.02
Yes 5 5 OFF OFF OFF OFF 79 40 20 50 165
E3554–2–6/99
–5–
PRINTED IN U.S.A.
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