Analog Devices AN-550 Application Notes

AN-550

a

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com

Serial Transmission of ADV601 Compressed Video

by David Starr

OVERVIEW

This Application Note describes how to send com­pressed digital video from one ADV601LC-based Video­pipe evaluation board to another Videopipe board. This
enhancement of the Videopipe board function is accom­plished merely by replacing the standard Videopipe
firmware with special firmware. No hardware modifica­tions are necessary. The firmware to transmit video is
dubbed TRANLAYR. The firmware to receive is called
RECVLAYR. TRANLAYR and RECVLAYR communicate
video using the ISO 13818 (otherwise known as H.222.0)
transportation protocol over the 8 Megabit/sec serial
ports of the Videopipe boards. The TRANLAYR program
accepts standard analog video from a TV camera or
other source and outputs compressed digital video. The
RECVLAYR program is the inverse, it accepts com­pressed digital video and outputs standard analog video
to a TV monitor.

This Applications note is for hardware and software de­signers starting an ADV601 design. Using this note and
the information in any ADV601 family Video Codec data
sheet you can do the following:

Use Videopipe boards as engineering mock-ups on
compressed video projects.

Understand how to select compressed video bit rates.
Understand the theory of operation of TRANLAYR and
RECVLAYR.

Know how to program EPROMs and assemble the
programs.

The design examples in this application note refer to
the ADV601-based Videopipe demonstration board, but
you can apply the techniques used in these examples to
any ADV601-based design. The software source code
and hardware schematics mentioned in this note are

available on the Analog Devices computer products FTP
site, whose Uniform Resource Locator (URL) is:

ftp://ftp.analog.com/pub/dsp/adv601/

Serial Port Electrical Interface and Timing

The serial ports (SPORTS) of the ADV2185 DSP are de­scribed at length in the DSP2100 Family User’s Manual,
Chapter 5. These are synchronous serial ports that can
operate at any speed up to 16 Mbps, unlike the usual
RS-232 ports which are limited to perhaps 100 kbps. They
are internal to the chip and thus add no cost to an
ADSP-21xx-based product like Videopipe. The SPORT
input and output pins are connected inside the chip to
ordinary CMOS gates adequate to drive a signal around
a PC board. Long cables will require higher performance
bus drivers and receivers. Circuit designers should be
aware that the SPORT1 I/O pins all have multiple func­tions. The alternate functions will be unavailable if the
SPORT is in use. For example IRQ0 and Receive Frame
Sync 1 share the same pin. If SPORT 1 is used as a
SPORT, then IRQ0 becomes unavailable. Designers
should conduct a careful “pin inventory” to avoid a “pin
resource conflict” (two functions needing the same pin
at the same time).

Bit Clock and Word Clock

The SPORT uses a bit clock signal to decode the incom­ing serial data; there are no start or stop bits as in asyn­chronous serial ports. The “Frame” signal is actually a
word clock delimiting 16 bits on the serial link. Not to be
confused with a video frame, which is 486 lines of video
painted on the CRT. The beginning of each word is
marked by a pulse on the “frame” line. Word length is
programmable over the range 3 to 16 bits. The program
normally uses 16 bits. Eight bits are supported in soft­ware. Eight-bit mode can be enabled with some condi­tional assembly statements.

RAW ANALOG

VIDEO

TV CAMERA

Figure 1. Block Diagram, Serial Video Transmission

COMPRESSED SERIAL

DIGITAL VIDEO

TRANLAYR
VIDEOPIPE

RECVLAYR
VIDEOPIPE

RAW ANALOG

VIDEO

TV MONITOR

AN-550

EZ-ICE JP16

SERIAL PORT

(SPORT) JP17

RS-232 P1

DRAM

Y/C

CVBS

J11

CCIR656

J12

+5V dc

J10

J2

SAA7111

ADV601LC

ADV601LC

VIDEOPIPE

H/W RESET

ADSP-2185

H/W RESET

SRAM PALS

Figure 2. ADV601LC Videopipe Block Diagram

External and Internal Clock(s)

The bit and word clock signals can be programmed as
outputs or inputs to the SPORT. The software makes the
TRANLAYR Videopipe source both bit and word clock
and the receive Videopipe accepts the clock supplied by
the transmitter. This choice was arbitrary (someone has
to source clock and someone has to accept it). Future
versions of the code may autoswitch from internal to ex­ternal clock at power-up. If an external bit clock is de­tected the SPORT will be programmed to external clock.
If no external bit clock is detected, the SPORT will be
programmed to source bit clock. Interface to external
equipment (modems, RF transmitters etc.) is often
easier if the Videopipe accepts bit clock from the exter­nal equipment. The internal clock is created by dividing
down the processor crystal frequency, 8 MHz in
Videopipe. The Sport0_SclkDiv register is the “divisor.”
Zero yields an 8 MHz bit clock, one gives a 4 MHz bit
clock and so on. See the code in module sport0.dsp.

Bit Clock Automatically Sets the Video Compression Ratio

Bit clock determines how fast the TRANLAYR Videopipe
can send out compressed video. As the bit clock fre­quency is reduced, the bin width calculator will auto­matically increase the compression ratio to reduce the
compressed bit rate to a rate the SPORT can handle.
Likewise, should the bit clock frequency increase, the
compression ratio will be reduced to furnish more com­pressed video bits to send. This is useful when external
bit clock is used. There is no need to alter program code
to match the compression ratio to the SPORT capacity.

Bit and Word Clock Recovery Issues

Usually only one signal, the serial data, is transmitted
over a distance. In this case, the receiver at the far end
has to recover both the bit clock and the word clock
(frame signal) from the incoming serial data. Bit clock
recovery can be done with a phase locked loop (PLL) at

DRAM

Y/C
J8
CVBS

J7

CCIR656
J13

ROMSRAM

ADV601LC

H/W RESET

RESET

UP

FREEZE

PUSH BUTTONS

SELECT

DOWN

ADV7175

the receiver. The PLL needs to adjust the phase of the
local bit clock until the bit clock transitions do not occur
when the data is changing. Word clock (the frame sig­nal) can be recovered by counting bit clocks from some
recognizable marker in the data stream. The Videopipe
serial transmission demo does not address the clock re­covery issue. It requires the bit clock and word clock sig­nals to be run between the two Videopipe boards.

Pixel Clock Recovery

Practical systems need to deal with variations of pixel
clock. At the “camera” end of a system, pixels are digi­tized and TV sync created from a crystal in the camera.
The video is then compressed, transmitted to a distant
receiver, decompressed and played back. In the re­ceiver, TV sync is created from a local crystal in the re­ceiver. The two crystal oscillators (camera and receiver)
will run at slightly different speeds. This causes the re­ceiver to run either slightly faster or slightly slower than
the camera. The receiver finds his compressed video
buffer either running dry or overflowing. The serial
transmission demo merely discards or repeats the occa­sional video field. A more sophisticated design might
have a variable frequency pixel clock in the receiver and
adjust it to keep the receiver’s pixel clock running at ex­actly the same speed as the camera’s pixel clock.

COMPRESSED VIDEO

(LESS SYNC) SENT

OVER COMM LINK

27MHz CRYSTAL

IN CAMERA

27MHz CRYSTAL

IN RECEIVER

Figure 3. Pixel Clock Changes from Camera to TV Set

–2–