Analog Devices an420 Application Notes
AN-420
R3 AND
R4 NETS
*
R7 AND
R8 NETS
*
INPUT WORD
(14 PLACES)
R40 AND
R41 NETS
C1
*
, C2*,
C25
*
, TO C36*,
C19
*
R1 AND
R2 NETS
*
R5 AND
R6 NETS
*
CLOCK
AD9708/60/62/64
R15
50Ω
P1
(14 SECTIONS)
+AVDD
JP1
B POS
+DVDD
J1
*
THESE COMPONENTS WERE NOT INSTALLED AT THE FACTORY
IOUT A
(OUT 1)
AD9708/60/62/64
R38
49.9Ω
C13
22pF
J4
R20
49.9Ω
C12
22pF
J3
IOUT B
(OUT 2)
J7
a
ONE TECHNOLOGY WAY • P.O. BOX 9106
Using the AD9708/AD9760/AD9762/AD9764-EB Evaluation Board
GENERAL DESCRIPTION
The AD9708-EB, AD9760-EB, AD9762-EB and AD9764-EB
evaluation boards are used to evaluate the AD976x family of 8-, 10-, 12- and 14-bit D/A converters (AD9708,
AD9760, AD9762, AD9764, respectively). This board allows the user to exercise the AD9708/AD9760/AD9762/
AD9764’s many features. They include resistor, transformer, op amp loading of the converter and sleep mode
operation for reduced power consumption. For greater
gain accuracy, an external reference may also be used
with the converters. Each of these functions will be outlined in this note; however, the user should refer to the
AD9708/AD9760/AD9762/AD9764 data sheet. It covers
the operation and application in far greater detail than
this evaluation board note.
•
NORWOOD, MASSACHUSETTS 02062-9106
by Bill Odom
APPLICATION NOTE
617/329-4700
•
family is assigned to Pin #1. The unused DAC input pins
will be floating. This allows the 8-, 10-, 12- and 14-bit
DACs to be soldered to the same evaluation board.
Figure 1. Input Word Configuration
Configuration
Although the AD9708/AD9760/AD9762/AD9764-EB evaluation board can exercise the many attributes of this D/A
family, it is shipped with the following configuration
in place:
Its digital input is designed for direct drive from various
word generators. Looking into the input connector, the
generator will see a high impedance load through small
series resistors. Its output is constructed to drive
resistive loads and a transformer. The AD9708/AD9760/
AD9762/AD9764-EB evaluation board is shipped with its
internal reference connected. If its other functions are to
be exercised (external reference, external output amplification and sleep mode) the user must build up the applicable section of the board. Figures 1 and 2 illustrate the
configuration of the board as shipped from the factory.
The entire family of converters is MSB-justified and may
be soldered into the same 28-pin socket (they are all pin
compatible), i.e., the MSB of all the members of the
Figure 2. Resistor and Transformer Load
The parallel data input pins of the DAC follow standard
positive binary coding. An input of all 1s will give a +FS
output current at IOUTA. An input of all 0s will give a
zero output current at IOUTA. (IOUTB is the inversion of
IOUTA. All 1s will give zero current at IOUTB and all 0s
will give it full-scale current.)
Note: The frequency domain data shown in this application note was gathered from an AD9760.
EVALUATION BOARD OPERATION
The AD9708/AD9760/AD9762/AD9764-EB is a 5 × 5.5 inch,
four-layer board. Its layers are composed of component
and solder signal layers, ground plane and power plane.
A schematic and a parts list are on succeeding pages of
this note.
The AD9708/AD9760/AD9762/AD9764 is shipped with
JP2 “B” Pos, JP4 and JP1 “A” Pos installed.
For immediate operation, the user need only apply
power and a CMOS level input word to P1 and a CMOS
level clock to J1 (CMOS levels cross a threshold of
{DVDD – DGND}/2). The analog output can be observed
at J3, J4 or J7 (the transformer should be removed before making observations at J3 or J4). Refer to Figure 3
for setup. See sections on resistive and transformer
loads.
WORD
GENERATOR
+5V
NOMINAL
P1
EXTERNAL
CLOCK
+5V
NOMINAL
AD9708/60/62/64
EVALUATION BOARD
–5V OR
AS REQ
+5V OR
AS REQ
AVCCAVEEDVDD AVDDDGND AGND
J3, J4,
OR J7
SPECTRUM
ANALYZER
Figure 3. Equipment Setup
POWER CONNECTIONS
The AD9708/AD9760/AD9762/AD9764-EB is powered by
two power supplies. They are shown in the table below
with typical amplitudes for initial operation (setup is
shown in Figure 3). Power is distributed on the board
with power planes.
Table I. Power Supplies
DVDD +5 V 1 in = 10 mA typ*
AVDD +5 V 1 in = 30 mA typ*
AVEE† –5 V
AVCC† +5 V
*Current was measured with a 50 MHz clock, +5 V supplies and 50 Ω
loads on the signal output pins.
†These supplies are not required for DAC operation. (Current drain
depends on what components are mounted.)
AVDD and DVDD may be varied independently from
+3 V to +5 V depending on the user’s application (logic
family, power limits, etc.). AVEE and AVCC are used to
power the optional, external reference and output amplifier circuits. When using high supply potentials (voltages greater that ±6.5 V, the user should ensure that the
AD9708/AD9760/AD9762/AD9764 device is not over
stressed (i.e., don’t let the AD9708/AD9760/AD9762/
AD9764 device’s reference or output pins see high voltage transients on turn-on). To avoid damage, please
consult data sheet for maximum values.
GROUND
The AD9708/AD9760/AD9762/AD9764-EB has separate
ground planes for analog and digital returns. The
ground planes are tied together by a single trace under
the AD9708/AD9760/AD9762/AD9764. Clock and the
digital input word have been routed over the digital
ground plane. Reference circuitry and output signal
have been routed over the analog ground plane. As the
users ponder the layout of their own board, they might
consider using the ground planes to develop a controlled impedance with its associated signal layers. This
is required if fast edge rates and/or long trace lengths
are present. Propagation time and line loading will become a concern under these conditions.
DIGITAL INPUT SIGNAL CONFIGURATIONS
To allow flexibility in the input logic levels used, the
AD9708/AD9760/AD9762/AD9764-EB allows several input coupling schemes. Refer to Figure 1.
Load impedance seen by the input word generator is
controlled by R1, R2, R5 and R6. Resistor networks R1
and R2 are tied to DGND. Resistor networks R5 and R6
are tied to DVDD. Their values can be selected to present
the desired load impedance and thevenin voltage to
meet the user’s signal generator requirements. R40 and
R41 are series resistor networks of 22 Ω. If ac-coupled
inputs are desired, R40 and R41 should be removed and
ac-coupling capacitors soldered on the backside of the
board (C19, C1, C2 and C25 through C36). Resistor networks R3, R4, R7 and R8 serve to determine the dc
clamp voltage (level shift) of the ac-coupled signal.
We recommend the clamp voltage be at the switching
threshold of the AD9708/AD9760/AD9762/AD9764 device ({DVDD – DGND}/2).
Care should be made to properly load the input word at
the input connector (P1, a 100 mil sq. ribbon connector)
and at the AD9708/AD9760/AD9762/AD9764. Proper load
termination at these points will insure that the digital input lines are not ringing at the AD9708
/
AD9760/AD9762/
AD9764 device input pins. Note: alternate pins of the
ribbon connector are grounded on the board.
The AD9708/AD9760/AD9762/AD9764-EB is shipped
without R1 through R8 or the ac-coupling capacitors.
Series input resistors R40 and R41 are installed.
CLOCK INPUT
The AD9708/AD9760/AD9762/AD9764’s data input is
triggered on the rising edge of its input clock. This clock
signal is fed to the DAC through either J1 or P1.
The clock source may be taken from either J1 or P1, depending on the position of jumper JP1. If the jumper is
in position “A,” the clock is fed from J1 (SMA connector). If it is in position “B,” it is fed through P1 (ribbon
connector). J1 is terminated by a 49.9 Ω, 1/8 W resistor.
P1’s signal is routed through the same input loading/
level-shifting scheme as the input data word (see digital
input signal configurations). The board is shipped with
the clock signal routed from J1 (JP1 “A” Pos connected).
–2–
EXISTING COMPONENTS
IOUT A
(OUT 1)
AD9708/60/62/64
IOUT B
(OUT 2)
JP8
JP9
499Ω
R35
499Ω
R18
C12
22pF
C13
22pF
J3
JP7A
A POS
JP7B
A POS
R10
499Ω
R9
SHORT
B POS
A POS
JP6A
R20
49.9Ω
J4
JP6B
R38
49.9Ω
Figure 4. Differential Amplifier Configuration
VCC
CONNECTOR
(+)
7
3
AD9631
2
4
VEE
CONNECTOR
(–)
R36
499Ω
C21
0.1µF
6
C23
0.1µF
C8
10µF@
25V
R37
121Ω
C5
10µF@
25V
C22
1µF
C24
1µF
J6
EXISTING COMPONENTS
IOUT A
(OUT 1)
AD9708/60/62/64
IOUT B
(OUT 2)
EXISTING COMPONENTS
IOUT A
(OUT 1)
AD9708/60/62/64
IOUT B
(OUT 2)
J3
JP6A
C12
22pF
C13
22pF
R20
50Ω
J4
R38
50Ω
A POS
B POS
JP6B
JP7A
R9
SHORT
JP8
B POS
R35
499Ω
JP9
B POS
Figure 5. Noninverting Amplifier Configuration
J3
JP6A
C12
22pF
C13
22pF
R20
49.9Ω
R38
49.9Ω
A POS
B POS
JP6B
J4
JP7A
R9
SHORT
JP9
A POS
R35
249kΩ
R18
165Ω
CONNECTOR
3
AD9631
2
R36
499Ω
CONNECTOR
VCC
CONNECTOR
R36
499kΩ
2
AD9631
3
VCC
(+)
7
4
VEE
(–)
(+)
7
4
C21
0.1µF
6
C23
0.1µF
C21
0.1µF
6
C23
0.1µF
C8
10µF@
25V
R37
121Ω
C5
10µF@
25V
C8
10µF@
25V
R37
121Ω
C22
1µF
C24
1µF
C22
1µF
C24
1µF
J6
J6
Figure 6. Inverting Amplifier Configuration
–3–
VEE
CONNECTOR
(–)
C5
10µF@
25V
OUTPUT CONFIGURATIONS
Resistive Load
The single-ended outputs of the AD9708/AD9760/AD9762/
AD9764 may be observed through J3 and J4. At these
points the user will observe IOUTA and its complement,
output IOUTB (respectively). The output voltage is developed by the flow of output current into 50 Ω resistors
(R20, R38) and 20 pF capacitors (C12, C13). One RC net is
shunted to ground for each output. The evaluation
board is shipped with the RC networks installed. Refer to
Figures 2 and 14 for schematics.
Figure 7 illustrates a frequency domain plot for the resistive load. It was obtained by connecting a spectrum analyzer to J3 with a 50 Ω cable. The spectrum analyzer
input impedance was set to 50 Ω. There may be some
difference between the frequency domain spurs between
IOUTA and IOUTB.
The transformer must be removed
for measurements using the resistive loads.
F
= 50MHz
CLK
F
= 5MHz
OUT
SFDR = 75dB
F
= 50MHz
CLK
= 5MHz
F
OUT
SFDR = 69dB
Figure 8. Transformer Output Load
Amplifier Load
The AD9708/AD9760/AD9762/AD9764 can be operated in
differential or single-ended modes through the use of
high quality amplifiers such as the AD9631. The op amp
is especially useful at analog output frequencies below
300 kHz and where dc accuracy is important. The
AD9708/AD9760/AD9762/AD9764-EB is shipped without
the output op amp and its support components. Table II
details the components that can be mounted with the
amplifier (refer to the schematics in Figures 4, 5, 6 and
13). By mounting the components outlined in Table II,
various amplifier configurations may be obtained.
The transformer should be removed from the board before using the amplifier. Figures 9, 10 and 11 illustrate
typical frequency domain plots for differential, inverting
(AV = –2) and noninverting (AV = +2) configurations.
Figure 7. Resistive Output Load
Transformer Load
With T1 in place, the differential signals of IOUTA and
IOUTB are converted from differential to single-ended
mode. This signal can be observed at J7. It is derived by
transformer T1 (mini-circuits T1–1T). The transformer is
capable of processing signals above 350 kHz from the
AD9708/AD9760/AD9762/AD9764 device. The transformer
can process signals above 80 MHz, well beyond the
Nyquist frequency of the DAC. The board is shipped
with the transformer and its associated components in
place. Refer to Figures 2 and 14 for schematics.
Figure 8 illustrates a frequency domain plot for the
transformer load. It was obtained by connecting a spectrum analyzer to J7 with a 50 Ω cable. The spectrum analyzer input impedance was set to 50 Ω.
F
= 50MHz
CLK
= 5MHz
F
OUT
SFDR = 68dB
Figure 9. Differential Amplifier Output
–4–
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