Analog Devices an417 Application Notes
AN-417
a
ONE TECHNOLOGY WAY • P.O. BOX 9106
•
NORWOOD, MASSACHUSETTS 02062-9106
APPLICATION NOTE
617/329-4700
•
Fast Rail-to-Rail Operational Amplifiers Ease Design Constraints in Low Voltage
High Speed Systems
by Eamon Nash
Movement towards lower power supply voltages is
driven by the demand that systems consume less and
less power coupled with the desire to reduce the number of power supply voltages in the system. Lowering
power supply voltages and reducing the number of supplies has obvious advantages. One such advantage is to
lower system power consumption. This has the additional benefit of saving space. Lowering overall power
consumption has a residual benefit in that there may no
longer be a need for cooling fans in the system.
However, as the traditional system power supply
voltages of ±15 V and ±12 V give way to lower bipolar
supplies of ±5 V and single supplies of +5 V and +3.3 V, it
is necessary for circuit designers to understand that designing in this new environment is not simply a matter
of finding components that are specified to operate at
lower voltages. Not all design principles used in the
past can be directly translated to a lower voltage
environment.
different power supply conditions (e.g., ±5 V, +5 V and
+3 V), along with corresponding loading conditions, are
useful and necessary here.
Rail-to-rail amplifiers are seen as a solution to the
dilemma of decreasing power supply voltages. The term
rail-to-rail, while not exactly defined, refers to devices
whose inputs and/or outputs can swing close to both
rails. This definition does not put an exact value on
“close to both rails”, nor does it specify the loading conditions under which rail-to-rail performance must be
maintained. Rail-to-rail op amps are a subset of singlesupply op amps which are devices that operate on a
single rail. The inputs and outputs of a single-supply op
amp may or may not be able to approach the rails. In
order to work successfully with rail-to-rail and singlesupply op amps, an basic understanding of some commonly used output stages is necessary.
+V
S
+V
S
Reducing the power supply voltage to a typical op amp
has a number of effects. Obviously, the signal swings
both at the input and output are reduced. The required
headroom between signal and rail (typically 1 V to 2 V in
conventional amplifiers), which is of lesser importance
with power supplies of ±15 V, now drastically reduces
the usable signal range. While this reduction does not
normally increase noise levels in the system, signal-tonoise ratios will be degraded. Because the designer can
no longer use techniques such as increasing power supply voltages and signal swings in order to “swamp”
noise levels, greater attention must be paid to noise
levels in the system.
Both bandwidth and slew rate decrease as power supplies drop. However, it should be noted that smaller
signal swings need lower slew rates to maintain the
same bandwidth. In choosing an operational amplifier,
close study of the data sheet is essential. Data sheet
specifications that list slew rate and bandwidth under
OUTPUT
–V
S
COMMON EMITTER
Figure 1. Common Op Amp Output Stages
Figure 1 shows two typical high speed op amp output
stages. The emitter-follower stage is widely used in low
distortion op amps. Its output voltage swing is limited to
slightly greater than one diode drop from the rails. In
reality, the headroom is closer to 1 V. In order to maintain low distortion at high frequencies, even more
headroom may be required, reducing the available
–V
S
EMITTER FOLLOWER
OUTPUT
R
L
50Ω TO
500Ω
peak-to-peak swing even further. Adding an external
load resistor (typically 50 Ω to 500 Ω) referenced to the
negative rail (this would be ground in a single-supply
application) provides a pull-down path to the output.
This, combined with the biasing on the bases of the NPN
and PNP transistors, allows the PNP transistor to shut
off. This allows the output to be pulled close to the negative rail so that the output stage behaves much like a
simple NPN follower. This only allows the voltage to approach the negative rail. The load resistor would have to
be referenced to the positive supply to bring the output
voltage close to the positive rail. Another potential
drawback of this configuration is the large load current
that would be drawn for signal swings greater than a
few hundred millivolts. Using a 50 Ω pull-down resistor,
for example, would draw a current from the op amp of
40 mA if a 2 V p-p swing was desired.
The common-emitter stage shown allows the output to
swing to within the transistor saturation voltage, V
CESAT
of both rails. For small amounts of load current (less
than 100 µA), the saturation voltage may be as low as 5
mV to 20 mV; but for higher load currents, the saturation
voltage may increase to several hundred millivolts (for
example, 500 mV at 50 mA). This type of output stage
has higher open-loop output impedance than an emitter
follower stage and is more likely to distort when driving
such nonlinear loads as flash converters. It is important
though not to look at open loop output impedance in
isolation. Closed loop output impedance, Z
, is given by
o
the formula
Z
Z
where
Z
is the open loop output impedance,
o
open loop gain and β is the feedback factor (
o
=
o
1+
a
β
o
a
is the
o
a
β is com-
o
monly referred to as Loop Gain). So a large open loop
gain, of 100 dB for example, would reduce the output
impedance of an op amp, connected as a unity gain
buffer, by a factor of 100,000. As frequency increases,
the decreasing open loop gain will cause the output
impedance to increase.
of the available voltage range. Step-up transformers can
increase voltages to an arbitrarily high level, but at the
cost of increased output current from the driving amplifier. The following collection of common high speed
applications seeks to illustrate the challenges involved
in designing low voltage analog circuits and looks specifically at the techniques involved in obtaining optimal
performance when using rail-to-rail op amps.
Driving High Speed ADCs
While most modern high speed ADCs operate from
single supplies, they are still most often used in signal
chains that have bipolar supplies. Because singlesupply ADCs typically have lower quiescent currents
than their dual supply equivalents, the main impetus
behind this trend is the power that is saved.
Bipolar signals usually need some form of level shifting
before being applied to a single-supply ADC. Because
,
the safe input voltage to an ADC should not generally
exceed the power supply voltages by more than a few
hundred millivolts, consideration must be given to the
protection of single-supply devices in a dual supply
environment.
Figure 2 shows an 8-bit 125 MSPS flash converter being
driven by a 240 MHz clamping amplifier. The ADC uses
ECL logic and is powered from a single –5.2 V supply.
The input voltage swing is 2 V (–1 V ± 1 V). The device’s
absolute maximum ratings specify a safe input voltage
range to be between –V
and +0.5 V. While choosing a
S
rail-to-rail amplifier to run from the same single supply
would inherently protect the ADC from overvoltage,
powering the op amp from a bipolar supply is more
appropriate in this example.
Even though a rail-to-rail amplifier running on a single
supply of –5.2 V would be capable of swinging most of
the way up to ground, signal distortion tends to degrade
significantly as voltages approach the rails. A more reasonable approach involves powering the op amp with
bipolar supplies so that there is a large amount of headroom (5 V on the positive side and 3 V on the negative
side) between the signal and the rails.
Even though rail-to-rail amplifiers can typically swing to
within a few tens of millivolts of the power supplies,
there is generally a tradeoff between distortion and
signal swing. Data sheets of op amps usually specify
optimum distortion with output signals that do not exercise the complete available voltage range. As signal
levels approach within a few hundred millivolts of the
rails, distortion performance degrades significantly. The
best distortion/signal level tradeoff in rail-to-rail op
amps, with common-emitter output stages, occurs when
there is a signal-to-rail headroom of about 500 mV to
each rail. This is a generalization and the optimal value
will also depend on loading.
In addition to using rail-to-rail amplifiers, there are a
number of techniques that can be used to increase signal swings without having to increase power supply
levels. Differential drive circuits make more efficient use
Using two resistor dividers, the input referred clamp
voltages of the op amp are set to ±0.55 V or 50 mV
greater than the normal maximum input voltages. In
order to map the ±0.5 V input voltage into the 0 V to –2 V
input range of the ADC, the op amp provides a gain of
two and uses a +2.5 V reference to give a level shift of
1
–1 V
. The output referred clamp voltages translate to
+0.1 V and –2.1 V. The 1N5712 Schottky diode provides
additional protection during power-up and actually
holds the maximum voltage at the ADC’s input to about
+0.3 V. A 50 Ω resistor in series with the op amp’s output
limits the current through the diode during overvoltage
as well as isolating the output stage from the signal
dependent capacitive load of the flash ADC
maximum value of 22 pF. The negative clamping level of
–2.1 V, while not necessary to protect the converter, prevents excessive negative overdrive of the analog input.
–2–
2
that has a
10µF
+5V
0.1µF
BIPOLAR
SIGNAL
+/–0.5 V
+5V
+
AD780
+2.5 V REF
0.1µF
R3
750Ω
R
75Ω
T
0.1µF
–5.2V
R1
499Ω
806Ω
AD8037
806Ω 100Ω
R2
301Ω
100Ω
V
= +0.55V
H
V
= –0.55V
L
1N5712
49.9Ω
AD8037 OUTPUT
CLAMPS AT +0.1 V, –2.1 V
AD9002
FLASH CONVERTER
(8-BITS, 125 MSPS)
V
= –1 +/–1V
IN
SUBSTRATE
DIODE
–5.2V
0.1µF
Figure 2. AD9002, 8-Bit, 125 MSPS Flash Converter
In addition to and perhaps more important than providing the necessary signal conditioning, a drive amplifier
must provide a low impedance source which does not
degrade the ADC’s dynamic capabilities. The signal to
noise plus distortion (S/(N+D) or SINAD) plot of the ADC
should generally be used as the first selection criterion
for the drive amplifier. This plot should be compared to
the op amp’s total harmonic distortion plus noise
(THD+N). Comparing like with like is important here and
both measurements should reference similar signal
levels, power supply voltages and bias conditions as will
be used in the actual circuit. The amplifier’s loading conditions should also be similar to those presented by the
ADC. As a general rule, in order to prevent the op amp
from degrading the dynamic performance of the ADC,
its THD+N should be 6 dB to 10 dB better than the ADC’s
S/(N+D) at the highest signal frequency
3
(usually but not
always the ADC’s Nyquist frequency). In some applications, such as spectral analysis, low distortion can be
more important than low noise. In such cases, comparing the op amp’s THD to the ADC’s distortion (usually
specified as spurious free dynamic range or SFDR) is
more meaningful. Once again, choosing an op amp
whose distortion is 6 dB to 10 dB better than the ADC’s is
appropriate.
This selection criterion can be used where the ADC’s input
impedance is fixed and does not change during the conversion process. This is usually the case with ADCs designed on bipolar processes. On the other hand, ADCs
designed on CMOS processes typically connect the
sample-and-hold switches directly to the analog input.
This generates transient currents during the conversion
that the external drive circuit must be able to deliver. In
addition to this, the (relatively low) on-impedance of
CMOS switches has some signal dependency. The
ADC’s analog input may, therefore, exhibit a signal-leveldependent input impedance, which leads to distortion.
Figure 3 shows a 12-bit 10 MSPS single-supply CMOS
ADC being driven by a differential amplifier, created using a single-supply dual op amp. The input stage of the
ADC is a differential sample-and-hold. The switches that
open and close at the sampling frequency are shown in
track mode. The capacitances denoted C
PARCPIN
are
about 16 pF and represent the combined stray capacitance of the switches and the input pins. C
and CH repre-
S
sent the sampling and hold capacitances respectively. In
the track mode, the differential input voltage is applied
to the C
capacitors. When it goes into hold mode, the
S
voltages on these capacitors are transferred to the hold
capacitors.
The input range of the ADC is set, by pin strapping, to 2 V
peak-to-peak. The differential drive amplifier sets up a
common-mode voltage of 2.5 V. From a signal distortion
point of view, this is the optimal configuration for a number of reasons.
In systems that truly operate on a single power supply, it
can often be difficult to maintain dc coupling from
source all the way to the ADC. In such systems, a virtual
ground is often created, usually centered halfway between the rails. This introduces the question of an optimum input voltage range for a single-supply ADC. At
first glance, it would seem that a zero-volt referenced input might be desirable. But in fact, this places some severe constraints on both the ADC and its driving
amplifier because both must maintain full linearity and
low distortion at or near 0 V.
A more optimum voltage range for both ADC and op
amp is one that includes neither ground nor the positive
supply. A range centered around V
/2 is usually opti-
S
mum. For example, an input range of 2 V p-p centered
around +2.5 V is bounded by +1.5 V and +3.5 V. If the
dynamic specifications of single-supply op amps are
stated for a midscale bias condition, a direct specification comparison can be made to help in making an
–3–
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