AN-408
a
ONE TECHNOLOGY WAY • P.O. BOX 9106
AC Motor Control Using the ADMC200 Coprocessor
INTRODUCTION
This document describes the design of an ac motor control system using the ADSP-2115 digital signal processor (DSP) and the ADMC200 motion coprocessor. The
architecture illustrated in this application note can be
utilized for a number of systems, and was chosen for
illustration purposes only. The purpose of the document
is to demonstrate the use of the ADMC200 in the digital
implementation of a high speed motor control system.
The document starts with a system hardware description that illustrates the hardware simplification when using the ADMC200 and ADSP-2115. A typical control
scheme is described to demonstrate the ADMC200 features. A control algorithm is produced to match the described control scheme. The DSP control software is
presented in both pseudo code and in DSP assembly
code. This code demonstrates how the ADMC200 functions can be closely integrated into the control algorithm. Timing information is also presented which
shows how the shaft torque functions could be implemented in less than 20 µs.
SYSTEM HARDWARE
The complete system consists of a permanent magnet
ac servo motor with a shaft mounted resolver, a three
phase power inverter, and the motor control circuit. The
primary ICs in the control circuit are the ADSP-2115, the
ADMC200, and the AD2S90 resolver-to-digital converter
(RDC). The DSP is the shaft control processor and carries
out all the motion control and torque current loop functions. The ADMC200 is the interface between the DSP
and the inverter, and in addition provides the vector
•
NORWOOD, MASSACHUSETTS 02062-9106
by Aengus Murray and Paul Kettle
APPLICATION NOTE
617/329-4700
•
transformation functions required for ac motor control.
The interface to the host controller can be either via the
DSP data and address bus or via the serial port.
The motion control software is stored on an external
8-bit EPROM and is automatically loaded into the DSP’s
1K words of internal program RAM on power-up. Each
of the 24-bit program words is stored on the EPROM in a
4-byte segment. The DSP boot firmware copies the program from the EPROM to the internal RAM in the correct
order to rebuild the 24-bit wide program memory. This
arrangement limits the external EPROM requirement to
just a single slow memory device.
It is possible to switch between eight pages of program
memory RAM stored in a 32K EPROM. For example, the
first boot page could contain the programs which will
initialize all data variables (look up tables, etc.), configure the ADMC200 registers (setup PWM registers, etc.),
and perform self-diagnostic functions. While the second
page can contain the motion control algorithms which
are loaded at the end of the initialization phase.
The ADMC200 device can be connected directly to the
DSP data and address busses, as described in detail in
Appendix C. The internal registers can be written to in
the same way as data RAM placed in the low memory
address space. The shaft control algorithm can be timed
through the ADMC200 CONVST pin or via the interrupt
pin on the DSP.
8K X 8
EPROM
(BOOT)
ADSP-2115
IRQ
ADDR
ADMC200
CONTROL
SEQUENCER
PARK
CLARKE
CENTER
BASED
PWM
t
A
t
C
3 PHASE
INVERTER
PM AC
MOTOR
DATA
CONTROL
SP1 SP0
HOST
REGISTERS
Figure 1. Motion Control Hardware
THE CONTROL SYSTEM
Figure 2 below illustrates a field oriented control
scheme for a permanent magnet synchronous motor.
The outer position and velocity loop calculates the
torque demand which is the input I
current loops. At speeds less than the base speed, the I
* reference for the
q
d
reference current will be zero. If an extended constant
power speed range is required, the field control scheme
can introduce some field weakening by setting a negative I
* value as a function of the motor speed.
d
*Reference input to controller.
I
4 CH SS
11–BIT
ADC
B
I
C
V
BUS
RESOLVER
ω
θ
AD2S90
The analog-to-digital converter (ADC) block within the
ADMC200 samples the motor currents; the vector transformation block performs a reverse Clarke and Park vector transformation on these ac current waveforms,
mapping them into equivalent direct and quadrature
*
current components within a rotating reference frame (I
d
Iq). A current loop control algorithm implemented on the
DSP calculates desired V
and Vq voltages for the motor.
d
Finally the ADMC200 forward vector transformation
block performs a forward Park and Clarke transformation, mapping these direct and quadrature motor voltages into ac voltages within the stator reference frame.
The DSP scales and then write these results to the PWM
block of the ADMC200.
ADSP-2115
–
+
–
FIELD
Id*
CONTROL
*
REFERENCE INPUT TO CONTROLLER
I_CONT
I_CONT
+
ω
Iq*
Figure 2. Motion Control System
V
q
V
d
I
d
I
q
POSITION
VELOCITY
CONTROL
AND
PARK
CLARKE
ADMC200
V
A
V
B
–1
V
C
–2–
PWM
CLARKE
PARK
θ
ω
t
A
3 PHASE
INVERTER
t
C
I
B
I
–1
C
= –IB –I
I
C
A
RDC
PM AC
MOTOR
RESOLVER
CONTROL ALGORITHM
An outline of the control algorithm, based on the
scheme in Figure 2, is given in Table I. The functions in
bold are implemented on the ADMC200 coprocessor.
The scheduling of the control algorithm is synchronized
with the ADC interrupt service routine. In this application the ADC will generate an interrupt at a rate of
10 kHz. The torque control loop is realized at this frequency, while the motion loop is scheduled every fourth
ADC sample. The motion control loop can be segregated
into a
posterior
a priori
portion is executed during the first three time
slices while the
and
a priori
posterior
measurement portions. The
portion is executed in the forth
interval. The basic torque loop functions can be carried
out in less than 20 µs; this leaves the remaining 80% of
the time for the motion control loop and other functions.
The code required takes up less than 10% of the available 1K of internal program RAM.
Table I. Control Algorithm Outline
inputs ADMC200 Motion_Control out ADMC200
write register functions read register
Read_RDC ω ADCAUX
ρ
ω position_velocity_loop Iq*
ω Field_control I
* = 0 for ω < ω
(I
d
base
)
*
d
inputs ADMC200 Torque_control out ADMC200
write register functions register
Sample_phase_ currents I
I
b
I
c
PHIP2/VQ Clarke_Park
PHIP3 I
–1
ρ RHO (Ia = –Ib –Ic) I
I
q
I_control_q V
b
I
c
I
d
q
a
q
ADCV
ADCW
ID/PHV1/VX
IQ/PHV2
IX/PHV3
Iq*
ω
I
d
I_control_d V
d
Id*
ω
V
q
V
d
PHIP1/VD Park _ Clarke
PHIP2/VQ V
ρ RHOP V
V
a
V
b
V
c
T
a
T
b
T
c
PWMCHA PWM_out
PWMCHB
PWMCHC
PWM_scale T
–1
V
a
b
c
a
T
b
T
c
ID/PHV1
IQ/PHV2
IX/PHV3
–3–