Analog Devices AN-407 Application Notes
AN-407
a
ONE TECHNOLOGY WAY • P.O. BOX 9106
AC Motor Control Experiments
Using the ADMC200-EVAL Board
INTRODUCTION
The ADMC200-EVAL board can be used to build a simple
motor control demonstration based around the ADMC200
motion coprocessor. The board is designed to interface
directly to the ADDS-2101-EZ-LAB or the ADMC21xxEZ-LAB boards through the 60-pin user interface connector. This board can be used with processors that are
compatible with the ADMC200 address and data bus.
The evaluation board is supplied with a DSP assembly
code for a demonstration program that exercises all the
ADMC200 functions.
The software provided with the evaluation board serves
two purposes. Running the software demonstrates
ADMC200 functions and verifies the operation of the IC.
The software can also serve as a useful template around
which to write motor control software using the
ADMC200.
This application note describes the ADMC200-EVAL
board hardware, setting up with the ADSP-2101 EZ-LAB
board, and a description of the demonstration software.
Instructions on how to load and run the software is given
in the
Running the Demonstration Program
section.
•
NORWOOD, MASSACHUSETTS 02062-9106
by Aengus Murray and Paul Kettle
APPLICATION NOTE
617/329-4700
•
A more detailed description of the ADMC200 functions and pinout is included in the product data
sheet. There is also a companion application note
describing the digital implementation of a high
speed motor control systems using the ADMC200/
ADMC201 and an ADSP-2105 DSP.
This document only relates to REV 2.0 of the
ADMC200-EVAL board and REV 2.0 of the demonstration software.
ADMC200-EVAL BOARD HARDWARE
The system block diagram is shown in Figure 1,
while the full circuit diagram is in Appendix A. The
board has the ADMC200/ADMC201 as the main component, a 74S138 address decoder, a 74LS04 hex inverting buffer, and some passive components. The
user connections to the board are made via three terminal blocks: PWM output, analog input, and digital
I/O. Separate analog (5 VA) and logic (5 VL) power is
supplied through a 4-way terminal block.
The analog input channels have Zener diode protection and a two-pole passive anti-aliasing filter with a
default cutoff frequency of 5 kHz. The reference input
DSP INTERFACE CONNECTOR (FOR ADSP-21xxEZ-LAB
JPG1..3
CLK
RDWR
PWMSTOP
RESET
JP2
A
AP
B
BP
C
CP
CS
7
4
1
3
8
7
4
0
4
ADDRESS
DECODE
AD 9..10,
AD 12..13
DMS
PWM CONNECTOR
D0..11 A0..3
J
P
1
POWER CONNECTOR DIGITAL CONNECTOR
U V W AUX
RC FILTER
NETWORK
ANALOG INPUT CONNECTOR
ADMC200
Figure 1. ADMC200-EVAL Board System Block Diagram
can be taken from the ADMC200/ADMC201 reference
output or through the analog connection block. The
CONVST pin can be connected to the PWMSYNC pin or
to the external digital I/O connector. The ADMC200/
ADMC201 PWM outputs are buffered using a 74LS04 hex
inverter to give active high PWM signals at the connector. Other signal formats can be obtained by using a different buffer.
The ADMC200 board connects to the ADSP-2101 data
and address busses via the 60-pin user interface connector. The ADMC200/ADMC201 data bus is connected to
the top 12 bits of the DSP data bus (D12 . . . D23). The
ADMC200/ADMC201 4-bit address bus is connected to
the lower 4 bits of the DSP address bus (AD0 . . . AD3).
The ADMC200/ADMC201 chip select line
using the 74S138 address decoder from the DSP address
lines AD4, AD5, AD12 and AD13. The memory space
between 1000 and 2FFF is used by the EZ-LAB Digital to
Analog Converter. The ADMC200 read registers are
memory mapped to the DSP data memory between 3000
and 300F. To allow read and write registers to have different names the write registers are mapped between
3010 and 301F. The DSP read, write and output clock
lines are connected directly to the ADMC200. The
ADMC200 interrupt line
rupt
IRQ2.
Power Supply Connections
The board requires a +5 V power supply. Separate analog (+5 VA and 0 VA) and logic (+5 VL and 0 VL) supply
connections are provided to minimize noise on supply
cables. It is recommended that the logic, analog, and signal grounds be connected to a common star point on the
board using jumpers JPG1. . . .
Jumper Configuration
The board has three ground planes: a logic ground plane
(0 VL), an analog ground plane (0 VA) and a signal
ground plane. These can all be connected to a common
star point using jumpers JPG1 . . . 3 as described in the
following table.
Table I. ADMC200-EVAL Ground Jumpers
JUMPER Position Function
JPG1 IN Connects Analog Ground 0 VA to
JPG2 IN Connects Logic Ground 0 VL to
JPG3 IN Connects Signal Ground SGND to
IRQ is connected to DSP inter-
Star Point
Star Point
Star Point
CS, is derived
The ADMC200/ADMC201 A/D converter connections can
be configured using jumpers JP1 and JP2 as described in
Table II. Here, the names in bold are ADMC200/ADMC201
pins, while the names in italic are brought from one of the
terminal blocks. The start of conversion signal can be synchronized to the PWM switching frequency (using
PWMSYNC), or to an external CONVST signal. The A/D
reference (REFIN) can be derived from the on board reference (REFOUT) or through the analog connector.
Table II. ADMC200/ADMC201-EVAL ADC Jumpers
Jumper Position Function
JP1 1–2 Connects
2–3 Connects
JP2 1–2 Connects
2–3 Connects REFIN to
JP3 1–2 Connect IRQ on ADMC200/ADMC201
to DSP IRQ2
2–3 Connect IRQ on ADMC200/ADMC201
to DSP IRQ1
Analog Input Signals
Analog inputs to the Analog to Digital (A/D) converter
are brought through a 14-way connector block, described in Table III. There is a two-stage passive antialiasing low-pass filter at the input to each of the A/D
converter channels. The filter R and C values are 10 kΩ
and 3.3 nF which gives a cutoff frequency of 5 kHz. Other
cutoff frequencies can be selected by replacing the resistor networks (7XR DIL isolated resistor network).
Table III. ADMC200-EVAL Analog Connector
Connector
Name ADMC200 Connection
SHIELD Connected to 0 VL Ground Plane
SGND Connected to SGND Ground Plane
U Connected to U via RC Filter
SGND Connected to SGND Ground Plane
V Connected to V via RC Filter
SGND Connected to SGND Ground Plane
W Connected to W via RC Filter
SGND Connected to SGND Ground Plane
AUX0 Connect to AUX
AUX1 ADMC201 Only
AUX2 ADMC201 Only
AUX3 ADMC201 Only
SGND Connected to SGND Ground Plane
REFIN Connected to REFIN (Pin)
PWMSYNC
EXTSAMPLE
REFOUT
to
REFIN
to
CONVST
to
REFIN
CONVST
–2–
PWM Output Signals
The six PWM outputs signals are buffered by a 74LS04
HEX buffer IC and brought to the 8-way terminal block. If
active low signals are required, direct from the
ADMC200, this inverter IC can be bypassed. The buffer
can be replaced by an open collector device to drive
opto-isolating LED input type gate drive circuits. The
PWM STOP input is brought directly from the connector
to ADMC200. If this input is unused, it should be pulled
low through a 10K resistor to prevent spurious tripping
of the PWM signals.
Table IV. ADMC200-EVAL PWM Connector
Connector Name ADMC200 Connection
0 VL Connected to 0 VL Ground Plane
PWMSTOP Input to ADMC200 STOP Pin
CP Driven by ADMC200 CP through Buffer
C Driven by ADMC200 C through Buffer
BP Driven by ADMC200 BP through Buffer
B Driven by ADMC200 B through Buffer
AP Driven by ADMC200 AP through Buffer
A Driven by ADMC200 A through Buffer
Digital I/O Signals
Only two of the digital I/O signals are used with the
ADMC200. An external start of conversion signal can
be supplied via the EXTSAMPLE connection, and the
PWMSYNC pulse is brought out to this connector.
Data and Address Bus Interface
The ADMC200 board connects to the ADSP-2101 data
and address busses via the 60-pin user interface connector. The ADMC200 4-bit address bus is connected to
the lower 4 bits of the DSP address bus (AD0 . . . AD3).
The ADMC200 chip select line (
74S138 address decoder from the DSP address lines
AD9, AD10, AD12 and AD13, according to Table VI. The
memory space between 1000 and 2FFF is used by the
EZ-LAB DAC. The ADMC200 read registers are memory
mapped to the DSP data memory between 0x3000 and
0x300F. To allow read and write registers to have different names the write registers are mapped between
0x3010 and 0x301F. The memory map for the system is
given in Table VII.
The DSP reads and writes data directly to and from the
ADMC200 registers. The ADMC200 data bus is connected to the top 12 bits of the DSP data bus (D12 . . .
D23), thus lowest 4 bits read by the DSP will always be
invalid. This data bus connection scheme easily allows
the use of the DSP fixed 1.15 mode of operation. Therefore, a full-scale negative input on the A/D converter,
giving 2s complement number 0x800 will be read into
the DSP as 0x8000 HEX or –1.0000000 fixed point (See
Chapter 2 of the ADSP-2100
ADMC200 interrupt line is connected to DSP interrupt
IRQ2.
CS) is derived using the
Family User’s Manual
). The
Table V. ADMC200-EVAL Digital I/O Connector
Connector Name ADMC200 Connection
0 VL Connected to 0 VL Ground Plane
PIO0 ADMC201 Only
PIO1 ADMC201 Only
PIO2 ADMC201 Only
PIO3 ADMC201 Only
PIO4 ADMC201 Only
PIO5 ADMC201 Only
PWMSYNC ADMC200 PWMSYNC Output
EXTSAMPLE External CONVST Signal Input
–3–
Table VI. ADMC200-EVAL Chip Select Logic
21xx EZ-LAB DMS AD13 AD12 AD10 AD9
ADMC200-EVAL DMS A3 A2 A1 A0 ADMC200 CS ADMC200 RESET
HXXXX1 1
L11001 0
L11010 1
Table VII. ADMC200-EVAL Memory Map
Address Direction ADMC200
HEX & (Wait States) Address Mnemonic Function
0x1000 W(2) Write_DAC0_ DAC Channel 0 Data Input
0x1001 W(2) Write_DAC1 DAC Channel 1 Data Input
0x1002 W(2) Write_DAC2_ DAC Channel 2 Data Input
0x1003 W(2) Write_DAC3_ DAC Channel 3 Data Input
0x2000 W(2) Load_DAC_ Load DAC Data
0x3000 W(0) ADMC200_RESET_ ADMC200 Chip Reset
0x3000 R(0) 0 ID_PHV1_ Forward/Reverse Rotation Result
0x3001 R(0) 1 IQ_PHV2_ Forward/Reverse Rotation Result
0x3002 R(0) 2 IX_PHV3_ Forward/Reverse Rotation Result
0x3003 R(0) 3 IY_VY_ Forward/Reverse Rotation Result
0x3005 R(0) 5 ADCV_ A/D Conversion Result
0x3006 R(0) 6 ADCW_ A/D Conversion Result
0x3007 R(0) 7 ADCAUX_ A/D Conversion Result
0x3008 R(0) 8 ADCU_ A/D Conversion Result
0x300E R(0) E SYSSTAT_ System Status Register
0x3010 W(0) 0 RHO_ Forward Rotation Angle Input
0x3011 W(0) 1 PHIP1_VD_ Forward/Reverse Rotation Input
0x3012 W(0) 2 PHIP2_VQ_ Forward/Reverse Rotation Input
0x3013 W(0) 3 PHIP3_ Reverse Rotation Input
0x3014 W(0) 4 RHOP_ Reverse Rotation Angle Input
0x3015 W(0) 5 PWMTM_ PWM Period Input
0x3016 W(0) 6 PWMCHA_ PWM Channel On Time Input
0x3017 W(0) 7 PWMCHB_ PWM Channel On Time Input
0x3018 W(0) 8 PWMCHC_ PWM Channel On Time Input
0x3019 W(0) 9 PWMDT_ PWM Deadtime Input
0x301A W(0) A PWMPD_ PWM Pulse Deletion Input
0x301D R/W(0) D SYSCTRL_ System Control Register
–4–
The ADMC200-EVAL board connects to the DSP over
the EZ-LAB user interface connector according to the
following table. Here, the ADMC200 connections in bold
are direct connections to the DSP, while the connections
Table VIII. ADMC200-EVAL DSP Interface Connector
ADSP-2101 ADMC200 Pin Pin ADMC200 ADSP-2101
IRQ2 IRQ2 1 2 GND GND
NC 3 4 NC
NC 5 6 NC
NC 7 8 NC
IRQ1 IRQ1 910NC
HOST_RESET HOST_RESET 11 12 NC
NC 13 14 NC
NC 15 16 NC
WR
RD
GND GND 21 22 NC
AD0 A0 23 24 NC
AD1 A1 25 26 NC
AD2 A2 27 28 NC
AD3 A3 29 30 D12 D12
GND GND 31 32 D13 D13
AD4 NC 33 34 D14 D14
AD5 NC 35 36 D15 D15
AD6 NC 37 38 GND GND
AD7 NC 39 40 D16 D16
AD8 NC 41 42 D17 D17
GND GND 43 44 D18 D18
AD9 AD9 45 46 D19 D19
AD10 AD10 47 48 D20 D20
AD11 NC 49 50 D21 D21
AD12
AD13
GND GND 55 56 GND GND
DMS DMS 57 58 CLK CLOUT
GND GND 59 60 GND GND
WR 17 18 NC
RD 19 20 GND GND
AD12
AD13
51 52 D22 D22
53 54 D23 D23
shown in
nals for the ADMC200. The relevant EZ-LAB DSP connections are shown for reference.
italic
are used to produce CS and RESET sig-
–5–
Using the ADMC200-EVAL Board with the ADSP-2101
EZ-LAB
To run the supplied demonstration software the ADSP2101 EZ-LAB board IRQ2 must be enabled from the user
interface connector (60-pin IDC), and The FLAG IN pushbutton must be enabled. The required jumper configurations are shown below. If you are using higher clock
frequencies you need to edit the software and run in
the divide-by-two clock mode (see source code listing).
Table IX. ADSP-2101 EZ-LAB Jumper Configuration
Jumper Position Function
JP2 3-2 Enable FLAG IN Pushbutton
JP3 . . . JP8 Don’t Care
JP1 2-1 Enable IRQ2 from the User
Interface Connector
ADMC200-EVAL Board Software
The demonstration software exercises the three main
functional blocks on the ADMC200: the A/D converter,
the vector transformation block, and the PWM block.
The program can be loaded on to the EZ-LAB using the
EZ-ICE or by burning a boot EPROM. The program runs
in a loop timed by the ADMC200 A/D converter interrupt
signal that is synchronized to the PWM frequency.
There are four modes of operation that can be
sequenced through by pressing the FLAG IN button on
the EZ-LAB board:
• In the ADC_TEST mode the program reads the four
A/D channels and writes the values to the EZ-LAB
DAC outputs DAC0 . . . 3.
• In the FOR_PARK_TEST mode two of the A/D channels V and W are used as the Vd and Vq inputs for a
forward PARK and CLARKE transformation. The rotation angle is incremented at a constant rate and the
PARK results are displayed on DAC0 . . . 2 as a set of
three phase voltages.
• In the REV_PARK_TEST mode the most recent PHV1
. . . 3 results of the forward PARK and CLARKE transformation are used as the PHIP2 and PHIP3 inputs for
a reverse PARK and CLARKE transformation. The rotation angle is again incremented at a constant rate
but this time the PARK results displayed on DAC0 . . .
1 as a set of quadrature sin/cos voltages.
• In the PWM_TEST mode a set of three phase voltages
are incremented by 1 count per PWM cycle, thus
giving a slowly varying duty cycle on each of the
channels.
The demonstration software disks includes a system
file ADMC200.SYS, two include files ADMC200C.H,
ADMC200P.H, the main DSP code A200EVAL.DSP, and a
GO batch file.
The System Hardware File: ADMC200.SYS (Appendix B)
The system file describes the ADMC200 EVAL and the
ADSP-2101 EZ-LAB board address decode schemes. The
EZ-LAB DAC ports are mapped between memory locations 0x1000 and 0x2000. The ADMC200 reset line
is mapped to the data memory location 0x3000. The
ADMC200 read registers are mapped to data memory
locations running from 0x3000 to 0x300F. The ADMC200
write registers are mapped to data memory locations
running from 0x3010 to 0x301F, this does not effect the
address decode hardware but it allows the use of different register names for data memory reads and writes.
ADMC200 Constants File: ADMC200C.H (Appendix C)
This file includes a number of universal constants used
in the program. The first group of constants define some
ADSP-2101 memory mapped registers. The second
group of constants define ADSP-2101 interrupt masks.
The next group of constants define the bits that must be
set in the ADMC200/ADMC201 system control register to
operate the device in different modes, e.g., AUX_EN:
enable the A/D AUX channel by setting Bit 7. The last set
of constants define the bits in the SYSSTAT register that
should be compared with in order to determine the
ADMC200 interrupt source.
ADMC200 Port File: ADMC200P.H (Appendix D)
This file includes all the port definitions required for the
ADMC200 memory mapped registers.
ADMC200 DSP Code: A200EVAL.DSP (Appendix E)
There is a single file for the main DSP assembly code.
The file can be edited to change the user program
parameters, such as system clock frequency etc., as
listed below. These parameters, in SI units, used to
derive program constants such as the PWM period in
clock counts etc.
The code at the beginning of the program performs
initialization of the DSP and ADMC200. The program is
interrupt driven. The main part of the code consists of
interrupt service routines (ISR) which services the
ADMC200 interrupt. There are two sources of ADMC200
interrupt enabled enabled, namely the A/D conversion
and the Park and Clarke transformation. The ISR is
partitioned into three portions, one for each of the
interrupt sources and an initial portion that parses the
ADMC200 SYSSTAT register to determine the source of
the interrupt and subsequently call one of the two
service portions. The A/D portion of the ISR is subdivided into four sections depending on which one of
four modes is in operation.
The source code file can be split into a number of sections:
1. Definition of program constants
2. Definition of program variables
3. Interrupt jump table code
4. Initialization code
5. Mode change code
6. Interrupt service routine code
7. Subroutine code
–6–
Loading...