Analog Devices AN-400 Application Notes

AN-400

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ONE TECHNOLOGY WAY • P.O. BOX 9106

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APPLICATION NOTE

617/329-4700

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Considerations for Selecting a DSP Processor—Why Buy the ADSP-2181?

(The Analog Devices ADSP-2181 vs. Texas Instruments & Motorola Fixed-Point DSPs)

INTRODUCTION

You should use the ADSP-2181 Digital Signal Processor
for your high performance, fixed-point DSP applications
because this processor provides all the memory, I/O,
and interface support you need in a single chip. Table I
shows a comparison of the ADSP-2181, TMS320C5x,
and DSP56000 processors. The ADSP-2181 beats the
other DSPs with the following features:

• 32K words of on-chip RAM (nearest competitor has

9.5K words)

• Glue-less (no decode required) interface for off-chip
RAM and I/O peripherals

• Integrated 8 and 16-bit DMA support

This application note explains how the ADSP-2181’s on­chip RAM, off-chip RAM & I/O interface, and integrated
DMA support provide increased performance and de­creased system costs compared to Texas Instruments
and Motorola fixed-point DSPs.

COMPARING THE DSP PROCESSORS—ADSP-2181,
TMS320C5X, AND DSP56000

The point of comparing DSP processors is to determine
which provides the features you need to develop your
DSP system and run your DSP applications. This section
first examines typical system and algorithm require­ments then reviews how each of the DSPs meet these
needs.

DSP applications require high speed RAM. Data and
instructions for the DSP are stored in RAM and accessed
at run time. As shown in Table II, many common RAM­intensive applications require 9.5K words of RAM or
more; this information was gathered from Analog
Devices applications engineers using ADSP-2100 Family
DSPs.

To support these types of applications, DSP systems
must

either

use a DSP with sufficient on-chip RAM
include sufficient off-chip DSP RAM. And, the RAM used
must have a fast enough access speed to
DSP’s operation. From the data in Tables I and II, you
can see that the ADSP-2181 is the only fixed-point DSP
that provides sufficient on-chip RAM to support all these
typical DSP algorithms.

not

impair the

or

Table I. Comparison of Fixed-Point DSP Costs and Features

DSP Processor ADSP-2181 DSP56002 TMS320C50 TMS320C53

On-Chip RAM 32K words 1K word 9.5K words 3.5K words

“Glue-Less” Off-Chip RAM
and I/O Interface? Yes No No No

DSP Instruction Rate 33 MIPS 20 MIPS 40 MIPS 40 MIPS

Table II. Typical DSP Algorithms with Approximate MIPS and Memory Requirements

Algorithm Approximate MIPS Required Approximate RAM Required

V.32bis or V.32terbo FAX/Modem 16 16K words PM, 16K words DM

20 Voice Music Synthesis 20 6K words PM, 4K words DM

Full Duplex Speaker Phone 13 2K words PM, 2K words DM

Digital Answering Machine 8 5K words PM, 1K word DM

GSM, 13 kbps Compression/Decompression 4 2K words PM, 1K word DM

CELP, 4.3 or 7.5 kbps Compression/Decompression 12.5 1.5K words PM, 1.5K words DM

MPEG Layer2, 64 kbps Compression 16 5K words PM, 4K words DM

MPEG Layer2, 64 kbps Decompression 10 1K words PM, 8.5K words DM

Dolby AC-2, 117 kbps Compression/Decompression 13 4K words PM, 8.5K words DM

There are two factors that influence the access time
(speed) of RAM needed in DSP systems—DSP instruc­tion rate and decode logic. At DSP instruction rates of
25 MIPS and higher, SRAM with access times of 15 ns or
less are required for full-speed DSP operation (zero wait
state). Systems using address decoding logic require
SRAM with faster access times to compensate for the
delay incurred by the decoding.

Another important issue tied to using off-chip RAM in a
DSP system is the time involved in designing, debug­ging, and using an interface for off-chip RAM. From the
number of application notes, articles, and user’s manual
pages devoted to developing interfaces for off-chip RAM
by all DSP vendors, it is easy to conclude that building
an off-chip RAM interface requires a considerable de­sign time investment.

DSP systems that use off-chip RAM face a performance
bottleneck. Many DSP operations require two reads
from data memory and one read from program
memory. The ADSP-2181, with its large on-chip RAM
and triple internal memory bus, can complete these ac­cesses and execute the instruction in one instruction
cycle. Using an off-chip memory interface on other DSPs
to complete this same operation requires three instruc­tion cycles for the memory reads alone.

One technique for reducing DSP overhead (the number
of DSP cycles/access) related to RAM access is Direct
Memory Accessing (DMA). Using DMA, an external de­vice can access internal DSP memory without any inter­vention by the DSP. This easy access to DSP internal
RAM lets you interface the DSP and host devices with­out incurring a lot of DSP overhead with each DMA data
transfer.

All DSP systems have some type of peripherals (DACs,
ADCs, CODECs, etc.) connected to the DSP. Many DSPs
include specialized interface ports (serial, parallel, or
both) for these peripherals. For connecting parallel
I/O DSP peripherals, a DSP with a separate I/O memory
space, I/O control lines, and I/O specific instructions
provides some advantages. Having a separate I/O
space for peripherals implies that you do not have to
use DSP memory addresses to memory map the exter­nal I/O devices. By supporting control lines to external
I/O peripherals, the DSP reduces the amount of decode
and control logic needed in your system. I/O specific
instructions for controlling the I/O interface ease I/O
programming.

The sections that follow describe the features of each
processor, and the conclusion section of this note pre­sents a table of the comparison results. Each compari­son feature contributes or detracts from the ease of
DSP system and software development. The compari­son topics covered are the following:

• Internal DSP RAM Size

• External Memory and I/O Interface

• System Design Simplicity

The Texas Instruments TMS320C5x

The TMS320C5x DSPs are general purpose 16-bit,
fixed-point DSPs. Depending on the device version,
TMS320C5x parts include up to 9.5K words of on-chip
program/data RAM, up to 16K words of ROM, a stan­dard serial port, a time-division-multiplexed (TDM) se­rial port, and a 16-bit timer. The four variations of the
TMS320C5x are TMS320C50 (9.5K words on-chip
RAM), TMS320C51 (1.5K words on-chip RAM),
TMS320C52 (1K word on-chip RAM), and TMS320C53
(3.5K words on-chip RAM). Table III lists the compari­son features for the TMS320C52 processor.

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