Analog Devices AN-397 Application Notes

AN-397

a

ONE TECHNOLOGY WAY • P.O. BOX 9106

•

NORWOOD, MASSACHUSETTS 02062-9106

APPLICATION NOTE

617/329-4700

•

Electrically Induced Damage to Standard Linear Integrated Circuits:

The Most Common Causes and the Associated Fixes to Prevent Reoccurrence

by Niall Lyne

INTRODUCTION

The sensitivity of electronic components to transient
electrical overstress events is a well-known problem,
exacerbated by the continuing evolution of integrated
circuits. Smaller geometries, increased circuit densities,
and the limited area allotted to on-chip protection all
tend to increase this sensitivity. In an effort to minimize
costs in each particular segment of system implementa­tion, the burden of transient protection is often shifted to
other, less efficient means.

This application note will first review the nature of the
threat to integrated circuits in an operating environ­ment, and then briefly discuss overall device protection
from the following: (1)
handling, automatic board insertion equipment, etc., (2)

LATCH-UP

errors, floating ground(s) due to a loose edge connec­tors, etc., and finally, (3)
generated from a power supply, a defective circuit
board, during circuit board troubleshooting, etc.

generated from power-up/down sequencing

ESD

events caused by human

HIGH VOLTAGE TRANSIENTS

Techniques for protection from “zapping” depend on
the stage of manufacture. During the manufacturing of
integrated circuits and assembly of electronic equip­ment, protection is achieved through the use of well­known measures such as static dissipative table tops,
wrist straps, ionized air blowers, antistatic shipping
tubes, etc. These methods will be discussed only briefly
here in relation to Electrostatic Discharge (ESD) protec­tion. Likewise this application note is not addressed to
precautionary measures employed during shipping, in­stallation, or repair of equipment. Rather, the main
thrust will be limited to protection aspects called upon
during printed circuit board assembly, normal operation
of the equipment (often by operating personnel who are
untrained in preventative measures), and in service con­ditions where the transient environment may not be well
characterized.

The transient environment varies widely. There are sub­stantial differences among those experienced by, say,
automotive systems, airborne or shipborne equipment,
space systems, industrial equipment or consumer prod­ucts. All types of electronic components can be
destroyed or degraded.
nectors, printed circuit boards, etc., are susceptible,
although their threshold levels are much higher than
integrated circuits. Microwave diodes and transistors
are among the most sensitive components. However,
this application note will be restricted to standard linear
integrated circuits because of their wide usage, and to
limit the scope of coverage.

1

Even capacitors, relays, con-

Electrostatic Discharge

Electrostatic discharge is a single, fast, high current
transfer of electrostatic charge that results from:

• Direct contact transfer between two objects at differ-

ent potentials,

• A high electrostatic field between two objects when

they are in close proximity.

The prime sources of static electricity are mostly insula­tors and are typically synthetic materials, e.g., vinyl or
plastic work surfaces, insulated shoes, finished wood
chairs, Scotch tape, bubble pack, soldering irons with
ungrounded tips, etc. Voltage levels generated by these
sources can be extremely high since their charge is not
readily distributed over their surfaces or conducted to
other objects.

The generation of static electricity caused by rubbing
two substances together is called the triboelectric effect.
Examples of sources of triboelectric electrostatic charge
generation in a high RH ( ≈60%) environment include:

• Walking across a carpet ⇒ 1000 V–1500 V generated.

• Walking across a vinyl floor ⇒ 150 V–250 V generated.

• Handling material protected by clear plastic covers ⇒

400 V–600 V generated.

• Handling polyethylene bags ⇒ 1000 V–1200 V generated.

• Pouring polyurethane foam into a box ⇒ 1200 V–

1500 V generated.

or

• ICs sliding down an open antistatic shipping tube ⇒

25 V–250 V generated.

Note

: For low RH (<30%) environments, generated volt-

ages can be >10 × those listed above.

ESD Models

To evaluate the susceptibility of devices to simulated
stress environments a host of test waveforms have been
developed. The three most prominent of these wave­forms currently in general use for simulating ESD events
in semiconductor or discrete devices are: The Human
Body Model (HBM), the Machine Model (MM), and the
Charged Device Model (CDM). The test circuits and cur­rent waveform characteristics for these three models
are shown in Figures 1 to 3. Each of these models repre­sents a fundamentally different ESD event. Conse­quently, correlation between the test results for these
models is minimal.

Human Body Model:

2

Simulates the discharge event that occurs when a per­son charged to either a positive or negative potential
touches an IC at a different potential.

RLC = 1.5 kΩ, ~0 nH, 100 pF.

I

DUT

t

HVPS

10MΩ

S1

0H 1.5kΩ

100pF

Figure 1. Human Body Model

Comparison of HBM, MM, and CDM Waveforms

Figure 4 shows 400 V HBM, MM, and CDM discharge
waveforms on the same current vs. time scale. These
waveforms are of great use in predicting what failure
mechanism may result on a particular device type due to
ESD events simulated by one of these three models.

The rise time for the HBM waveform is <10 ns (typically
6 ns–9 ns), and this waveform decays exponentially to­wards 0 V with a fall time of >150 ns. MIL-STD-883
Method 3015

cation

requires a rise time of <10 ns and a delay time of

Electrostatic Discharge Sensitivity Classifi-

150 ± 20 ns (Method 3015 defines delay time as the time
for the waveform to drop from 90% of the peak current
to 36.8% of the peak current). The peak current for the
HBM waveform is ≈400 V/1500 Ω or 0.267A. Although
this peak current is much lower than that for 400 V CDM
and MM events, the relatively long duration of the total
HBM event results in a discharge of relatively high
energy.

2

AMPS

6

4

2

0

AMPS

–2

–4

20ns/DIV

20ns/DIV

HBM

MM

3

t

t

Machine Model:

Japanese model based on a worst-case HBM.

RLC = 0 Ω, 500 nH, 200 pF.

I

HVPS

10MΩ

S1

500nH 0kΩ

200pF

DUT

Figure 2. Machine Model

Charged Device Model:

Simulates the discharge that occurs when a pin on an IC
charged to either a positive or negative potential con­tacts a conductive surface at a different (usually ground)
potential.

RLC = 0 Ω, ~0 nH, 1 pF–20 pF.

I

HVPS

1GΩ

CHARGE

1Ω

DISCHARGE

DIELECTRIC

GROUND PLANE

Figure 3. Charged Device Model

2

AMPS

20ns/DIV

CDM

t

Figure 4. Relative Comparison of 400 V HBM, MM,
and CDM Discharges

t

The MM waveform consists of both positive-going and
negative-going sinusoidal peaks with peak magnitudes
that decay exponentially. The initial MM peak has a rise
time of ≈14 ns, i.e., only slightly greater than that of the
single HBM peak. The total duration of the MM wave­form is comparable to that for the HBM waveform. How­ever, the peak current for the first peak of the 400 V MM
event is ≈5.8 A, which is the highest of the three models.
The next four peaks, though decreasing in current, still
all have magnitudes of >1 A. These multiple high current
peaks of substantial duration result in an overall dis­charge energy that is by far the highest of the three
models because there is no current limiting; R = 0 Ω.

The CDM waveform corresponds to the shortest known

t

real-world ESD event. The socketed CDM waveform has
a rise time of 400 ps, with the total duration of the CDM
event of ≈2 ns. The CDM waveform is essentially unipo­lar, although some slight ringing occurs at the end of the
CDM event that results in some negative-going peaks.

–2–

With a 400 V charging voltage, a socketed CDM dis­charge will have a peak current of 2.1 A. However, the
very short duration of the overall CDM event results in
an overall discharge of relatively low energy.

Summary of ESD Models

Table I is a reference table that compares the most
important characteristics of the three ESD simulation
models.

Table I.

Model HBM MM Socketed CDM

Simulate Human Body Machine Charged Device

Origin US Military Japan 1976 AT&T 1974

Late 1960s

Real World Yes Generally No Yes

RC 1.5 kΩ, 100 pF 0 Ω, 200 pF 1 Ω , 1 pF–20 pF

Rise Time <10 ns 14 ns* 400 ps**

I

at 400 V 0.27 A 5.8 A* 2.1 A**

PEAK

Package

Dependent No No Yes

Leakage

Recovery No No Yes

• Prohibit the use of prime static generators, e.g.,

Scotch tape.

• Follow up with ESD audits at a minimum of three

month intervals.

• Training: Keep in mind, the key to an effective ESD

control program is “TRAINING.” Training should be
given to all personnel who come in contact with inte­grated circuits and should be documented for certifi­cation purposes, e.g., ISO 9000 audits.

Determining whether a device failed as a result of ESD
or Electrical Overstress (EOS) can be difficult and is of­ten best left to Failure Analysis Engineers. Typically
ESD damage is less obvious than that of EOS when elec­trical analysis and internal visual analysis are
performed. In the case of ESD, events of 1 kV or more
(depending on the ESD rating of the device) can rupture
oxides (inter layer dielectric of the die) and damage
junctions in less than 10 ns (see Figure 6). Alternately,
EOS conditions leading to 1 to 3 amps of current for a
duration of ≥1 ms can cause sufficient self-heating of
bond wires to fuse them. Such conditions can occur as a
result of latch-up. Lower currents can cause rapid melt­ing of chip metallization and other interconnect layers
(see Figure 5).

Standard MIL-STD-883 ESD Assoc. ESD Assoc. Draft

Method 3015 Standard S5.2; Standard DS5.3

EIAJ Standard
ED-4701,
Method C-111

* These values are per ESD Association Standard S5.2. EIAJs stan-

dard ED-4701 Method C-111 includes no waveform specifications.

**These values are for the direct charging (socketed) method.

Prevention

When auditing a facility in which ESD protective mea­sures will be taken, the following should be considered:

• There must be a grounded workbench on which to

handle static sensitive devices incorporating:

a) Personal ground strap (wrist strap)

b) Conductive trays or shunts, etc.

c) Conductive work surface

d) Conductive floor or mat

e) A common ground point

• All steel shelving or cabinets used to store devices

must be grounded.

• The relative humidity should be controlled; the desir-

able range is 40 to 60 percent. Where high relative
humidity levels cannot be maintained, the use of ion­ized air should be used to dissipate electrostatic
charges.

• All electrical equipment used in the area must be

grounded.

4

Figure 5. Scanning Electron Microscope View of a
Fused Metallization Site, as a Result of Electrical
Overstress

Figure 6. Scanning Electron Microscope Cross­Sectional View of a CDM ESD Site. This subsurface site
could not be viewed from the surface with an optical
microscope.

–3–