Analog Devices AN-279 Application Notes

AN-279

a

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com

Using the AD650 Voltage-to-Frequency Converter As a

Frequency-to-Voltage Converter

By Steve Martin

The AD650 is a versatile monolithic voltage-to­frequency converter (VFC) that utilizes a charge­balanced architecture to obtain high performance in
many applications. Like other charge-balanced VFCs,
the AD650 can be used in a reverse mode as a
frequency-to-voltage (F/V) converter. This application
note discusses the F/V architecture and operation,
component selection, a design example, and the
fundamental trade-off between output ripple and circuit
response time.

F/V CIRCUIT ARCHITECTURE

Figure 1 shows the major components of the frequency­to-voltage (F/V) converter. It includes a comparator, a
one-shot with a switch, a constant current source, and a
lossy integrator. When the input signal crosses the

C

INT

R

INT

V

OUT

COMP

f

IN

–0.6V

C

OS

ONE

SHOT

␣

Figure 1. Circuit Architecture

threshold at the comparator input, the comparator
triggers the one-shot. The one-shot controls a single
pole double throw switch which directs the current
source to either the summing junction, or the output, of
the lossy integrator. When the one-shot is in its “on”
state, there is current injected into the input of the
integrator and its output rises. When the one-shot
period has passed, the current is steered to the output of
the integrator. Since the output is a low impedance
node, the current has no effect on the circuit and is
effectively turned off. During this time the output falls
due to the discharge of C

through R

INT

. When constant

INT

triggering is applied to the comparator, the integration
capacitor will charge to a relatively steady value and be

REV. B

maintained by constant charging and discharging. The
charge stored on C

is unaffected by loading

INT

because of the low output impedance of the op amp.

THEORY OF OPERATION

Figure 2 shows a simplified representation of the AD650
in the F/V mode. Figure 3 represents the current i(t)
delivered to the lossy integrator. The current can be
thought of as a series of charge packets delivered at

1

f

=

OS

IN

with constant amplitude (α) and

T

)

C

INT

R

INT

V

OUT

i(t)

␣

frequency

duration (t

Figure 2. Simplified Schematic

i(t)

␣

t

OS

T

t

Figure 3. Current i(t) into Integrator

From inspection of Figure 3, the average value of input
current is found by dividing the area of the current i(t) by
the period T. The dc component of the output voltage is
found by scaling the average input current by the
feedback resistor R

V

OUTAVG

=×α.

.

INT

t

OS

R

T

INT

(1a)

Equation 1a becomes a linear function of frequency

when f

is substituted for

IN

VtRf

OUTAVG OS INT IN

=× ××α

1

.

T

(1b)

AN-279

Notice that the relationship between the average output
voltage and input frequency is a function of the one-shot
time constant and the feedback resistor but not of the
integration capacitor. This is because the integration
capacitor is an open circuit to dc. From Equation 1b it is
clear that the most practical way to trim the full-scale
voltage is to include a trim potentiometer in series with
R

. Typically, a 30% trim range will be required to

INT

absorb errors associated with t

and α.

OS

It is also important to characterize the transient
response of the integrator in order to determine settling
time of the F/V to a step change of input frequency. The
transfer function of the lossy integrator is given in the
frequency domain by:

1

VS

()

OUT

IS

()

IN

=

C

INT

S

+

RC

INT INT

1

(2)

×

which indicates that the natural or step response to a
change of input frequency is governed by an
exponential function with time constant π = R

INT

× C

INT.

With the average output voltage and transient response
known, the peak-peak output ripple can be determined
using Equation 3. Once this is determined, a design
algorithm can be developed (Reference 1).

The peak-peak ripple is given by:

//

tRC

()−()

OS OS

eee

V

=

PP

TIRC

−+ −

1

−

e

TIRC

Tt RC

1

××

α

R

(3)

where:

t

= one-shot time constant [seconds]

OS

T

= period of input frequency (1/fIN) [hertz]

R

= integration resistor [ohms]

C

= integration capacitor [farads]

α = current source value (1 mA for AD650) [amps]

Equation 3 accurately represents the ripple amplitude
for a given design. The following section shows how
this equation is used as an iterative part of the total
solution. Equation 3 can also be used to illustrate how
the ripple amplitude changes as a function of input
frequency. It is interesting to note that the ripple
amplitude changes only moderately with input
frequency and has its largest magnitude at the
minimum frequency.

DESIGN PROCEDURE

Recall from looking at Figure 3, that the one-shot “on”
time will be some fraction of the total input period. This
is the time that the circuit integrates the current signal α.
The output ripple can be minimized by allowing the
current source to be on during the majority of this
period. This is achieved by choosing the one-shot time
constant so that it occupies almost the full period of the
input signal when this period is at its minimum (or the
input frequency at its maximum). To design safely and
allow for component tolerance at f

, make t

MAX

OS

approximately equal to 90% of the minimum period.
Given t
C

OS

, the value of the one-shot timing capacitor,

OS

, is determined from Equation 1 in the AD650 data
sheet. This equation has been rearranged and appears
here as:

−

t sec

−×

C

where

(NOTE: For maximum linearity performance use a low dielectric absorp­tion capacitor for COS.)

OS

=

OS

t

OS

×

6.8 10

is in seconds and

7

3

10

3

sec F

/

C

is in farads.

OS

(4)

Once COS is known, the integration resistor is uniquely
determined from the full-scale equation (Equation 1b),
since t

, α, fIN, and V

OS

are known. This leaves only the

OUT

integration capacitor as the final unknown.

C

is chosen by first determining the response time of

INT

the device being measured. If, for example the
frequency signal to be measured is derived from a
mechanical device such as an aircraft turbine shaft, the
momentum of the shaft and the blades should be used
to determine the response time. The time constant of
the F/V is then set to match the time constant of the
mechanical system. It may be set somewhat lower,
depending on the desired total response time of the
mechanical and electrical system. Remember to allow
several time constants (N) for the F/V to approach its
final value. For the first iteration of C

use the following

INT

expression:

C

Mechanical sponse Time

=

INT

Re

×

NR

INT

(5)

where N is the number of time constants chosen to
allow adequate settling. Table I may be used to
determine the number of time constants required for
given settling accuracy.

–2–

REV. B