ANALOG DEVICES AN-1103 Service Manual
AN-1103
APPLICATION NOTE
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Layout Considerations for Digital Power Management (ADP1046)
By Subodh Madiwale
INTRODUCTION
The ADP1046 is a digital power controller. It is a secondary side
controller featuring several analog-to-digital converters (ADCs)
with different data conversion rates. It also has integrated I
communication, analog comparators, and digital compensation.
For such complicated mixed signal devices where several input
and output functions are present in a small 5 mm × 5 mm area,
layout is crucial, and proper care must be taken to avoid layout
hazards. It is better to address layout issues from the beginning
to avoid complications and failures at a later stage in the design
cycle or, much worse, in the field. This application note
provides critical layout guidelines to avoid noise coupling as
well as proper grounding techniques for the ADP1046.
2
C
MODES OF NOISE COUPLING AND HOW TO MINIMIZE THEM
Noise is predominantly a high frequency phenomenon. In the
case of a switching power supply, high frequency denotes any
frequency above 100 kHz where the higher order harmonics of
significant amplitude can be as high as 1 MHz to 10 MHz. A
low frequency noise is generally not considered detrimental to
the proper functioning of the circuit and is characterized in the
order of a few hertz (Hz), for example, the output ripple of the
boost power factor correction stage. In an electromagnetic
circuit, there are four main causes of noise injection: common
impedance coupling, capacitive coupling, inductive coupling,
and radiation.
Common Impedance Coupling
Noise from common impedance coupling is introduced when
the return trace of one loop connects to the trace of another
loop and a common path is shared for the signal. For example, if
one loop contains a high frequency (HF) signal (a noisy switching
waveform), the other is a low frequency signal (quiet VDD
signal), and both loops share the same return, noise can very
easily be injected into the low frequency (LF) path due to the
sharing of the common return. The voltage drop caused by the
HF signal on the shared impedance is also seen by the LF loop.
A star connection is the safest way to avoid this type of noise.
Capacitive Coupling
Noise from capacitive coupling is introduced when the signal
traces are routed close to each other. Whenever a trace is routed
close to another with high frequency dv/dt changes, noise is
capacitively coupled due to stray capacitances between the two
traces. This type of noise is modeled as a current source with
high input impedance and affects low impedance nodes.
Rerouting the signal traces is the only option available to reduce
noise without adding external filtering components.
Inductive Coupling
Inductive coupling can be considered the opposite of capacitive
coupling. Mutual inductance is the coupling mechanism for this
type of noise. Reducing the loop area of high di/dt traces is
crucial to reduce noise pickup.
Radiation
Noise from radiation is at very high frequencies (above 30 MHz).
The switching nodes of a power supply where high di/dt transitions occur act as antennas, radiating noise, and can affect far
fields and remote parts of the circuit. Using a six-frame Faraday
shield or reducing the antenna effect is the best option
(reducing copper area at noisy nodes).
PLACEMENT OF THE ADP1046
The ADP1046 is a secondary side controller. It must be placed
in a location that is close to the output because the majority of
the ADCs for sensing output voltage and current, as well as the
PWM outputs that control the synchronous rectifiers, are
present at the secondary side. However, the IC also provides
PWM pulses for driving power switches placed on the primary
side of the power supply. It also monitors and provides
protection for primary signals such as primary current.
Therefore, it cannot be placed too far away from the MOSFET
drivers and the primary current sense transformer.
In a power supply layout,
MOSFETs, IGBTs) and their respective gate drivers must be
close together. Placement of the ADP1046 should be done in a
manner that does not degrade the PWM outputs or the sensing/
measuring of the current and output voltages.
For prototyping and bench testing, it is highly recommended
that the user lay out the ADP1046 on a small daughter card and
connect it to the power board using external connectors (see
the PRD1274). This layout allows easy monitoring of signals
because the pins of the ADP1046 are easily accessible on the
daughter card.
the switching elements (for example,
Rev. 0 | Page 1 of 8
AN-1103 Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Modes of Noise Coupling and How to Minimize Them ............. 1
Placement of the ADP1046 ............................................................. 1
Revision History ............................................................................... 2
ADP1046 Layout and Grounding .................................................. 3
Location of PGND........................................................................ 4
VS3 and CS2 Differential Sensing .............................................. 4
VS1, VS2, VS3− Sensing .............................................................. 4
RES Pin .......................................................................................... 4
CS1 Pin........................................................................................... 4
ACSNS Pin .................................................................................... 5
PSON Pin ....................................................................................... 5
REVISION HISTORY
4/12—Revision 0: Initial Version
Power Traces (VDD and VCORE Pins) .....................................5
Decoupling Capacitors .................................................................5
OUTA to OUTD, SR1, and SR2 PWM Outputs .......................6
GATE Pin .......................................................................................6
RTD Pin ..........................................................................................6
PGOOD1, PGOOD2, and FLAGIN Pins ...................................7
SHAREo and SHAREi Pins ..........................................................7
SDA and SCL Pins (I2C Clock and Data) ...................................7
Clearance and Creepage Requirements......................................7
Conclusion .....................................................................................7
References .......................................................................................7
Rev. 0 | Page 2 of 8
Application Note AN-1103
09514-001
09514-002
09514-003
TRANSFORMER
PRIMARY
D15
2
1
D6
SMAZ16
2 1
C13 1uF
R38
5.5k
TP37
VS3+
J18
1
2
R39
5.5k
C19 1nF
C65
10uF
J20
1
2
TP38
VS3-
T7
1
2
3
4
5
6
7
8
Q11
1
23
Q10
1
2
3
16V
SR1/SR2
R38 & R39 are not populated for low-side curr ent sensi ng
R26 & R16 are not populated for high-side curr ent se nsing
25V
V+
PGND
10uH 10A
1
3
2
4
25V
J3
VOUT+
1
C23
0.1uF
J4
VOUT-
1
OUT
R35
12K
R16
4.99k
0R
1N4148
D7
2
1
R58
10K
VSS
Q15
DMN5L06K
1
23
GATE
AGND
1R
PGND
AGND
J18 & J20 for remote sensing
C12
0.1u
VS3+
VS3-
R11
500
RSHUNT
1
2
C8
1000uF
VS2
ORFET
3
1
2
R26
4.99k
CS2+
CS2-
ADP1046 LAYOUT AND GROUNDING
In mixed signal systems, the first step is to separate the analog
and digital signals to reduce interference. Noise in the digital
side can couple with the analog circuitry and severely interfere
with the signal integrity. Grounding is very important in mixed
signal systems and can be the major source of radiated noise in
systems where several multipoint grounds are present. In the
case of a power supply using the ADP1046, the system has three
grounds: the power ground (PGND), the analog ground
(AGND), and the digital ground (DGND). The proper
grounding technique for the ADP1046 is to place a ceramic
capacitor (330 nF/X7R) from VCORE to DGND. DGND must
be connected to AGND with a star connection. An AGND
plane can be created on the second layer of the PCB to prevent
noise caused by the high speed ADCs and other digital circuitry
from appearing on the analog side. A ground plane acts as a
Faraday shield and terminates the noise signal to ground.
Layout engineers who prefer to use separate DGND planes
must ensure that the AGND and DGND planes do not overlap
because the analog and digital noise can easily couple from one
ground plane to another. Instead, the AGND and DGND planes
should be connected at a single point, and the planes must be
separated by at least 3 mm to 6 mm using a 0 Ω resistor. This
layout eliminates any ground bouncing and provides the IC
with a clean ground reference.
Figure 2. Single Point Connection Between PGND and AGND Using 0 Ω
Figure 1. ADP1046 Daughter Card Layout
Figure 3. Typical PSU Secondary Side with Synchronous Rectifiers
The exposed pad of the IC must be connected to AGND.
VCORE is referenced to DGND and VDD is referenced to
AGND. All signals referenced to AGND and DGND must be
connected to their respective grounds with vias to the second
layer. Additionally, PGND and AGND must be tied together at
a single point with a 0 Ω resistor (see Figure 2).
The return point of the synchronous rectifier drivers must be
tied to VSS (see Figure 3) to minimize any inductance along
its path.
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