Analog Devices ADXL313 Datasheet

3-Axis, ±0.5 g/±1 g/±2 g/±4 g

VSV

Data Sheet

FEATURES

Ultralow power (scales automatically with data rate)

As low as 30 µA in measurement mode (V
As low as 0.1 µA in standby mode (V

Low noise performance

150 g/√Hz typical for X- and Y-axes
250 g/√Hz typical for the Z-axis

Embedded, patent pending FIFO technology minimizes host

processor load

User-selectable resolution

Fixed 10-bit resolution for any g range
Fixed 1024 LSB/g sensitivity for any g range

Resolution scales from 10-bit at ±0.5 g to 13-bit at ±4 g

Built-in motion detection functions for activity/inactivity

monitoring
Supply and I/O voltage range: 2.0 V to 3.6 V
SPI (3-wire and 4-wire) and I

2

C digital interfaces
Flexible interrupt modes mappable to two interrupt pins
Measurement range selectable via serial command
Bandwidth selectable via serial command
Wide temperature range (−40°C to +105°C)
10,000 g shock survival
Pb free/RoHS compliant
Small and thin: 5 mm × 5 mm × 1.45 mm LFCSP package
Qualified for automotive applications

APPLICATIONS

Car alarms
Hill start aid (HSA) systems
Electronic parking brakes
Data recorders (black boxes)

S

= 3.3 V)

S

= 3.3 V)

FUNCTIONAL BLOCK DIAGRAM

Digital Accelerometer

ADXL313

GENERAL DESCRIPTION

The ADXL313 is a small, thin, low power, 3-axis accelerometer
with high resolution (13-bit) measurement up to ±4 g. Digital
output data is formatted as 16-bit twos complement and is
accessible through either a serial port interface (SPI) (3-wire or
4-wire) or I

The ADXL313 is well suited for car alarm or black box
applications. It measures the static acceleration of gravity in tilt­sensing applications, as well as dynamic acceleration resulting
from motion or shock. Its high resolution (1024 LSB/g) and low
noise (150 μg/√Hz) enable resolution of inclination changes of as
little as 0.1°. A built-in FIFO facilitates using oversampling
techniques to improve resolution to as little as 0.025° of
inclination.

Several built-in sensing functions are provided. Activity and
inactivity sensing detects the presence or absence of motion
and whether the acceleration on any axis exceeds a user-set
level. These functions can be mapped to interrupt output pins.
An integrated 32-level FIFO can be used to store data to
minimize host processor intervention, resulting in reduced
system power consumption.

Low power modes enable intelligent motion-based power
management with threshold sensing and active acceleration
measurement at extremely low power dissipation.

The ADXL313 is supplied in a small, thin 5 mm × 5 mm ×

1.45 mm, 32-lead LFCSP package and is pin compatible with
the ADXL312 accelerometer device.

2

C digital interface.

DD I/O

ADXL313

SENSE

3-AXIS

SENSOR

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

ELECTRONICS

GND

ADC

DIGITAL

FILTER

32-LEVEL

FIFO

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2013–2019 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

POWER

MANAGEMENT

CONTROL

AND

INTERRUPT

LOGIC

SERIAL I/O

CS

INT1

INT2

SDA/SDI/SDIO

SDO/ALT
ADDRESS

SCL/SCLK

11469-001

ADXL313 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution .................................................................................. 4

Pin Configuration and Function Descriptions ............................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ........................................................................ 8

Power Sequencing ........................................................................ 8

Power Savings ............................................................................... 8

Serial Communications ................................................................. 10

SPI ................................................................................................. 10

I2C ................................................................................................. 13

Interrupts ..................................................................................... 15

FIFO ............................................................................................. 15

Self Test ........................................................................................ 16

Register Map ................................................................................... 17

Register Definitions ................................................................... 18

Applications Information .............................................................. 22

Power Supply Decoupling ......................................................... 22

Mechanical Considerations for Mounting .............................. 22

Threshold .................................................................................... 22

Link Mode ................................................................................... 22

Sleep Mode vs. Low Power Mode............................................. 22

Using Self Test ............................................................................. 23

3200 Hz and 1600 Hz ODR Data Formatting ........................ 24

Axes of Acceleration Sensitivity ............................................... 25

Solder Profile ................................................................................... 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 28

Automotive Products ................................................................. 28

REVISION HISTORY

2/2019—Rev. B to Rev. C

Changes to Standby Mode Leakage Current Parameter,

Table 1 ................................................................................................ 3

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 28

11/2015—Rev. A to Rev. B

Change to Register 0x02, Table 14 ................................................ 17

Changes to Register 0x02—PARTID (Read Only) Section ....... 18

Change to Preheat Time (T

Table 20 ............................................................................................ 26

11/2013—Rev. 0 to Rev. A

Changes to Figure 3, Figure 4, and Figure 5.................................. 6

4/2013—Revision 0: Initial Version

SMIN

to T

) (tS) Parameter,

SMAX

Rev. C | Page 2 of 28

Data Sheet ADXL313

Micro-Nonlinearity

Measured over any 50 mg interval

±2 %

Interaxis Alignment Error

±0.1 Degrees

Cross-Axis Sensitivity2

±1 %

NOISE PERFORMANCE

POWER SUPPLY

TEMPERATURE

Operating Temperature Range

−40 +105

°C

SPECIFICATIONS

TA = −40°C to +105°C, VS = V

Table 1.

Parameter1 Test Conditions/Comments Min Typ Max Unit

SENSOR INPUT Each axis

Measurement Range User selectable ±0.5, ±1, ±2, ±4 g
Nonlinearity Percentage of full scale ±0.5 %

OUTPUT RESOLUTION Each axis

All g Ranges Default resolution 10 Bits
±0.5 g Range Full resolution enabled 10 Bits
±1 g Range Full resolution enabled 11 Bits
±2 g Range Full resolution enabled 12 Bits
±4 g Range Full resolution enabled 13 Bits

SENSITIVITY Each axis

Sensitivity at X
±0.5 g, 10-bit or full resolution 921 1024 1126 LSB/g
±1 g, 10-bit resolution 460 512 563 LSB/g
±2 g, 10-bit resolution 230 256 282 LSB/g
±4 g, 10-bit resolution 115 128 141 LSB/g
Sensitivity Change Due to Temperature ±0.01 %/°C

0 g BIAS LEVEL Each axis

Initial 0 g Output T = 25°C, X
T = 25°C, Z
0 g Output Drift over Temperature −40°C < T < +105°C, X

−40°C < T < +105°C, Z
0 g Offset Tempco X
Z

OUT

, Y

, Z

Any g-range, full resolution mode 1024 LSB/g

OUT

OUT

= 3.3 V, a cceleration = 0 g, unless otherwise noted.

DD I/O

, Y

±50 mg

OUT

OUT

±75 mg

OUT

, Y

referenced to initial 0 g output −125 +125 mg

OUT

OUT,

, referenced to initial 0 g output −200 +200 mg

OUT

, Y

±0.5 mg/°C

OUT

OUT

±0.75 mg/°C

OUT

Noise Density X-, Y-axes 150 µg/√Hz
Z-axis 250 µg/√Hz
RMS Noise X-, Y-axes, 100 Hz output data rate (ODR) 1.5 mg rms
Z-axis, 100 Hz ODR 2.5 mg rms

OUTPUT DATA RATE/BANDWIDTH User selectable

Measurement Rate3 6.25 3200 Hz

SELF TEST4 Data rate ≥ 100 Hz, 2.0 V ≤ VS ≤ 3.6 V

Output Change in X-Axis 0.20 2.36 g
Output Change in Y-Axis −2.36 −0.20 g
Output Change in Z-Axis 0.30 3.70 g

Operating Voltage Range (VS) 2.0 3.6 V
Interface Voltage Range (V

) 1.7 VS V

DD I/O

Supply Current Data rate > 100 Hz 100 170 300 µA
Data rate < 10 Hz 30 55 110 µA
Standby Mode Leakage Current T = 25°C 0.1 2 µA
Over entire operating temperature range 10 μA
Turn-On (Wake-Up) Time5 1.4 ms

1

All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.

2

Cross-axis sensitivity is defined as coupling between any two axes.

3

Bandwidth is half the output data rate.

4

Self test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit =

0 (in the DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self test, where τ = 1/(data rate).

5

Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For

other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate).

Rev. C | Page 3 of 28

ADXL313 Data Sheet

whichever is less

Output Short-Circuit Duration

Indefinite

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Acceleration

Any Axis, Unpowered 10,000 g

Any Axis, Powered 10,000 g
VS −0.3 V to +3.9 V
V

−0.3 V to +3.9 V

DD I/O

All Other Pins −0.3 V to V

(Any Pin to Ground)
Temperature Range

Powered −40°C to +125°C

Storage −40°C to +125°C

+ 0.3 V or 3.9 V,

DD I/O

Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA θJC Unit

32-Lead LFCSP Package 27.27 30 °C/W

ESD CAUTION

Rev. C | Page 4 of 28

Data Sheet ADXL313

NOTES

1. NC = NO CONNECT. DO NOT CONNECT

TO THIS PIN.

2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE.

24

SDA/SDI/SDIO

23

SDO/A

L

T ADDRESS

22

RESERVED

21

INT2

20

INT1

19

NC

18

NC

17

NC

1
2
3
4
5
6
7
8

GND

RESERVED

GND
GND

V

S

CS

RESERVED

NC

9

10

11

12

13

14

15

16

NCNCNCNCNCNCNC

NC

32313029282726

25

NC

V

DD I/O

NCNCNCNCSCL/SCLK

NC

T

OP

VIEW

(Not to S cale)

ADXL313

11469-002

21

INT2

Interrupt 2 Output.

22

RESERVED

Reserved. This pin must be connected to GND or left open.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 GND This pin must be connected to ground.
2 RESERVED Reserved. This pin must be connected to VS or left open.
3 GND This pin must be connected to ground.
4 GND This pin must be connected to ground.
5 VS Supply Voltage.
6

CS

Chip Select.
7 RESERVED Reserved. This pin must be left open.
8 to 19 NC No Connect. Do not connect to this pin.

20 INT1 Interrupt 1 Output.

23 SDO/ALT ADDRESS Serial Data Output/Alternate I2C Address Select.
24 SDA/SDI/SDIO Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input/Output (SPI 3-Wire).
25 NC No Connect. Do not connect to this pin.
26 SCL/SCLK I2C Serial Communications Clock/SPI Serial Communications Clock.
27 to 30 NC No Connect. Do not connect to this pin.
31 V

Digital Interface Supply Voltage.

DD I/O

32 NC No Connect. Do not connect to this pin.
EP Exposed Pad. The exposed pad must be soldered to the ground plane.

Rev. C | Page 5 of 28

ADXL313 Data Sheet

–125

–100

–75

–50

–25

0

25

50

75

100

125

10

30 50

70 90 110

ACCELERATION (mg)

TEMPERA

TURE (°C)

11469-003

–50 –30

–10

–125

–100

–75

–50

–25

0

25

50

75

100

125

–50 –30 –10 10 30 50 70 90 110

ACCELERATION (mg)

TEMPERATURE (°C)

11469-004

–200

–150

–100

–50

0

50

100

150

200

10 30 50

70 90 110

ACCELERATION (mg)

TEMPERA

TURE (°C)

11469-005

–50 –30 –10

–1.0

–0.5

0

0.5

1.0

–40

–30

–20

–10

0

10

20

30

40

0

500

1000

1500

2000

NONLINEARIT

Y

(%FS)

NONLINEARITY (mg

)

INPUT

ACCELER

A

TION (m

g

)

11469-006

–2000 –1500

–1000

–500

–1.0

–0.5

0

0.5

1.0

–40

–30

–20

–10

0

10

20

30

40

–2000 –1500

–1000 –500

0

500

1000 1500

2000

NONLINEARITY

(%FS)

NONLINEARITY (m

g)

INPUT

ACCELERA

TION (m

g)

1

1469-007

–1.0

–0.5

0

0.5

1.0

–40

–30

–20

–10

0

10

20

30

40

0 500 1000 1500

2000

NONLINEARIT

Y (%FS)

NONLINEARITY

(mg)

INPUT ACCELERATION (mg

)

1

1469-008

–2000 –1500

–1000

–500

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. X-Axis Acceleration vs. Temperature, Three Lots (N = 80)

Figure 4. Y-Axis Acceleration vs. Temperature, Three Lots (N = 80)

Figure 6. X-Axis Nonlinearity, ±2 g Input Range

Figure 7. Y-Axis Nonlinearity, ±2 g Input Range

Figure 5. Z-Axis Acceleration vs. Temperature, Three Lots (N = 80)

Figure 8. Z-Axis Nonlinearity, ±2 g Input Range

Rev. C | Page 6 of 28

Data Sheet ADXL313

–5

–4

–3

–2

–1

0

1

2

3

4

5

–1000 –750 –500 –250 0 250 500 750 1000

MICROLINEARITY (%)

INPUT ACCELERATION (mg)

11469-009

–5

–4

–3

–2

–1

0

1

2

3

4

5

–1000 –750 –500

–250 0 250 500 750

1000

MICROLINEARITY (%)

INPUT ACCELERATION (mg)

11469-010

–5

–4

–3

–2

–1

0

1

2

3

4

5

–1000 –750 –500 –250 0 250 500 750 1000

MICROLINEARITY (%)

INPUT ACCELERATION (mg)

11469-011

0

10

20

40

30

50

80

70

60

305070

90110

130

150

170

190

210

230

250

270

290

310

CURRENT (nA)

PERCENT OF POPUL

ATION (%)

1

1469-1

18

0

5

10

20

15

25

35

30

100

120

140

160

180

200

220

240

260

280

300

CURRENT CONSUMP TION (µA)

PERCENT OF POPULATION (%)

11469-119

0

50

100

150

200

2.0 2.4 2.8 3.2 3.6

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

11469-233

Figure 9. X-Axis Microlinearity, 50 mg Step Size

Figure 12. Standby Mode Current Consumption, VS = V

= 3.3 V, 25°C

DD I/O

Figure 10. Y-Axis Microlinearity, 50 mg Step Size

Figure 11. Z-Axis Microlinearity, 50 mg Step Size

Figure 13. Current Consumption, Measurement Mode, Data Rate = 100 Hz,

V

= V

= 3.3 V, 25°C

S

DD I/O

Figure 14. Supply Current vs. Supply Voltage, V

at 25°C

S

Rev. C | Page 7 of 28

ADXL313 Data Sheet

Bandwidth (Hz)

Rate Code

IDD (µA)

on the communication bus. Minimize the duration of this state during power-up to prevent a conflict.

THEORY OF OPERATION

The ADXL313 is a complete 3-axis acceleration measurement
system with a selectable measurement range of ±0.5 g, ±1 g,
±2 g, or ±4 g. It measures both dynamic acceleration resulting
from motion or shock and static acceleration, such as gravity,
which allows it to be used as a tilt sensor.

The sensor is a polysilicon surface-micromachined structure
built on top of a silicon wafer. Polysilicon springs suspend the
structure over the surface of the wafer and provide a resistance
against acceleration forces.

Deflection of the structure is measured using differential
capacitors that consist of independent fixed plates and plates
attached to the moving mass. Acceleration deflects the beam
and unbalances the differential capacitor, resulting in a sensor
output whose amplitude is proportional to acceleration. Phase­sensitive demodulation is used to determine the magnitude and
polarity of the acceleration.

POWER SEQUENCING

Power can be applied to VS or V
damaging the ADXL313. All possible power-on modes are
summarized in Table 5. The interface voltage level is set with
the interface supply voltage, V
ensure that the ADXL313 does not create a conflict on the
communication bus. For single-supply operation, V
the same as the main supply, V
however, V

can differ from VS to accommodate the desired

DD I/O

interface voltage, as long as V
After V

is applied, the device enters standby mode, where power

S

consumption is minimized and the device waits for V
applied and for the command to enter measurement mode to be
received. (This command can be initiated by setting the measure
bit in the POWER_CTL register (Address 0x2D).) In addition, any
register can be written to or read from to configure the part while
the device is in standby mode. It is recommended that the device
be configured in standby mode before measurement mode is
enabled. Clearing the measure bit returns the device to the standby
mode.

in any sequence without

DD I/O

, which must be present to

DD I/O

DD I/O

. In a dual-supply application,

S

is greater than or equal to V

S

DD I/O

can be

.

DD I/O

to be

POWER SAVINGS

Power Modes

The ADXL313 automatically modulates its power consumption
in proportion to its output data rate, as outlined in Table 5. If
additional power savings are desired, a lower power mode is
available. In this mode, the internal sampling rate is reduced,
allowing for power savings in the 12.5 Hz to 400 Hz data rate
range at the expense of slightly greater noise. To enter low
power mode, set the LOW_POWER bit (Bit 4) in the BW_RATE
register (Address 0x2C). The current consumption in low power
mode is shown in Table 6 for cases where there is an advantage
to using low power mode. Use of low power mode for a data
rate not shown in Table 6 does not provide any advantage over
the same data rate in normal power mode. Therefore, it is
recommended that only data rates shown in Table 6 be used in
low power mode. The current consumption values shown in
Table 5 and Table 6 are for a V

Table 5. Current Consumption vs. Data Rate
(T

= 25°C, VS = V

A

Output Data
Rate (Hz)

3200 1600 1111 170
1600 800 1110 115
800 400 1101 170
400 200 1100 170
200 100 1011 170
100 50 1010 170
50 25 1001 115
25 12.5 1000 82

12.5 6.25 0111 65

6.25 3.125 0110 57

DD I/O

Bandwidth (Hz) Rate Code IDD (µA)

Table 6. Current Consumption vs. Data Rate, Low Power Mode
(T

= 25°C, VS = V

A

Output Data
Rate (Hz)

400 200 1100 115
200 100 1011 82
100 50 1010 65
50 25 1001 57
25 12.5 1000 50

12.5 6.25 0111 43

DD I/O

of 3.3 V.

S

= 3.3 V)

= 3.3 V)

Table 7. Power Sequencing

Condition VS V

Power Off Off Off The device is completely off, but there is a potential for a communication bus conflict.
Bus Disabled On Off The device is on in standby mode, but communication is unavailable, and the device creates a conflict

Bus Enabled Off On No functions are available, but the device does not create a conflict on the communication bus.
Standby or

Measurement

On On The device is in standby mode, awaiting a command to enter measurement mode, and all sensor

Description

DD I/O

functions are off. After the device is instructed to enter measurement mode, all sensor functions are
available.

Rev. C | Page 8 of 28

Data Sheet ADXL313

Autosleep Mode

Additional power savings can be obtained by having the

ADXL313 automatically switch to sleep mode during periods of

inactivity. To enable this feature, set the THRESH_INACT
register (Address 0x25) to an acceleration threshold value.
Levels of acceleration below this threshold are regarded as no
activity. Set TIME_INACT (Address 0x26) to an appropriate
inactivity time period. Then set the AUTO_SLEEP bit and the
link bit in the POWER_CTL register (Address 0x2D). If the
device does not detect a level of acceleration in excess of
THRESH_INACT for TIME_INACT seconds, the device is
transitioned to sleep mode automatically. Current consumption
at less than 10 Hz data rates used in this mode is typically 55 µA
for a V

of 3.3 V.

S

Standby Mode

For even lower power operation, standby mode can be used.
In standby mode, current consumption is reduced to 0.1 µA
(typical). In this mode, no measurements are made. Standby
mode is entered by clearing the measure bit (Bit 3) in the
POWER_CTL register (Address 0x2D). Placing the device into
standby mode preserves the contents of the FIFO.

Rev. C | Page 9 of 28

ADXL313 Data Sheet

SERIAL COMMUNICATIONS

I2C and SPI digital communications are available. In both cases,
the ADXL313 operates as a slave. I
is tied high to V
V

or be driven by an external controller because there is no

DD I/O

default mode if the

. The CS pin must always be tied high to

DD I/O

CS

pin is left unconnected. Therefore, not

2

C mode is enabled if the CS pin

taking these precautions may result in an inability to communicate
with the part. In SPI mode, the
master. In both SPI and I

CS

2

C modes of operation, ignore data

pin is controlled by the bus

transmitted from the ADXL313 to the master device during
writes to the ADXL313.

SPI

For SPI communication, either 3- or 4-wire configuration is
possible, as shown in the connection diagrams in Figure 15 and
Figure 16. Clearing the SPI bit in the DATA_FORMAT register
(Address 0x31) selects 4-wire mode, whereas setting the SPI bit
selects 3-wire mode. The maximum SPI clock speed is 5 MHz
with 100 pF maximum loading, and the timing scheme follows
clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. If power
is applied to the ADXL313 before the clock polarity and phase
of the host processor are configured, the
high before changing the clock polarity and phase. When using
the 3-wire SPI configuration, it is recommended that the SDO
pin be either pulled up to V

DD I/O

10 kΩ resistor.

ADXL313

CS

SDIO

SDO

SCLK

Figure 15. 3-Wire SPI Connection Diagram

ADXL313

CS

SDI

SDIO

SCLK

Figure 16. 4-Wire SPI Connection Diagram

CS

pin must be brought

or pulled down to GND via a

PROCESSOR

D OUT

D IN/OUT

D OUT

PROCESSOR

D OUT

D OUT

D IN

D OUT

11469-012

11469-013

CS

is the serial port enable line and is controlled by the SPI master.
This line must go low at the start of a transmission and high at
the end of a transmission, as shown in Figure 17 to Figure 19.
SCLK is the serial port clock and is supplied by the SPI master.
SCLK idles high during a period of no transmission. SDI and
SDO are the serial data input and output, respectively. Data is
updated on the falling edge of SCLK and sampled on the rising
edge of SCLK.

To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/

W

bit in the first byte transfer
(MB in Figure 17 to Figure 19), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the ADXL313 to point
to the next register for a read or write. This shifting continues
until the clock pulses cease and
or writes on different, nonsequential registers,

CS

is deasserted. To perform reads

CS

must be
deasserted between transmissions, and the new register must be
addressed separately.

The timing diagram for 3-wire SPI reads or writes is shown in
Figure 17. The 4-wire equivalents for SPI reads and writes are
shown in Figure 18 and Figure 19, respectively. For correct
operation of the part, the logic thresholds and timing parameters
in Table 8 and Table 9 must be met at all times.

Use of the 3200 Hz and 1600 Hz output data rates is recommended
only with SPI communication rates greater than or equal to
2 MHz. The 800 Hz output data rate is recommended only for
communication speeds greater than or equal to 400 kHz, and
the remaining data rates scale proportionally. For example, the
minimum recommended communication speed for a 200 Hz
output data rate is 100 kHz. Operation at an output data rate
below the recommended minimum may result in undesirable
effects on the acceleration data, including missing samples or
additional noise.

Rev. C | Page 10 of 28

Data Sheet ADXL313

Limit

2, 3

Parameter

Min

Max

Unit

Description

t

5 ns

SDI valid after SCLK rising edge.

Table 8. SPI Digital Input/Output

Limit1
Parameter Test Conditions/Comments Min Max Unit

Digital Input

Low Level Input Voltage (VIL) 0.3 × V
High Level Input Voltage (VIH) 0.7 × V
Low Level Input Current (IIL) VIN = V

0.1 µA

DD I/O

V

DD I/O

High Level Input Current (IIH) VIN = 0 V −0.1 µA

Digital Output

Low Level Output Voltage (VOL) IOL = 10 mA 0.2 × V
High Level Output Voltage (VOH) IOH = −4 mA 0.8 × V
Low Level Output Current (IOL) VOL = V
High Level Output Current (IOH) VOH = V

10 mA

OL, max

−4 mA

OH, min

V

DD I/O

Pin Capacitance fIN = 1 MHz, VIN = 2.5 V 8 pF

1

Limits based on characterization results; not production tested.

V

DD I/O

V

DD I/O

Table 9. SPI Timing (TA = 25°C, VS = V

f

5 MHz SPI clock frequency.

SCLK

t

200 ns 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40.

SCLK

t

5 ns

DELAY

t

5 ns

QUIET

t

10 ns

DIS

t

150 ns

,DIS

CS

tS 0.3 × t
tM 0.3 × t
t

5 ns SDI valid before SCLK rising edge.

SETUP

HOLD

t

40 ns SCLK falling edge to SDO/SDIO output transition.

SDO

4

t

20 ns SDO/SDIO output high to output low transition.

R

4

t

20 ns SDO/SDIO output low to output high transition.

F

1

The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.

2

Limits based on characterization results, characterized with f

3

The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 8.

4

Output rise and fall times measured with capacitive load of 150 pF.

ns SCLK low pulse width (space).

SCLK

ns SCLK high pulse width (mark).

SCLK

DD I/O

= 3.3 V)1

falling edge to SCLK falling edge.

CS
SCLK rising edge to

rising edge to SDO disabled.

CS

deassertion between SPI communications.

CS

= 5 MHz and bus load capacitance of 100 pF; not production tested.

SCLK

rising edge.

CS

Rev. C | Page 11 of 28

ADXL313 Data Sheet

S

CS

SCLK

t

DELAY

t

SCLK

t

t

M

S

t

QUIET

t

CS,DIS

t

SETUP

SDIO

SDO

NOTES

t

IS ONLY PRESENT DURING READS.

1.

SDO

CS

t

DELAY

SCLK

t

SETUP

SDI

SDO

t

HOLD

R/W MB A5 A0 D7 D0

ADDRESS BITS DATA BIT S

t

,

t

R

F

t

SDO

Figure 17. SPI 3-Wire Read/Write

t

SCLK

t

HOLD

RMBA5

t

SDO

XXX

ADDRESS BITS

t

t

M

S

A0

t

,

t

R

F

X

D7

DATA BIT S

t

QUIET

X

t

DIS

Figure 18. SPI 4-Wire Read

11469-014

t

CS,DIS

D0X

11469-015

CS

t

MtS

XX X

t

,

t

R

F

t

QUIET

t

CS,DIS

t

DIS

11469-016

CLK

SDI

SDO

t

SETUP

t

t

DELAY

W

XXX

SCLK

t

HOLD

MB A5 A0 D7 D0

t

SDO

ADDRESS BITS DATA BITS

Figure 19. SPI 4-Wire Write

Rev. C | Page 12 of 28

Data Sheet ADXL313

PROCESSOR

D IN/OUT

D OUT

R

P

V

DD I/O

R

P

ADXL313

CS

SDA

ALT ADDRESS

SCL

11469-017

Parameter

Test Conditions/Comments

Min

Max

Unit

Pin Capacitance

fIN = 1 MHz, VIN = 2.5 V

8 pF

NOTES

1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.

2. THE SHADED AREAS RE P RE S E NT WHEN THE DE V ICE IS LISTENING .

11469-133

MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS
SLAVE ACK ACK ACK

MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS
SLAVE ACK ACK

ACK ACK

MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS

STOP

SLAVE ACK ACK

MASTER START

START

1

START

1

SLAVE ADDRESS + WRITE REGISTER ADDRESS NACK ST OP

SLAVE ACK ACK

DATA

STOP

ACK

SINGLE-BYTE W RI TE

MULTIPLE-BYTE WRITE

DATA

DATA

MULTIPLE-BYTE READ

SLAVE ADDRESS + READ

SLAVE ADDRESS + READ

ACK

DATA

DATA

DATA

STOP

NACK

ACK

SINGLE-BYTE READ

I2C

With CS tied high to V
requiring a simple 2-wire connection, as shown in Figure 20.
The ADXL313 conforms to the UM10204 I
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the bus parameters given in Table 10 and
Table 11 are met. Single- or multiple-byte reads/writes are
supported, as shown in Figure 21. With the ALT ADDRESS pin
high, the 7-bit I

W

bit. This translates to 0x3A for a write and 0x3B for a read. An

R/
alternate I

2

C address for the device is 0x1D, followed by the

2

C address of 0x53 (followed by the R/W bit) can be
chosen by grounding the ALT ADDRESS pin (Pin 23). This
translates to 0xA6 for a write and 0xA7 for a read.

Table 10. I

2

C Digital Input/Output

Limit1

Digital Input

Low Level Input Voltage (VIL) 0.3 × V
High Level Input Voltage (VIH) 0.7 × V
Low Level Input Current (IIL) VIN = V
High Level Input Current (IIH) VIN = 0 V −0.1 µA

Digital Output

Low Level Output Voltage (VOL) V
V
Low Level Output Current (IOL) VOL = V

, the ADXL313 is in I2C mode,

DD I/O

2

C-Bus Specification

2

Figure 20. I

C Connection Diagram (Address 0x53)

If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed V
by more than 0.3 V. External pull-up resistors, R
for proper I
the UM10204 I

2

C operation. To ensure proper operation, refer to

2

C-Bus Specification and User Manual, Rev. 03—

, are necessary

P

19 June 2007, when selecting pull-up resistor values.

V

DD I/O

V

DD I/O

0.1 µA

DD I/O

< 2 V, IOL = 3 mA 0.2 × V

DD I/O

≥ 2 V, IOL = 3 mA 400 mV

DD I/O

3 mA

OL, max

V

DD I/O

DD I/O

1

Limits based on characterization results; not production tested.

2

Figure 21. I

C Device Addressing

Rev. C | Page 13 of 28

ADXL313 Data Sheet

t9

1.3 µs

Bus-free time between a stop condition and a start condition

t10 300

ns

Rise time of both SCL and SDA when receiving

SDA

t

9

SCL

t

3

t

10

t

1

1

t

4

t

4

t

6

t

2

t

5

t

7

t

1

t

8

S

TART

CONDITION

REPEATED

ST

ART

CONDITION

S

TOP

CONDITION

11469-018

Table 11. I2C Timing (TA = 25°C, VS = V

Limit
Parameter Min Max Unit Description

f

400 kHz SCL clock frequency

SCL

t1 2.5 µs SCL cycle time
t2 0.6 µs SCL high time
t3 1.3 µs SCL low time
t4 0.6 µs Start/repeated start condition hold time
t5 100 ns Data setup time

3, 4, 5, 6

t

0 0.9 µs Data hold time

6

t7 0.6 µs Setup time for repeated start
t8 0.6 µs Stop condition setup time

0 ns Rise time of both SCL and SDA when receiving or transmitting
t11 250 ns Fall time of SDA when receiving
300 ns Fall time of both SCL and SDA when transmitting
20 + 0.1 C

7

ns Fall time of both SCL and SDA when transmitting or receiving

b

Cb 400 pF Capacitive load for each bus line

1

Limits based on characterization results, with f

2

All values referred to the VIH and the VIL levels given in Table 10.

3

t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.

4

A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to V

region of the falling edge of SCL.

5

The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.

6

The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t

t

= t3 − t10 − t

6(max )

7

C

is the total capacitance of one bus line in picofarads.

b

5(min)

.

= 3.3 V)

DD I/O

1, 2

= 400 kHz and a 3 mA sink current; not production tested.

SCL

of the SCL signal) to bridge the undefined

IH, min

). This value is calculated as

5(min)

Figure 22. I

Rev. C | Page 14 of 28

2

C Timing Diagram

Data Sheet ADXL313

INTERRUPTS

The ADXL313 provides two output pins for driving interrupts:
INT1 and INT2. Both interrupt pins are push-pull, low impedance
pins with output specifications shown in Tabl e 12. The default
configuration of the interrupt pins is active high. This can be
changed to active low by setting the INT_INVERT bit in the
DATA_FORMAT register (Address 0x31). All functions can be
used simultaneously, with the only limiting feature being that
some functions may need to share interrupt pins.

Interrupts are enabled by setting the appropriate bit in the
INT_ENABLE register (Address 0x2E) and are mapped to either
the INT1 or INT2 pin based on the contents of the INT_MAP
register (Address 0x2F). When initially configuring the interrupt
pins, it is recommended that the functions and interrupt mapping
be completed before enabling the interrupts. When changing the
configuration of an interrupt, it is recommended that the interrupt
be disabled first, by clearing the bit corresponding to that function
in the INT_ENABLE register, and then the function be reconfig­ured before enabling the interrupt again. Configuration of the
functions while the interrupts are disabled helps to prevent the
accidental generation of an interrupt.

The interrupt functions are latched and cleared either by reading
the data registers (Address 0x32 to Address 0x37) until the inter­rupt condition is no longer valid for the data-related interrupts
or by reading the INT_SOURCE register (Address 0x30) for the
remaining interrupts. The following sections describe the
interrupts that can be set in the INT_ENABLE register and
monitored in the INT_SOURCE register.

DATA_READY

The DATA_READY bit is set when new data is available and is
cleared when no new data is available.

Table 12. Interrupt Pin Digital Output

Limit1
Parameter Test Conditions/Comments Min Max Unit

Digital Output

Low Level Output Voltage (VOL) IOL = 300 µA 0.2 × V
High Level Output Voltage (VOH) IOH = −150 µA 0.8 × V
Low Level Output Current (IOL) VOL = V

High Level Output Current (IOH) VOH = V
Pin Capacitance fIN = 1 MHz, VIN = 2.5 V 8 pF
Rise/Fall Time

Rise Time (tR)2 C

Fall Time (tF)3 C

1

Limits based on characterization results, not production tested.

2

Rise time is measured as the transition time from V

3

Fall time is measured as the transition time from V

LOAD

LOAD

OL, m ax

OH, min

300 µA

OL, max

OH, min

= 150 pF 210 ns
= 150 pF

to V

to V

of the INTx pin.

OH, min

of the INTx pin.

OL, m ax

Activity

The activity bit is set when acceleration greater than the value
stored in the THRESH_ACT register (Address 0x24) is sensed.

Inactivity

The inactivity bit is set when acceleration of less than the value
stored in the THRESH_INACT register (Address 0x25) is sensed
for more time than is specified in the TIME_INACT register
(Address 0x26). The maximum value for TIME_INACT is 255 sec.

Watermark

The watermark bit is set when the number of samples in
the FIFO equals the value stored in the samples bits in the
FIFO_CTL register (Address 0x38). The watermark bit is
cleared automatically when the FIFO is read, and the content
returns to a value below the value stored in the samples bits.

Overrun

The overrun bit is set when new data replaces unread data. The
precise operation of the overrun function depends on the FIFO
mode. In bypass mode, the overrun bit is set when new data
replaces unread data in the DATA_Xx, DATA_Yx, and DATA_Zx
registers (Address 0x32 to Address 0x37). In all other modes, the
overrun bit is set when the FIFO is filled. The overrun bit is
automatically cleared when the contents of FIFO are read.

FIFO

The ADXL313 contains patent pending technology for an
embedded memory management system with a 32-level FIFO
that can be used to minimize host processor burden. This buffer
has four modes: bypass, FIFO, stream, and trigger (see Tabl e 17).
Each mode is selected by the settings of the FIFO_MODE bits
in the FIFO_CTL register (Address 0x38).

Bypass Mode

In bypass mode, the FIFO is not operational and, therefore,
remains empt y.

V

DD I/O

V

DD I/O

−150 µA

150 ns

Rev. C | Page 15 of 28

ADXL313 Data Sheet

FIFO Mode

In FIFO mode, data from measurements of the x-, y-, and z-axes
are stored in the FIFO. When the number of samples in the FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. The
FIFO continues accumulating samples until it is full (32 samples
from measurements of the x-, y-, and z-axes) and then stops
collecting data. After the FIFO stops collecting data, the device
continues to operate; therefore, features such as activity detection
can be used after the FIFO is full. The watermark interrupt contin­ues to occur until the number of samples in the FIFO is less
than the value stored in the samples bits of the FIFO_CTL
register.

Stream Mode

In stream mode, data from measurements of the x-, y-, and z­axes is stored in FIFO. When the number of samples in the FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. FIFO
continues accumulating samples and holds the latest 32 samples
from measurements of the x-, y-, and z-axes, discarding older
data as new data arrives. The watermark interrupt continues
occurring until the number of samples in FIFO is less than the
value stored in the samples bits of the FIFO_CTL register.

Trigger Mode

In trigger mode, the FIFO accumulates samples, holding the
latest 32 samples from measurements of the x-, y-, and z-axes.
After a trigger event occurs and an interrupt is sent to the INT1
or INT2 pin (determined by the trigger bit in the FIFO_CTL
register), FIFO keeps the last n samples (where n is the value
specified by the samples bits in the FIFO_CTL register) and
then operates in FIFO mode, collecting new samples only when
the FIFO is not full. A delay of at least 5 μs must be present between
the trigger event occurring and the start of reading data from
the FIFO to allow the FIFO to discard and retain the necessary
samples. Additional trigger events cannot be recognized until
the trigger mode is reset. To reset the trigger mode, set the device
to bypass mode and then set the device back to trigger mode. Note
that the FIFO data must be read first because placing the device
into bypass mode clears FIFO.

Retrieving Data from FIFO

The FIFO data is read through the DATA_Xx, DATA _Yx, and
DATA_Zx registers (Address 0x32 to Address 0x37). When the
FIFO is in FIFO, stream, or trigger mode, reads to the DATA_Xx,
DATA_xY, an d DATA_Zx registers read data stored in the
FIFO. Each time data is read from the FIFO, the oldest x-, y-,

and z-axes data is placed into the DATA_Xx, DATA_Yx, and
DATA_Zx registers.

If a single-byte read operation is performed, the remaining
bytes of data for the current FIFO sample are lost. Therefore, all
axes of interest must be read in a burst (or multiple-byte) read
operation. To ensure that the FIFO has completely popped (that
is, that new data has completely moved into the DATA_Xx,
DATA_Yx, and DATA_Zx registers), there must be at least 5 μs
between the end of reading the data registers and the start of a
new read of the FIFO or a read of the FIFO_STATUS register
(Address 0x39). The end of reading a data register is signified by
the transition from Register 0x37 to Register 0x38 or by the

CS

pin

going high.
For SPI operation at 1.6 MHz or less, the register addressing

portion of the transmission is a sufficient delay to ensure that
the FIFO has completely popped. For SPI operation greater than

1.6 MHz, it is necessary to deassert the

CS

pin to ensure a total
delay of 5 μs; otherwise, the delay is not sufficient. The total delay
necessary for 5 MHz operation is at most 3.4 μs. This is not a
concern when using I

2

C mode because the communication rate is

low enough to ensure a sufficient delay between FIFO reads.

SELF TEST

The ADXL313 incorporates a self test feature that effectively
tests its mechanical and electronic systems simultaneously.
When the self test function is enabled (via the SELF_TEST bit
in the DATA_FORMAT register, Address 0x31), an electrostatic
force is exerted on the mechanical sensor. This electrostatic force
moves the mechanical sensing element in the same manner as
acceleration, and it is additive to the acceleration experienced
by the device. This added electrostatic force results in an output
change in the x-, y-, and z-axes. Because the electrostatic force
is proportional to V
test feature of the ADXL313 also exhibits a bimodal behavior.
However, the limits shown in Tabl e 1 and Table 13 are valid for
all potential self test values across the entire allowable voltage
range. Use of the self test feature at data rates of less than 100 Hz or
at 1600 Hz may yield values outside these limits. Therefore, the
part must be in normal power operation (LOW_POWER bit = 0
in the BW_RATE register, Address 0x2C) and be placed into a
data rate of 100 Hz through 800 Hz or 3200 Hz for the self test
function to operate correctly.

Table 13. Self Test Output (T

Axis Min (g) Max (g)

X 0.20 2.36
Y −2.36 +0.20
Z 0.30 3.70

2

, the output change varies with VS. The self

S

= 25°C, 2.0 V ≤ VS ≤ 3.6 V)

A

Rev. C | Page 16 of 28

Data Sheet ADXL313

0x02

PARTID

R

PARTID[7:0]

0xCB

0x23

0x34

DATA_Y0

R

DATA_Y0[7:0]

0x00

REGISTER MAP

Table 14. Register Map

Reg. Name Type D7 D6 D5 D4 D3 D2 D1 D0

0x00 DEVID_0 R DEVID_0[7:0] 0xAD
0x01 DEVID_1 R DEVID_1[7:0] 0x1D

0x03 REVID R REVID[7:0] 0x00
0x04 XID R XID[7:0] 0x00
0x05 to

0x17
0x18 SOFT_RESET
0x19 to

0x1D
0x1E OFSX

0x1F OFSY
0x20 OFSZ
0x21 to

Reserved RSVD Reserved

W

R/

Reserved RSVD Reserved

W

R/

W

R/

W

R/

Reserved RSVD Reserved

SOFT_RESET[7:0] 0x00

OFSX[7:0] 0x00
OFSY[7:0] 0x00
OFSZ[7:0] 0x00

Reset
Value

0x24 THRESH_ACT
0x25 THRESH_INACT
0x26 TIME_INACT
0x27 ACT_INACT_CTL

0x28 to
0x2B

0x2C BW_RATE
0x2D POWER_CTL

0x2E INT_ENABLE

0x2F INT_MAP

0x30 INT_SOURCE R DATA_

0x31 DATA_FORMAT

0x32 DATA_X0 R DATA_X0[7:0] 0x00
0x33 DATA_X1 R DATA_X1[7:0] 0x00

0x35 DATA_Y1 R DATA_Y1[7:0] 0x00
0x36 DATA_Z0 R DATA_Z0[7:0] 0x00
0x37 DATA_Z1 R DATA_Z1[7:0] 0x00
0x38 FIFO_CTL
0x39 FIFO_STATUS R FIFO_TRIG 0 Entries 0x00

Reserved RSVD Reserved

W

R/

W

R/

W

R/

ACT_

W

R/

AC/DC

0 0 0 LOW_POWER Rate[3:0] 0x0A

W

R/

0 I2C_

W

R/

DATA_

W

R/

READY
DATA_

W

R/

READY

READY
SELF_

W

R/

TEST

W

R/

FIFO_MODE[1:0] Trigger Samples[4:0] 0x00

ACT_X ACT_Y ACT_Z INACT_

DISABLE
0 0 Activity Inactivity 0 Watermark Overrun 0x00

0 0 Activity Inactivity 0 Watermark Overrun 0x00

0 0 Activity Inactivity 0 Watermark Overrun 0x02

SPI

Link AUTO_SLEEP Measure Sleep Wake-up[1:0] 0x00

INT_
INVERT

THRESH_ACT[7:0] 0x00

THRESH_INACT[7:0] 0x00

TIME_INACT[7:0] 0x00

INACT_X INACT_Y INACT_Z 0x00

AC/DC

0 FULL_RES Justify Range[1:0] 0x00

Rev. C | Page 17 of 28

ADXL313 Data Sheet

D7

D6

D5

D4

D3

D2

D1

D0

ACT_AC/DC

ACT_X

ACT_Y

ACT_Z

REGISTER DEFINITIONS

Register 0x00—DEVID_0 (Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 0 1 1 0 1

The DEVID_0 register holds a fixed device ID identifying
Analog Devices, Inc., as the device manufacturer. The default
value of this register is 0xAD.

Register 0x01—DEVID_1 (Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 1 1 0 1

The DEVID_1 register holds a fixed device ID that further
enhances traceability of the ADXL313. The default value of this
register is 0x1D.

Register 0x02—PARTID (Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0 1 0 1 1

The PARTID register identifies the device as an ADXL313. The
default hexadecimal value stored in this register, 0xCB, is meant
to be interpreted as an octal value that corresponds to 313. If
the user does not read back 0xCB from this register, assume that
the device under test is not an ADXL313 device.

Register 0x03—REVID (Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

REVID[7:0]

The number contained in the REVID register represents the
silicon revision of the ADXL313. This number is incremented
for any major silicon revision.

Register 0x04—XID (Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

XID[7:0]

The XID register stores a semiunique serial number that is
generated from the device trim and calibration process.

Register 0x18—SOFT_RESET (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

SOFT_RESET[7:0]

Writing a value of 0x52 to Register 0x18 triggers the soft reset
function of the ADXL313. The soft reset returns the ADXL313
to the beginning of its power-on initialization routine, clearing
the configuration settings that were written to the memory
map, which allows easy reconfiguration of the ADXL313 device.

Register 0x1E—OFSX (Read/Write), Register 0x1F—OFSY (Read/Write), Register 0x20—OFSZ (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

OFSX[7:0]
OFSY[7:0]
OFSZ[7:0]

The OFSX, OFSY, and OFSZ registers are each eight bits and
offer user set offset adjustments in twos complement format,
with a scale factor of 3.9 mg/LSB (that is, 0x7F = 0.5 g). The
value stored in the offset registers is automatically added to the
acceleration data, and the resulting value is stored in the output
data registers.

Register 0x24—THRESH_ACT (Read/Write)

THRESH_ACT[7:0]

The THRESH_ACT register is eight bits and holds the threshold
value for detecting activity. The data format is unsigned;
therefore, the magnitude of the activity event is compared with
the value in the THRESH_ACT register. The scale factor is

15.625 mg/LSB. A value of 0 may result in undesirable behavior
if the activity interrupt is enabled.

Register 0x25—THRESH_INACT (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

THRESH_INACT[7:0]

The THRESH_INACT register is eight bits and holds the threshold
value for detecting inactivity. The data format is unsigned;
therefore, the magnitude of the inactivity event is compared
with the value in the THRESH_INACT register. The scale factor is

15.625 mg/LSB. A value of 0 may result in undesirable behavior
if the inactivity interrupt is enabled.

Register 0x26—TIME_INACT (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

TIME_INACT[7:0]

The TIME_INACT register is eight bits and contains an unsigned
time value. Acceleration must be less than the value in the
THRESH_INACT register for the amount of time represented by
TIME_INACT for inactivity to be declared. The scale factor is
1 sec/LSB. Unlike the other interrupt functions, which use
unfiltered data (see the Threshold section), the inactivity
function uses filtered output data. At least one output sample
must be generated for the inactivity interrupt to be triggered.
This results in the function appearing unresponsive if the
TIME_INACT register is set to a value less than the time
constant of the output data rate. A value of 0 results in an
interrupt when the output data is less than the value in the
THRESH_INACT register.

Register 0x27—ACT_INACT_CTL (Read/Write)

D7 D6 D5 D4

D3 D2 D1 D0

INACT_AC/DC INACT_X INACT_Y INACT_Z

ACT_AC/DC and INACT_AC/DC Bits

A setting of 0 selects dc-coupled operation, and a setting of 1
enables ac-coupled operation. In dc-coupled operation, the
current acceleration magnitude is compared directly with
THRESH_ACT and THRESH_INACT to determine whether
activity or inactivity is detected.

Rev. C | Page 18 of 28

Data Sheet ADXL313

In ac-coupled operation for activity detection, the acceleration
value at the start of activity detection is taken as a reference
value. New samples of acceleration are then compared to this
reference value and, if the magnitude of the difference exceeds
the THRESH_ACT value, the device triggers an activity interrupt.

Similarly, in ac-coupled operation for inactivity detection, a
reference value is used for comparison and is updated whenever
the device exceeds the inactivity threshold. After the reference
value is selected, the device compares the magnitude of the
difference between the reference value and the current acceleration
with THRESH_INACT. If the difference is less than the value in
THRESH_INACT for the time in TIME_INACT, the device is
considered inactive and the inactivity interrupt is triggered.

ACT_x and INACT_x Bits

A setting of 1 enables x-, y-, or z-axis participation in detecting
activity or inactivity. A setting of 0 excludes the selected axis
from participation. If all axes are excluded, the function is
disabled. For activity detection, all participating axes are
logically OR’ed, causing the activity function to trigger when
any of the participating axes exceeds the threshold. For inactiv­ity detection, all participating axes are logically AND’ed, causing
the inactivity function to trigger only if all participating axes are
below the threshold for the specified period of time.

Register 0x2C—BW_RATE (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 LOW_POWER Rate

LOW_POWER Bit

A setting of 0 in the LOW_POWER bit selects normal operation,
and a setting of 1 selects reduced power operation, which has
somewhat higher noise (see the Power Modes section for details).

Rate Bits

These bits select the device bandwidth and output data rate (see
Table 5 and Table 6 for details). The default value is 0x0A, which
translates to a 100 Hz output data rate. Select an output data
rate that is appropriate for the communication protocol and
frequency selected. Selecting too high of an output data rate
with a low communication speed results in samples being
discarded.

Register 0x2D—POWER_CTL (Read/Write)

D7 D6 D5 D4

0 I2C_DISABLE Link AUTO_SLEEP

D3 D2 D1 D0

Measure Sleep Wake-up

I2C_Disable Bit

The ADXL313 is capable of communicating via SPI or I2C
transmission protocols. Typically, these protocols do not
overlap; however, situations may arise where SPI transactions
can imitate an I

2

C start command. This causes the ADXL313 to
respond unexpectedly, causing a communications issue with
other devices on the network. To ensure that the ADXL313 does

not interpret SPI commands as an I

2

C start condition, assert the

I2C_Disable bit.

Link Bit

A setting of 1 in the link bit with both the activity and inactivity
functions enabled delays the start of the activity function until
inactivity is detected. After activity is detected, inactivity detection
begins, preventing the detection of activity. This bit serially links
the activity and inactivity functions. When this bit is set to 0,
the inactivity and activity functions are concurrent. Additional
information can be found in the Link Mode section.

When clearing the link bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the link bit is cleared
may have additional noise, especially if the device was asleep
when the bit was cleared.

AUTO_SLEEP Bit

If the link bit is set, a setting of 1 in the AUTO_SLEEP bit sets
the ADXL313 to switch to sleep mode when inactivity is detected
(that is, when acceleration is below the THRESH_INACT value for
at least the time indicated by TIME_INACT). A setting of 0
disables automatic switching to sleep mode. See the description of
the sleep bit in the Sleep Bit section for more information.

When clearing the AUTO_SLEEP bit, it is recommended that the
part be placed into standby mode and then set back to measure­ment mode with a subsequent write. This is done to ensure that
the device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the AUTO_SLEEP
bit is cleared may have additional noise, especially if the device
was asleep when the bit was cleared.

Measure Bit

A setting of 0 in the measure bit places the part into standby mode,
and a setting of 1 places the part into measurement mode. The

ADXL313 powers up in standby mode with minimum power

consumption.

Sleep Bit

A setting of 0 in the sleep bit puts the part into the normal mode
of operation, and a setting of 1 places the part into sleep mode.
Sleep mode suppresses DATA_READY (see Register 0x2E,
Register 0x2F, and Register 0x30), stops transmission of data to the
FIFO, and switches the sampling rate to one specified by the
wake-up bits. In sleep mode, only the activity function can be used.

When clearing the sleep bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the sleep bit is
cleared may have additional noise, especially if the device was
asleep when the bit was cleared.

Rev. C | Page 19 of 28

ADXL313 Data Sheet

Setting

Wak e -Up Bits

These bits control the frequency of readings in sleep mode as
described in Table 15.

Table 15. Frequency of Readings in Sleep Mode

D1 D0 Frequency (Hz)

0 0 8
0 1 4
1 0 2
1 1 1

Register 0x2E—INT_ENABLE (Read/Write)

D7 D6 D5 D4

DATA_READY 0 0 Activity
D3 D2 D1 D0
Inactivity 0 Watermark Overrun

Setting bits in this register to a value of 1 enables their respective
functions to generate interrupts, whereas a value of 0 prevents
the functions from generating interrupts. The DATA_READY,
watermark, and overrun bits enable only the interrupt output;
the functions are always enabled. It is recommended that interrupts
be configured before enabling their outputs.

Register 0x2F—INT_MAP (Read/Write)

D7 D6 D5 D4

DATA_READY 0 0 Activity
D3 D2 D1 D0
Inactivity 0 Watermark Overrun

Any bits set to 0 in this register send their respective interrupts to
the INT1 pin, whereas bits set to 1 send their respective interrupts
to the INT2 pin. All selected interrupts for a given pin are OR’ed.

Register 0x30—INT_SOURCE (Read Only)

D7 D6 D5 D4

DATA_READY 0 0 Activity
D3 D2 D1 D0
Inactivity 0 Watermark Overrun

Bits set to 1 in this register indicate that their respective functions
have triggered an event, whereas a value of 0 indicates that the
corresponding event has not occurred. The DATA_READY,
watermark, and overrun bits are always set if the corresponding
events occur, regardless of the INT_ENABLE register settings,
and are cleared by reading data from the DATA_Xx, DATA_Yx,
and DATA_Zx registers. The DATA_READY and watermark
bits may require multiple reads, as indicated in the FIFO mode
descriptions in the FIFO section. Other bits, and the corresponding
interrupts, are cleared by reading the INT_SOURCE register.

Register 0x31—DATA_FORMAT (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

SELF_TEST SPI INT_INVERT 0 FULL_RES Justify Range

The DATA_FORMAT register controls the presentation of data
to Register 0x32 through Register 0x37. All data, except that for
the ±4 g range, must be clipped to avoid rollover.

SELF_TEST Bit

A setting of 1 in the SELF_TEST bit applies a self test force to
the sensor, causing a shift in the output data. A value of 0 disables
the self test force.

SPI Bit

A value of 1 in the SPI bit sets the device to 3-wire SPI mode,
and a value of 0 sets the device to 4-wire SPI mode.

INT_INVERT Bit

A value of 0 in the INT_INVERT bit sets the interrupts to active
high, and a value of 1 sets the interrupts to active low.

FULL_RES Bit

When this bit is set to a value of 1, the device is in full resolution
mode, where the output resolution increases with the g range
set by the range bits to maintain 1024 LSB/g sensitivity. When
the FULL_RES bit is set to 0, the device is in 10-bit mode, and
the range bits determine the maximum g range and scale factor.

Justify Bit

A setting of 1 in the justify bit selects left (MSB) justified mode,
and a setting of 0 selects right justified (LSB) mode with sign
extension.

Range Bits

These bits set the g range as described in Table 16.

Table 16. g Range Setting

Setting

D1 D0 Range (g)

0 0 ±0.5
0 1 ±1
1 0 ±2
1 1 ±4

Rev. C | Page 20 of 28

Data Sheet ADXL313

FIFO_MODE

Trigger

Samples

Register 0x32 and Register 0x33—DATA_X0, DATA_X1 (Read Only), Register 0x34 and Register 0x35—DATA_Y0, DATA_Y1 (Read Only), Register 0x36 and Register 0x37—DATA_Z0, DATA_Z1 (Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

DATA_X0[7:0]
DATA_X1[7:0]
DATA_Y0[7:0]
DATA_Y1[7:0]
DATA_Z0[7:0]
DATA_Z1[7:0]

These six bytes (Register 0x32 to Register 0x37) are eight bits
each and hold the output data for each axis. Register 0x32 and
Register 0x33 hold the output data for the x-axis, Register 0x34 and
Register 0x35 hold the output data for the y-axis, and Register 0x36
and Register 0x37 hold the output data for the z-axis.

The output data is twos complement, with DATA_x0 as the least
significant byte and DATA_x1 as the most significant byte, where x
represents X, Y, or Z. The DATA_FORMAT register (Address
0x31) controls the format of the data. It is recommended that a
multiple-byte read of all registers be performed to prevent a
change in data between reads of sequential registers.

Register 0x38—FIFO_CTL (Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

FIFO_MODE Bits

These bits set the FIFO mode, as described in Tabl e 17.

Table 17. FIFO Modes

Setting

D7 D6 Mode Function

0 0 Bypass FIFO is bypassed.
0 1 FIFO FIFO collects up to 32 values and then

stops collecting data, collecting new data
only when FIFO is not full.

1 0 Stream FIFO holds the last 32 data values. When

FIFO is full, the oldest data is overwritten
with newer data.

1 1 Trigger When triggered by the trigger bit, FIFO

holds the last data samples before the
trigger event and then continues to collect
data until full. New data is collected only
when FIFO is not full.

Trigger Bit

A value of 0 in the trigger bit links the trigger event to INT1,
and a value of 1 links the trigger event to INT2.

Samples Bits

The function of these bits depends on the FIFO mode selected
(see Table 18). Entering a value of 0 in the samples bits immedi­ately sets the watermark status bit in the INT_SOURCE register,
regardless of which FIFO mode is selected. Undesirable opera­tion may occur if a value of 0 is used for the samples bits when
trigger mode is used.

Table 18. Samples Bits Functions

FIFO Mode Samples Bits Function

Bypass None.
FIFO Specifies how many FIFO entries are needed to

trigger a watermark interrupt.

Stream Specifies how many FIFO entries are needed to

trigger a watermark interrupt.

Trigger Specifies how many FIFO samples are retained in

the FIFO buffer before a trigger event.

0x39—FIFO_STATUS (Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

FIFO_TRIG 0 Entries

FIFO_TRIG Bit

A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
and a 0 means that a FIFO trigger event has not occurred.

Entries Bits

These bits report how many data values are stored in the FIFO.
Access to collect the data from the FIFO is provided through
the DATA_Xx, DATA_Yx, and DATA_Zx registers. FIFO reads
must be done in burst or multiple-byte mode because each FIFO
level is cleared after any read (single- or multiple-byte) of the
FIFO. The FIFO stores a maximum of 32 entries, which equates
to a maximum of 33 entries available at any given time because
an additional entry is available at the output filter of the device.

Rev. C | Page 21 of 28

ADXL313 Data Sheet

ADXL313

GND

INT1
INT2

CS

SCL/SCLK

SDO/ALT ADDRESS

SDA/SDI/SDIO

3-WIRE O R
4-WIRE SPI
OR I

2

C

INTERFACE

V

S

V

S

C

S

V

DD I/O

V

DD I/O

C

I/O

INTERRUPT

CONTROL

11469-019

MOUNTING POINTS

PCB

ACCELEROMETERS

11469-020

APPLICATIONS INFORMATION

POWER SUPPLY DECOUPLING

A 1 μF tantalum capacitor (CS) at VS and a 0.1 μF ceramic capacitor
(C

) at V

I/O

recommended to adequately decouple the accelerometer from
noise on the power supply. If additional decoupling is necessary,
a resistor or ferrite bead, no larger than 100 Ω, in series with V
may be helpful. Additionally, increasing the bypass capacitance
on V

to a 10 μF tantalum capacitor in parallel with a 0.1 μF

S

ceramic capacitor may also improve noise.
Take care to ensure that the connection from the ADXL313

ground to the power supply ground has low impedance because
noise transmitted through ground has an effect similar to noise
transmitted through V
be separate supplies to minimize digital clocking noise on the
V

supply. If this is not possible, additional filtering of the

S

supplies as previously mentioned may be necessary.

placed close to the ADXL313 supply pins is

DD I/O

. It is recommended that VS and V

S

DD I/O

S

THRESHOLD

The lower output data rates are achieved by decimating a
common sampling frequency inside the device. The activity
detection function is performed using undecimated data.
Because the bandwidth of the output data varies with the data
rate and is lower than the bandwidth of the undecimated data,
the high frequency and high g data that are used to determine
activity may not be present if the output of the accelerometer is
examined. This may result in functions triggering when accelera­tion data does not appear to meet the conditions set by the user
for the corresponding function.

LINK MODE

The function of the link bit in the POWER_CTL register
(Address 0x2D) is to reduce the number of activity interrupts
that the processor must service by setting the device to look
for activity only after inactivity. For proper operation of this
feature, the processor must still respond to the activity and
inactivity interrupts by reading the INT_SOURCE register
(Address 0x30) and, therefore, clearing the interrupts. If an activity
interrupt is not cleared, the part cannot go into autosleep mode.

Figure 23. Application Diagram

MECHANICAL CONSIDERATIONS FOR MOUNTING

Mount the ADXL313 on the PCB in a location close to a hard
mounting point of the PCB to the case. Mounting the ADXL313
at an unsupported PCB location, as shown in Figure 24, may
result in large, apparent measurement errors due to undamped
PCB vibration. Placing the accelerometer near a hard mounting
point ensures that any PCB vibration at the accelerometer is above
the accelerometer’s mechanical sensor resonant frequency and,
therefore, effectively invisible to the accelerometer. Multiple
mounting points close to the sensor and/or a thicker PCB also
help to reduce the effect of system resonance on the performance
of the sensor.

Figure 24. Incorrectly Placed Accelero meters

SLEEP MODE vs. LOW POWER MODE

In applications where a low data rate and low power consumption
are desired (at the expense of noise performance), it is recom­mended that low power mode be used. The use of low power
mode preserves the functionality of the DATA_READY
interrupt and the FIFO for postprocessing of the acceleration
data. Sleep mode, while offering a low data rate and low power
consumption, is not intended for data acquisition.

However, when sleep mode is used in conjunction with the
autosleep mode and the link mode, the part can automatically
switch to a low power, low sampling rate mode when inactivity
is detected. To prevent the generation of redundant inactivity
interrupts, the inactivity interrupt is automatically disabled and
activity is enabled. When the ADXL313 is in sleep mode, the host
processor can also be placed into sleep mode or low power
mode to save significant system power. When activity is
detected, the accelerometer automatically switches back to the
original data rate of the application and provides an activity
interrupt that can be used to wake up the host processor.
Similar to when inactivity occurs, detection of activity events is
disabled and inactivity is enabled.

Rev. C | Page 22 of 28

Data Sheet ADXL313

USING SELF TEST

The self test change is defined as the difference between the
acceleration output of an axis with self test enabled and the
acceleration output of the same axis with self test disabled (see
Endnote 4 of Table 1). This definition assumes that the sensor
does not move between these two measurements because, if the
sensor moves, a nonself test related shift corrupts the test.

Proper configuration of the ADXL313 is also necessary for an
accurate self test measurement. Set the part with a data rate
greater than or equal to 100 Hz. This is done by ensuring that a
value greater than or equal to 0x0A is written into the rate bits
(Bit D3 through Bit D0) in the BW_RATE register (Address 0x2C).
The part must also be placed into normal power operation by
ensuring that the LOW_POWER bit in the BW_RATE register
is cleared (LOW_POWER bit = 0) for accurate self test measure­ments. It is recommended that the part be set to full resolution,
±4 g mode to ensure that there is sufficient dynamic range for
the entire self test shift. This is done by setting Bit D3 of the
DATA_FORMAT register (Address 0x31) and writing a value of
0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT
register. This results in a high dynamic range for measurement
and 1024 LSB/g sensitivity.

After the part is configured for accurate self test measurement,
several samples of x-, y-, and z-axis acceleration data should be
retrieved from the sensor and averaged together. The number of
samples averaged is a choice of the system designer, but a recom­mended starting point is 0.1 sec worth of data, which corresponds
to 10 samples at 100 Hz data rate. Store and label the averaged
values appropriately as the self test disabled data, that is, X
Y

ST_OFF

, and Z

ST_OFF

.

ST_OFF

,

Next, enable self test by setting Bit D7 of the DATA_FORMAT
register (Address 0x31). The output needs some time (about
four samples) to settle after enabling self test. After allowing the
output to settle, take several samples of the x-, y-, and z-axis
acceleration data, and average them. It is recommended that the
same number of samples be taken for this average as was previously
taken. Store and label these averaged values appropriately as the
value with self test enabled, that is, X

ST_ON

, Y

ST_ON

, and Z

ST_ON

.
Self test can then be disabled by clearing Bit D7 of the DATA_
FORMAT register (Address 0x31).

With the stored values for self test enabled and disabled, the self
test change is as follows:

X

= X

ST

Y

= Y

ST

= Z

Z

ST

ST_ON

ST_ON

ST_ON

− X

− Y

− Z

ST_OFF

ST_OFF

ST_OFF

Because the measured output for each axis is expressed in LSBs,

, YST, and ZST are also expressed in LSBs. These values can be

X

ST

converted to acceleration (g) by multiplying each value by the
sensitiv ity, 1024 LSB/g, when configured for full resolution
mode. When operating in 10-bit mode, the self test delta in
LSBs varies according to the selected g range, even though the
self test force, in g, remains unchanged. Using a range below
±4 g may result in insufficient dynamic range and should be
considered when selecting the range of operation for measuring
self test.

If the self test change is within the valid range, the test is considered
successful. Generally, a part is considered to pass if the minimum
magnitude of change is achieved. However, a part that changes
by more than the maximum magnitude is not necessarily a failure.

Rev. C | Page 23 of 28

ADXL313 Data Sheet

0 1 ±1

D0

0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D7

DATA_x1 REGISTER DATA_x0 REGISTER

FOR THE RIGHT JUSTIFIED DATA:
WHEN OPERATING THE ADX L313 WITH AN OUTPUT RAT E OF EITHE R 3200Hz OR 1600Hz, THE D0 BIT OF
THE DATA_x0 REG I S TER IS ALWAYS 0 UNDER EITHER OF T HE FOLLOWING CONDITIONS:

1) FULL RE S OLUTIO N M ODE IS ENABL E D ( ANY g RANGE) , OR

2) DEVICE RANGE IS SET TO ±0.5g

11469-021

D0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D7

DATA_x1 REGISTER DATA_x0 REGIS TER

FULL RESOLUTION MODE; LSB FOR ±1g RANGE = 0

FULL RESOLUTION MODE; LSB FOR ±4g RANGE = 0

FULL RESOLUTION MODE; LSB FOR ±2g RANGE = 0

FULL RES OLUTIO N AND 10- BIT MODE: LSB FOR ±0. 5 RANGE = 0

11469-022

FOR THE LEFT JUSTIFIED DATA:
WHEN OPERATING THE ADX L313 WITH AN OUTPUT RAT E OF EITHE R 3200Hz OR 1600Hz, THE LSB OF T HE
ACCELERATI O N DATA-WORD I S ALWAYS 0 UNDER T HE FOLLOWING CO NDITIONS :

1) FULL RE S OLUTIO N M ODE IS ENABL E D ( ANY g RANGE) , OR

2) DEVICE RANGE IS SET TO ±0.5g.
FULL RESOLUTION MODE CAUSES THE LOCATION OF THE LSB TO CHANGE ACCORDING TO
THE SELECTED g RANGE. ALTHOUGH ITS LOCATION MAY CHANGE, ITS VALUE WILL REMAIN 0.

3200 Hz AND 1600 Hz ODR DATA FORMATTING

The following section applies for 3200 Hz and 1600 Hz output
data rates only. This section can be ignored for all other data rates.

For 3200 Hz and 1600 Hz output data rates, when the ADXL313
is configured for either a ±0.5 g output range or the full resolution
mode is enabled, the LSB of the output data-word is always 0.
If the acceleration data-word is right justified, this corresponds
to Bit D0 of the DATA_x0 register, as shown in Figure 25 and
Table 19.

When data is left justified and the part is operating in ±0.5 g
mode, the LSB of the output data-word is Bit D6 of the DATAx0
register. In full resolution operation, the location of the LSB
changes according to the selected output range. Table 19 and
Figure 26 demonstrate how the position of the LSB changes
when full resolution mode is enabled.

Table 19. Conditions for Which the LSB Is Set to 0 (3200 Hz
and 1600 Hz Output Data Rates Only)

Justify
(0x31[2])

FULL_RES
(0x31[3])

Range
(g)

LSB Bit Position

0 0 or 1 ±0.5 D0

0 1 ±2 D0
0 1 ±4 D0
1 0 or 1 ±0.5 D6
1 1 ±1 D5
1 1 ±2 D4
1 1 ±4 D3

The use of 3200 Hz and 1600 Hz output data rates for fixed 10-bit
operation in the ±1 g, ±2 g, and ±4 g output ranges provides an
LSB that is valid and that changes according to the applied accel­eration. Therefore, in these modes of operation, Bit D0 is not
always 0 when output data is right justified, and Bit D6 is not
always 0 when output data is left justified.

Figure 25. Right Justified Data Formatting: 3200 Hz and 1600 Hz Output Data Rate

Figure 26. Left Justified Data Formatting: 3200 Hz and 1600 Hz Output Data Rate

Rev. C | Page 24 of 28

Data Sheet ADXL313

A

Z

A

Y

A

X

11469-023

GRAVITY

X

OUT

= +1g

Y

OUT

= 0g

Z

OUT

= 0g

X

OUT

= –1g

Y

OUT

= 0g

Z

OUT

= 0g

TOP

X

OUT

= 0g

Y

OUT

= +1g

Z

OUT

= 0g

TOP

X

OUT

= 0g

Y

OUT

= –1g

Z

OUT

= 0g

TOP

X

OUT

= 0g

Y

OUT

= 0g

Z

OUT

= +1g

X

OUT

= 0g

Y

OUT

= 0g

Z

OUT

= –1g

TOP

11469-024

AXES OF ACCELERATION SENSITIVITY

Figure 27. Axes of Acceleration Sensitivity (Corresponding Output Increases When Accelerated Along the Sensitive Axis)

Figure 28. Output Response vs. Orientation to Gravity

Rev. C | Page 25 of 28

ADXL313 Data Sheet

SUPPLIER T

P

≥ T

C

USER T

P

≤ T

C

MAXIMUM RAMP - UP RATE = 3°C/sec

MAXIMUM RAMP - DOWN RATE = 6°C/sec

PREHEAT AREA

T

C

T

C

– 5°C

T

C

– 5°C

T

SMAX

T

SMAX

T

L

T

P

t

P

t

L

t

S

SUPPLIER

t

P

USER

t

P

TEMPERATURE

TIME

TIME 25°C TO PEAK

25

11469-025

Time (tL)

60 sec to 150 sec

60 sec to 150 sec

SOLDER PROFILE

Figure 29. Recommended Soldering Profile

Table 20. Recommended Soldering Profile

1, 2

Condition

Profile Feature

Sn63/Pb37 Pb-Free

Average Ramp Rate (TL to TP) 3°C/sec maximum 3°C/sec maximum
Preheat

Minimum Temperature (T
Maximum Temperature (T

SMIN

to T

) (tS) 60 sec to 120 sec 60 sec to 120 sec

SMAX

Time (T

T

to TL

SMAX

Ramp-Up Rate 3°C/sec 3°C/sec

) 100°C 150°C

SMIN

) 150°C 200°C

SMAX

Time Maintained Above Liquidous (tL)

Liquidous Temperature (TL) 183°C 217°C

Peak Temperature (TP) 240°C + 0°C/−5°C 260°C + 0°C/−5°C
Time Within 5°C of Actual Peak Temperature (tP) 10 sec to 30 sec 20 sec to 40 sec
Ramp-Down Rate 6°C/sec maximum 6°C/sec maximum
Time 25°C to Peak Temperature 6 min maximum 8 min maximum

1

Based on JEDEC standard J-STD-020D.1.

2

For best results, ensure that the soldering profile is in accordance with the recommendations of the manufacturer of the solder paste used.

Rev. C | Page 26 of 28

Data Sheet ADXL313

1

0.50

BSC

32

9

16

17

24

25

8

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.05

0.30

0.25

0.18

5.10

5.00 SQ

4.90

1.55

1.45

1.35

0.45

0.40

0.35

0.20 MIN

3.70

3.60 SQ

3.50

COMPLI ANT TO JEDEC STANDARDS MO-254-LJJD

09-12-2018-B

BOTTOM VIEW

TOP VIEW

PKG-003616

EXPOSED

PAD

END VIEW

PIN 1
IN DI CATO R AR E A OP T IO N S
(SEE DETAIL A)

DETAIL A

(JEDEC 95)

FOR PROPE R CONNECTIO N OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTIO N DES CRIPTIO NS
SECTION OF THIS DATA SHEET.

SEATING

PLANE

PIN 1

INDICATOR

AREA

1

1469-027

0.30mm

0.30mm

0.30mm

0.50mm

3.60mm

5.34mm

0.57mm

OUTLINE DIMENSIONS

Figure 30. 32-Lead Lead Frame Chip Scale Package [LFCSP_LQ]

5 mm × 5 mm Body, Thick Quad

(CP-32-17)

Dimensions shown in millimeters

Figure 31. Sample Solder Pad Layout (Land Pattern)

Rev. C | Page 27 of 28

ADXL313 Data Sheet

ORDERING GUIDE

Measurement
Range

Model

1, 2

ADXL313WACPZ-RL ±0.5 g/±1 g/±2 g/±4 g 3.3 −40°C to +105°C

Specified
Voltage (V)

Temperature
Range

Package Description

32-Lead Lead Frame Chip Scale Package
[LFCSP_LQ]

ADXL313WACPZ-RL7 ±0.5 g/±1 g/±2 g/±4 g 3.3 −40°C to +105°C

32-Lead Lead Frame Chip Scale Package
[LFCSP_LQ]

EVAL-ADXL313-Z

1

Z = RoHS Compliant Part.

2

W = Qualified for Automotive Applications.

Evaluation Board

AUTOMOTIVE PRODUCTS

The ADXL313W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

Package
Option

CP-32-17

CP-32-17

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D11469-0-2/19(C)

Rev. C | Page 28 of 28