ANALOG DEVICES ADW12001 Service Manual

14-Bit, 40 MSPS

FEATURES

Integrated dual 14-bit ADC
Single 3 V supply operation: 2.7 V to 3.6 V
Differential input with 500 MHz, 3 dB bandwidth
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option

APPLICATIONS

Ultrasound equipment
Direct conversion or IF sampling receivers

WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes

GENERAL DESCRIPTION

The ADW12001 is a dual, 3 V, 14-bit, 40 MSPS analog-to­digital converter (ADC). It features dual high performance
sample-and-hold amplifiers (SHAs) and an integrated voltage
reference. The ADW12001 uses a multistage differential
pipelined architecture with output error correction logic to
provide 14-bit accuracy and to guarantee no missing codes
over the full operating temperature. The wide bandwidth
differential SHA allows for a variety of user-selectable input
ranges and offsets, including single-ended applications. It is
suitable for various applications, including multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling inputs at frequencies well beyond the Nyquist rate.

Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos com­plement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.

Dual Analog-to-Digital Converter

ADW12001

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND

VIN+_A

VIN–_A

REFT_A

REFB_A

VREF

SENSE

AGND

REFT_B

REFB_B

VIN+_B

VIN–_B

SHA

0.5V

SHA

ADW12001

14

ADC

BUFFERS

DUTY CYCLE

STABILIZER

CONTROL

ADC

BUFFERS

DRVDD DRGND

Figure 1.

OUTPUT

MUX/

CLOCK

MODE

OUTPUT

MUX/

Fabricated on an advanced CMOS process, the ADW12001
is available in a Pb-free, space saving, 64-lead LFCSP and
is specified over the industrial temperature range (−40°C
to +115°C).

PRODUCT HIGHLIGHTS

1. Pin compatible with the AD9238, 12-bit 40 MSPS ADC.

2. Low power consumption: 40 MSPS = 330 mW.

3. Typical channel isolation of 85 dB @ f

4. The clock duty cycle stabilizer maintains performance over

a wide range of clock duty cycles.

5. Multiplexed data output option enables single port

operation from either Data Port A or Data Port B.

IN

OTR_A

14

D13_A TO D0_A

OEB_A

MUX_SELECT

CLK_A

CLK_B

DCS

SHARED_REF

PWDN_A

PWDN_B

DFS

OTR_B

1414

D13_B TO D0_B

OEB_B

= 10 MHz.

07737-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADW12001

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Table of Contents .............................................................................. 2

Revision History ........................................................................... 2

Specifications ..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications .......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ..............................9

Ter minology .................................................................................... 11

Typical Performance Characteristics ........................................... 12

Equivalent Circuits ......................................................................... 15

Theory of Operation ...................................................................... 16

Analog Input ............................................................................... 16

Clock Input and Considerations .............................................. 17

Power Dissipation and Standby Mode .................................... 18

Digital Outputs ........................................................................... 18

Timing ......................................................................................... 18

Data Format ................................................................................ 19

Voltage Reference ....................................................................... 19

Thermal Considerations ............................................................ 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

1/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADW12001

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
T

to T

MIN

Table 1.

Parameter Te mp Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 Bits
ACCURACY

No Missing Codes Guaranteed Full 14 14 Bits

Offset Error 25°C ±0.2 ±1.3 ±0.2 ±1.3 % FSR

Gain Error

Differential Nonlinearity (DNL)

25°C ±0.6 ±1.0 ±0.65 ±1.0 LSB

Integral Nonlinearity (INL)

25°C ±2.3 ±4.5 ±2.4 ±4.5 LSB
TEMPERATURE DRIFT

Offset Error Full ±2 ±2 ppm/°C

Gain Error

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±35 ±5 ±35 mV

Load Regulation @ 1.0 mA Full 0.8 0.8 mV

Output Voltage Error (0.5 V Mode) Full ±2.5 ±2.5 mV

Load Regulation @ 0.5 mA Full 0.1 0.1 mV

INPUT REFERRED NOISE

Input Span = 1 V 25°C 2.1 2.1 LSB rms

Input Span = 2.0 V 25°C 1.05 1.05 LSB rms

ANALOG INPUT

Input Span = 1.0 V Full 1 1 V p-p

Input Span = 2.0 V Full 2 2 V p-p

Input Capacitance

REFERENCE INPUT RESISTANCE Full 7 7 kΩ
POWER SUPPLIES

Supply Voltages

Supply Current

PSRR Full ±0.01 ±0.01 % FSR

POWER CONSUMPTION

DC Input

Sine Wave Input

Standby Power

, DCS enabled, unless otherwise noted.

MAX

25°C 115°C

1

Full ±0.3 ±2.4 ±0.5 ±2.5 % FSR

1

Full ±12 ±12 ppm/°C

3

Full 7 7 pF

2

Full ±0.65 ±0.7 LSB

2

Full ±2.7 ±2.8 LSB

AVDD Full 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD Full 2.25 3.0 3.6 2.25 3.0 3.6 V

2

IAVDD

Full 110 115 mA

IDRVDD

2

Full 10 11 mA

4

Full 330 350 mW

2

Full 360 400 315 412 mW

5

Full 7.0 7.0 mW

Rev. 0 | Page 3 of 24

ADW12001

25°C 115°C

Parameter Te mp Min Typ Max Min Typ Max Unit

MATCHING CHARACTERISTICS

Offset Error (Nonshared Reference Mode) 25°C ±0.19 ±1.56 ±0.25 ±1.74 % FSR
Offset Error (Shared Reference Mode) 25°C ±0.19 ±1.56 ±0.25 ±1.74 % FSR
Gain Error (Nonshared Reference Mode) 25°C ±0.07 ±1.43 ±0.07 ±1.47 % FSR
Gain Error (Shared Reference Mode) 25°C ±0.01 ±0.06 ±0.01 ±0.10 % FSR

1

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference).

2

Measured at the maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.

3

Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 18

4

Measured with dc input at the maximum clock rate.

5

Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).

Rev. 0 | Page 4 of 24

ADW12001

AC SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V external reference,
T

to T

MIN

Table 2.

Parameter Te mp Min Ty p Max Min Ty p Max Unit
SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.4 MHz Full

25°C 72.8 73.4 70.0 72.5 dB

fIN = 19.6 MHz Full

25°C 72.3 72.9 70.5 71.8 dB

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

fIN = 2.4 MHz Full dB

25°C 72.0 73.0 69.5 72.0 dB

fIN = 19.6 MHz Full dB

25°C 71.0 72.3 69.5 71.5 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.4 MHz Full 11.6 Bits

25°C 11.7 11.8 Bits

WORST HARMONIC (SECOND or THIRD)

fIN = 2.4 MHz Full 86.0 dBc

25°C 77.5 86.0 77 dBc

fIN = 19.6 MHz Full dBc

25°C 76.0 84.0 dBc

85 dBc

75 dBc

WORST OTHER SPUR (NONSECOND or THIRD)

fIN = 2.4 MHz Full 88.0 84 dBc

25°C 83.5 89.0 dBc

fIN = 19.6 MHz Full 88.0 85 dBc

25°C 82.6 88.5 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.4 MHz Full 85.0 84 92 dBc

25°C 77.5 86.0 77.5 86.0 dBc

fIN = 19.6 MHz Full 83.0 85 90 dBc

25°C 76.0 84.0 dBc

CROSSTALK Full −85.0 −85.0 dB

, DCS enabled, unless otherwise noted.

MAX

25°C 115°C

Rev. 0 | Page 5 of 24

ADW12001

DIGITAL SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
T

to T

MIN

Table 3.

Parameter Tem p Min Typ Max Unit
LOGIC INPUTS

High Level Input Voltage Full 2.0 V
Low Level Input Voltage Full 0.8 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full −10 +10 μA
Input Capacitance Full 2 pF

LOGIC OUTPUTS

High Level Output Voltage Full DRVDD − 0.05 V
Low Level Output Voltage Full 0.05 V

1

Output voltage levels measured with capacitive load only on each output.

, DCS enabled, unless otherwise noted.

MAX

1

25°C/115°C

Rev. 0 | Page 6 of 24

ADW12001

A

SWITCHING SPECIFICATIONS

AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
T

to T

MIN

Table 4.

Parameter Te mp Min Typ Max Unit
SWITCHING PERFORMANCE

Maximum Conversion Rate Full 40 MSPS

Minimum Conversion Rate Full 1 MSPS

CLK Period Full 25.0 ns

CLK Pulse Width High

CLK Pulse Width Low

DATA OUTPUT PARAMETER

Output Delay2 (tPD) Full 2 3.5 6 ns

Pipeline Delay (Latency) Full 7 Cycles

Aperture Delay (tA) Full 1.0 ns

Aperture Uncertainty (tJ) Full 0.5 ps rms

Wake-Up Time

OUT-OF-RANGE RECOVERY TIME Full 2 Cycles

1

This model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 16).

2

Output delay is measured from clock 50% transition to data 50% transition with a 5 pF load on each output.

3

Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.

Timing Diagram

, DCS enabled, unless otherwise noted.

MAX

1

1

Full 8.8 ns

3

Full 2.5 ms

N

NALOG

INPUT

N – 1

N + 1

N + 2

Full 8.8 ns

N + 8

N + 3

N + 4

N + 5

N + 6

N + 7

CLOCK

DATA

OUT

N – 9 N – 8

N – 7

N – 6

N – 5

Figure 2. Timing Diagram

N – 4

N – 3

N – 2

N – 1

N

t

PD

MIN 2.0ns,

=

MAX 6.0ns

07737-002

Rev. 0 | Page 7 of 24

ADW12001

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter1 Rating

Electrical

AVDD to AGND −0.3 V to +3.9 V
DRVDD to DRGND −0.3 V to +3.9 V
AGND to DRGND −0.3 V to +0.3 V
AVDD to DRVDD −3.9 V to +3.9 V
Digital Outputs CLK_A, CLK_B, DCS,

MUX_SELECT, SHARED_REF to DRGND
OEB, DFS to AGND

VIN±_A, VIN±_B to AGND

VREF to AGND

SENSE to AGND

REFB_A, REFB_B, REFT_A, REFT_B to AGND

PDWN_A, PDWN_B to AGND

Environmental2

Operating Temperature Range −45°C to +115 °C
Junction Temperature 150°C
Lead Temperature (10 sec) 300°C
Storage Temperature Range −65°C to +150°C

1

Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied.

2

Typical thermal impedances: 64-lead LFCSP, θJA = 26.4°C/W with heat slug

soldered to the ground plane. These measurements were taken on a 4-layer
board in still air, in accordance with EIA/JESD51-7.

−0.3 V to
DRVDD + 0.3 V

−0.3 V to
AVDD + 0.3 V

−0.3 V to
AVDD + 0.3 V

−0.3 V to
AVDD + 0.3 V

−0.3 V to
AVDD + 0.3 V

−0.3 V to
AVDD + 0.3 V

−0.3 V to
AVDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA Unit

64-Lead LFCSP 26.4 °C/W

ESD CAUTION

Rev. 0 | Page 8 of 24