ANALOG DEVICES ADV7619 Service Manual

3 GHz HDMI Receiver

ADV7619

Rev. B

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Fax: [phone] ©2011–2012 Analog Devices, Inc. All rights reserved.

TMDS

DDC

TMDS

DDC

COMPONENT
PROCESSOR

HS/VS

FIELD/DE

CLK

DATA

I2S

S/PDIF

DSD
HBR

MCLK

HS

VS/FIELD

DE

AUDIO

OUTPUT

MCLK

SCLK

CLK

36-/48-BIT

OUTPUT BUS

SCLK

LRCLK

36

48

OUTPUT M UX

OUTPUT M UX

HDMI1

HDMI2

ADV7619

09580-001

FAST

SWITCH

HDCP
KEYS

DEEP

COLOR

HDMI Rx

Data Sheet

FEATURES

High-Definition Multimedia Interface (HDMI®) 1.4a features

supported
All mandatory and additional 3D video formats supported
Extended colorimetry, including sYCC601, Adobe® RGB,

Adobe YCC601, xvYCC extended gamut color

CEC 1.4-compatible

HDMI 3 GHz receiver

297 MHz maximum TMDS clock frequency
Supports 4k × 2k resolution
Xpressview fast switching of HDMI ports
Up to 48-bit Deep Color with 36-/30-/24-bit support
High-bandwidth Digital Content Protection (HDCP) 1.4

support with internal HDCP keys
HDCP repeater support: up to 127 KSVs supported
Integrated CEC controller
Programmable HDMI equalizer
5 V detect and Hot Plug assert for each HDMI port

Audio support

Audio support including high bit rate (HBR) and

Direct Stream Digital (DSD)
S/PDIF (IEC 60958-compatible) digital audio support
Supports up to four I

2

S outputs

Dual Port, Xpressview,

Advanced audio mute feature
Dedicated, flexible audio output port
Super Audio CD® (SACD) with DSD output interface
HBR audio

Dolby® TrueH D
DTS-HD Master Audio™

General

Interrupt controller with 2 interrupt outputs
Standard identification (STDI) circuit
Highly flexible, 48-bit pixel output interface
36-bit output for resolutions up to 1080p Deep Color
2 × 24-bit pass-through outputs for HDMI formats

greater than 2.25 GHz
Internal EDID RAM
Any-to-any, 3 × 3 color space conversion (CSC) matrix
128-lead TQFP_EP, 14 mm × 14 mm package

APPLICATIONS

Projectors
Video conferencing
HDTV
AVR, HTiB
Soundbar
Video switch

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may resul t from its use. Specifications subject to cha nge without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

ADV7619 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Detailed Functional Block Diagram .......................................... 3

Specifications ..................................................................................... 4

Electrical Characteristics ............................................................. 4

Data and I2C Timing Characteristics ......................................... 6

Absolute Maximum Ratings ............................................................ 8

Package Thermal Performance ................................................... 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

REVISION HISTORY

5/12—Rev. A to Rev. B

Changes to Features Section............................................................ 1

Changes to General Description Section and Figure 2

ange to Table 1 ............................................................................. 4

Ch

Changes to Table 3 ............................................................................ 6

Changes to Figure 5; Deleted Figure 6, Renumbered

Sequentially ....................................................................................... 7

Changes to Figure 7 .......................................................................... 9

Changes t o Tabl e 5 .......................................................................... 11

Changes to HDMI Receiver Section and Other Features

Section .............................................................................................. 14

Deleted Time-Division Multiplexed (TDM) Mode Section

and Figure 9 ..................................................................................... 15

............... 3

Power Supply Recommendations ................................................. 13

Power-Up Sequence ................................................................... 13

Power-Down Sequence .............................................................. 13

Current Rating Requirements for Power Supply Design ...... 13

Functional Overview ...................................................................... 14

HDMI Receiver ........................................................................... 14

Component Processor (CP) ...................................................... 14

Other Features ............................................................................ 14

Pixel Input/Output Formatting .................................................... 15

Pixel Data Output Mode Features ............................................ 15

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

9/11—Rev. 0 t o R e v. A

Changes to General Description Section ...................................... 3

Changes to Data Output Transition Time Typ Values, Table 3 ... 6

Changes to Pin 113 Description ................................................... 12

Changes to Pixel Input/Output Formatting Section .................. 16

Added Endnote 1 to Tab l e 7 .......................................................... 17

Added Endnote 1 to Tab l e 1 2 ........................................................ 22

Changes to Ordering Guide .......................................................... 23

7/11—Revision 0: Initial Version

Rev. B | Page 2 of 24

Data Sheet ADV7619

09580-002

MUTE

XTALP
XTALN

SCL

SDA

CS

CEC

AP1
AP2
AP3
AP4

AP5

AP0

SCLK/INT2*
MCLK/INT2*

INT1
INT2*

P0 TO P11
P12 TO P23
P24 TO P35
P36 TO P47
LLC

HS
VS/FIELD/ALSB

DE

RXB_0±
RXB_1±
RXB_2±

RXA_0±
RXA_1±
RXA_2±

PLLs

RXA_C±
RXB_C±

DDCA_SDA

DDCA_SCL

DDCB_SDA

DDCB_SCL

HPA_A/INT2*

HPA_B

RXA_5V
RXB_5V

EQUALIZER

SAMPLER

EQUALIZER

HDCP

ENGINE

HDCP
KEYS

EDID

REPEATER

CONTROLLER

5V DETECT

AND HDP

CONTROLLER

CEC

CONTROLLER

CONTROL

INTERFACE

I

2

C

DPLL

CONTROL AND DATA

300MHz VIDEO PATH

HDMI

PROCESSOR

PACKET/

INFOFRAME

MEMORY

AUDIO

PROCESSOR

A
B
C

COMPONENT
PROCESSOR

BACK-END

COLOR
SPACE

CONVERSION

INTERRUPT

CONTROLLER

(INT1, INT2)

DATA

PREPROCESSOR

AND COLOR

SPACE

CONVERSION

PACKET

PROCESSOR

*INT2 CAN BE MADE AVAILABLE ON ONE OF THESE PINS: HPA_A/INT2, MCLK/INT2, OR SCL K/INT2.

Xpressview

FAST SWITCHI NG

SAMPLER

ADV7619

VIDEO OUTPUT FORMATTERAUDIO OUTPUT FORMATTER

GENERAL DESCRIPTION

The ADV7619 is a high quality, two input, one output (2:1)
multiplexed High-Definition Multimedia Interface (HDMI®)
receiver. The ADV7619 is offered in professional (no HDCP
keys) and commercial versions. The operating temperature
range is 0°C to 70°C.

The ADV7619 incorporates a dual input HDMI-capable
receiver that supports all mandatory 3D TV formats defined in
the HDMI 1.4a specification, HDTV formats up to 1080p 36-bit
Deep Color/2160p 8-bit, and display resolutions up to 4k × 2k
(3840 × 2160 at 30 Hz). It integrates an HDMI CEC controller
that supports the capability discovery and control (CDC) feature.

The ADV7619 incorporates Xpressview™ fast switching on both
input HDMI ports. Using the Analog Devices, Inc., hardware­based HDCP engine to minimize software overhead, Xpressview
technology allows fast switching between both HDMI input ports
in less than 1 sec.

Each HDMI port has dedicated 5 V detect and Hot Plug™ assert
pins. The HDMI receiver also includes an integrated program­mable equalizer that ensures robust operation of the interface
with long cables.

The ADV7619 offers a flexible audio output port for audio data
extraction from the HDMI stream. HDMI audio formats, includ­ing SACD via DSD and HBR, are supported by the ADV7619.

DETAILED FUNCTIONAL BLOCK DIAGRAM

The HDMI receiver has advanced audio functionality, such as
a mute controller, that prevents audible extraneous noise in the
audio output.

The ADV7619 contains one main component processor (CP),
which processes video signals from the HDMI receiver up to
1080p 36-bit Deep Color. It provides features such as contrast,
brightness and saturation adjustments, STDI detection block,
free-run, and synchronization alignment controls.

For video formats with pixel clocks higher than 170 MHz, the
video signals received on the HDMI receiver are output directly
to the pixel port output. To accommodate the higher bandwidth
required for these higher resolutions, the output on the pixel bus
consists of two 24-bit buses running at up to 150 MHz: one bus
contains the even pixels, and the other bus contains the odd
pixels. When these two buses are combined, they allow the
transfer of video data with pixel clocks up to 300 MHz. In this
mode, both 4:4:4 RGB 8-bit and 4:2:2 12-bit are supported.

Fabricated in an advanced CMOS process, the ADV7619
is provided in a 14 mm × 14 mm, 128-lead, surface-mount,
RoHS-compliant TQFP_EP package and is specified over the
0°C to 70°C temperature range.

Rev. B | Page 3 of 24

Figure 2.

ADV7619 Data Sheet

Other digital inputs

2

V

DIGITAL OUTPUTS1

Output Capacitance

C

20

pF

Digital I/O Power Supply

DVDDIO

3.14

3.3

3.46

V

Test Condition 2

10 mA

Tes t Condition 2

166 mA

Digital Core Power Supply

I

1.07 mA

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V,
operating temperature range, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

DIGITAL INPUTS1

Input High Voltage VIH XTALN a nd XTALP pins 1.2 V

Input Low Voltage VIL XTALN and XTALP pins 0.4 V
Other digital inputs 0.8 V
Input Current IIN

RESET and CS pins
Other digital inputs ±10 µA
Input Capacitance CIN 10 pF

DIGITAL INPUTS (5 V TOLERANT)1

DDCA_SCL, DDCA_SDA,

DDCB_SCL, and DDCB_SDA pins
Input High Voltage VIH 2.6 V
Input Low Voltage VIL 0.8 V
Input Current IIN −70 +70 µA

±45 ±60 µA

Output High Voltage VOH 2.4 V
Output Low Voltage VOL 0.4 V
High Impedance Leakage Current I

VS/FIELD/ALSB pin ±35 ±60 µA

LEAK

HPA_A/INT2 and HPA_B pins ±70 µA
Other digital outputs ±10 µA

OUT

POWER REQUIREMENTS

Digital Core Power Supply DVDD 1.71 1.8 1.89 V

PLL Power Supply PVDD 1.71 1.8 1.89 V
Terminator Power Supply TVDD 3.14 3.3 3.46 V
Comparator Power Supply CVDD 1.71 1.8 1.89 V

CURRENT CONSUMPTION See Table 2

Digital Core Power Supply I

Test Condition 1 268 mA

DVDD

Test Condition 2 186 mA
Digital I/O Power Supply I

PLL Power Supply I

Terminator Power Supply I

Test Condition 1 9 mA

DVDDIO

Tes t Condition 1 20 mA

PVDD

Tes t Condition 1 92 mA

TVDD

Test Condition 2 31 mA

Test Condition 2 92 mA
Comparator Power Supply I

Te st Condition 1 187 mA

CVDD

POWER-DOWN CURRENT2 See Table 2, Test Condition 3

DVDD_PD

Digital I/O Power Supply I
PLL Power Supply I
Terminator Power Supply I
Comparator Power Supply I

POWER-UP TIME t

1

Data guaranteed by characterization.

2

Data recorded during lab characterization.

0.034 mA

DVDDIO_PD

PVDD_PD

TVDD_PD

CVDD_PD

25 ms

PWRUP

0.691 mA

0.857 mA

0.053 mA

Rev. B | Page 4 of 24

Data Sheet ADV7619

HDCP Decryption

Off

Table 2. Test Conditions for Current Requirements

Parameter Value Used

TEST CONDITION 1

Number of HDMI Inputs (Xpressview Mode) Two inputs
Xpressview On
Video Format (Each HDMI Input) 4k × 2k
HDCP Decryption Off
Video Pattern (Each HDMI Input) SMPTE
Temperature 20°C
Power Supply Voltages Nominal

TEST CONDITION 2

Number of HDMI Inputs (Xpressview Mode) Two inputs
Xpressview On
Video Format (Each HDMI Input) 1080p60, 36 bits

Video Pattern (Each HDMI Input) SMPTE
Temperature 20°C
Power Supply Voltages Nominal

TEST CONDITION 3 (POWER-DOWN)

Number of HDMI Inputs (Xpressview Mode) N/A
Xpressview N/A
Video Format (Each HDMI Input) N/A
HDCP Decryption N/A
Video Pattern (Each HDMI Input) N/A
Temperature 20°C
Power Supply Voltages Nominal
Other Test Parameters

1

For information about these registers, see the Hardware User Guide for the ADV7619 (UG-237).

Power-Down Mode 0 (IO map, Register 0x0C = 0x62)
Ring oscillator powered down (HDMI map, Register 0x48 = 0x01)
DDC pads powered off (HDMI map, Register 0x73 = 0x03)

1

Rev. B | Page 5 of 24

ADV7619 Data Sheet

DATA AND I2C TIMING CHARACTERISTICS

Table 3.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

CLOCK AND CRYSTAL

Crystal Frequency, XTAL 28.63636 MHz
Crystal Frequency Stability ±50 ppm
LLC Frequency Range 13.5 170 MHz

I2C PORTS

SCL Frequency 400 kHz
SCL Minimum Pulse Width High1 t1 600 ns
SCL Minimum Pulse Width Low1 t2 1.3 μs
Start Condition Hold Time1 t
Start Condition Setup Time1 t
SDA Setup Time1 t
SCL and SDA Rise Time1 t
SCL and SDA Fall Time1 t
Stop Condition Setup Time1 t

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC Mark-Space Ratio1 t

DATA AND CONTROL OUTPUTS

1, 2

Data Output Transition Time t11 End of valid data to negative LLC edge 1.0 ns
t

I2S PORT, MASTER MODE1

SCLK Mark-Space Ratio t15:t16 45:55 55:45 % duty cycle
LRCLK Data Transition Time t17 End of valid data to negative SCLK edge 10 ns
t
I2Sx Data Transition Time t19 End of valid data to negative SCLK edge 5 ns
t

1

Data guaranteed by characterization.

2

DLL bypassed on clock path.

Timing Diagrams

SDA

600 ns

3

600 ns

4

100 ns

5

300 ns

6

300 ns

7

0.6 μs

8

45:55 55:45 % duty cycle

9:t10

Negative LLC edge to start of valid data 0.1 ns

12

Negative SCLK edge to start of valid data 10 ns

18

Negative SCLK edge to start of valid data 5 ns

20

t

3

t

5

t

3

t

t

6

1

SCL

t

2

t

7

Figure 3. I

2

C Timing

t

4

t

8

09580-003

Rev. B | Page 6 of 24

Data Sheet ADV7619

09580-004

t

9

LLC

P0 TO P47, HS ,

VS/FIELD/ALSB, DE

t

11

t

12

t

10

SCLK

LRCLK

I2Sx

LEFT-JUSTIFIED

MODE

I2Sx

RIGHT-JUSTIFIED

MODE

I2Sx

I

2

S MODE

MSB MSB – 1

t

15

t

16

t

17

t

19

t

20

t

18

MSB

MSB – 1

LSBMSB

t

19

t

20

t

19

t

20

NOTES

1. THE LRCLK SIGNAL IS AV AILABLE O N THE AP5 PIN.

2. I2Sx SI GNALS (WHERE x = 0, 1, 2, OR 3) ARE AV AILABLE
ON THE FOLLOW ING PINS: AP 1, AP2, AP3, AND AP 4.

09580-005

Figure 4. Pixel Port and Control SDR Output Timing

Figure 5. I

2

S Timing

Rev. B | Page 7 of 24

ADV7619 Data Sheet

PVDD to GND

2.2 V

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

DVDD to GND 2.2 V

DVDDIO to GND 4.0 V
CVDD to GND 2.2 V
TVDD to GND 4.0 V
Digital Inputs to GND GND − 0.3 V to DVDDIO + 0.3 V
5 V Tolerant Digital Inputs

to GND

1

5.3 V

Digital Outputs to GND GND − 0.3 V to DVDDIO + 0.3 V
XTALP, XTALN −0.3 V to PVDD + 0.3 V
SCL, SDA Data Pins to

DVDDIO − 0.3 V to DVDDIO + 3.6 V

DVDDIO

Maximum Junction

Temperature (T

J MAX

)

125°C

Storage Temperature Range −60°C to +150°C
Infrared Reflow Soldering

260°

(20 sec)

1

The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,

DDCA_SDA, DDCB_SCL, and DDCB_SDA.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the ADV7619, the
user is advised to turn off the unused sections of the part.

Due to PCB metal variation and, therefore, variation in PCB
heat conductivity, the value of θ

may differ for various PCBs.

JA

The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this solution eliminates the variance associated with
the θ

value.

JA

The maximum junction temperature (T

) of 125°C must not

J MAX

be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on the device under
test (DUT):

T

= TS + (ΨJT × W

J

TOTAL

)

where:

T

is the package surface temperature (°C).

S

= 0.22°C/W for the 128-lead TQFP_EP.

Ψ

JT

= ((PVDD × I

W

TOTA L

(CVDD × I

) + (DVDD × I

CVDD

) + (0.2 × TVDD × I

PVDD

) + (DVDDIO × I

DVDD

TVDD

) +

DVDDIO

))

where 0.2 is 20% of the TVDD power that is dissipated on the
part itself.

ESD CAUTION

Rev. B | Page 8 of 24