ANALOG DEVICES ADV7611 Service Manual
Low Power 165 MHz HDMI Receiver
ADV7611
Rev. D
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Fax: 781.461.3113 ©2010-2012 Analog Devices, Inc. All rights reserved.
HS/VS
4
I
2
S
S/PDIF
HDCP
KEYS
TMDS
DDC
HDMI1
DEEP
COLOR
HDMI Rx
ADV7611
COMPONENT
PROCESSOR
36
OUTPUT MUX
FIELD/DE
LLC
DATA
MCLK
SCLK
LRCLK
LRCLK
AP
MCLK
SCLK
OUTPUT MUX
24-BIT
YCbCr/RGB
HS
VS/FIELD
DE
LLC
09305-001
Data Sheet
FEATURES
High-Definition Multimedia Interface (HDMI®) 1.4a features
supported
All mandatory and additional 3D video formats supported
Extended colorimetry, including sYCC601, Adobe RGB,
Adobe YCC 601, xvYCC extended gamut color
CEC 1.4-compatible
HDMI receiver
165 MHz maximum TMDS clock frequency
24-bit output pixel bus
High-bandwidth Digital Content Protection (HDCP) 1.4
support with internal HDCP keys
HDCP repeater support
Up to 127 KSVs supported
Integrated CEC controller
Programmable HDMI equalizer
5 V detect and Hot Plug assert for HDMI port
Audio support
SPDIF (IEC 60958-compatible) digital audio
HDMI audio extraction support
Advanced audio mute feature
General
Interrupt controller with two interrupt outputs
Standard identification (STDI) circuit
Highly flexible 24-bit pixel output interface
Internal EDID RAM
Any-to-any 3 × 3 color space conversion (CSC) matrix
2-layer PCB design supported
64-lead LQFP_EP, 10 mm × 10 mm package
Qualified for automotive applications
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
Projectors
Automotive
Video conferencing
HDTVs
AVR, HTiB
Soundbars
Video switches
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rights of third parti es that may result from its use. Specification s subject to change without notice. No
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ADV7611 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Detailed Functional Block Diagram .......................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 4
Data and I2C Timing Characteristics ......................................... 5
Absolute Maximum Ratings ............................................................ 7
Package Thermal Performance ................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Power Supply Sequencing .............................................................. 10
Power-Up Sequence ................................................................... 10
Power-Down Sequence .............................................................. 10
Functional Overview ...................................................................... 11
HDMI Receiver ........................................................................... 11
Component Processor ............................................................... 11
Other Features ............................................................................ 11
Pixel Input/Output Formatting .................................................... 12
Pixel Data Output Modes Features .......................................... 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
Automotive Products ................................................................. 14
REVISION HISTORY
6/12—Rev. C t o R ev. D
Change to Pin 1 Description, Table 4 ............................................. 8
5/12—Rev. B t o R e v. C
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 3
Added Endnote 3 (Table 1) ............................................................. 4
Deleted TDM Serial Timing Parameter (Table 2) ........................ 5
Deleted Figure 6 ................................................................................ 7
Changed Pin 48 Description (Tab le 4 ) .......................................... 9
Changes to HDMI Receiver and Other Features Sections ........ 11
Added Endnote 1 in Pixel Input/Output Formatting Section and
Endnote 1 to Table 5 ....................................................................... 12
Deleted Time-Division Multiplexed (TDM) Mode Section
and Figure 9 ..................................................................................... 13
Changes to P14 (Table 6) ............................................................... 13
Changes to Ordering Guide .......................................................... 14
Added HDMI Note ......................................................................... 16
6/11—Rev. A to Re v. B
Changes to Figure 7 .......................................................................... 1
5/11—Rev. 0 t o R e v. A
Changes to Features Section............................................................ 1
Changes to Ordering Guide .......................................................... 16
Added Automotive Products Section .......................................... 16
11/10—Revision 0: Initial Version
Rev. D | Page 2 of 16
Data Sheet ADV7611
CONTROL
INTERFACE
I
2
C
CONTROL
AND DATA
PLL
EDID
REPEATER
CONTROLLER
HDCP
ENGINE
PACKET/
INFOFRAME
MEMORY
12
12
12
BACKEND
COLORSPACE
CONVERSION
OUTPUT FORMATTER
COMPONENT
PROCESSOR
5V DETECT
AND HPD
CONTROLLER
AUDIO
PROCESSOR
DATA
PREPROCESOR
AND COLOR
SPACE
CONVERSION
HDMI
PROCESSOR
PACKET
PROCESSOR
A
B
C
MUTE
INTERRUPT
CONTROLLER
(INT1,INT2)
P0 TO P7
*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: S CLK/INT2, MCLK/I NT2, OR HPA_A/ INT2.
XTALP
XTALN
SCL
SDA
CEC
RXA_5V
HPA_A/INT2*
DDCA_SDA
DDCA_SCL
RXA_C±
RXA_0±
RXA_1±
RXA_2±
P8 TO P15
P16 TO P23
LLC
HS
VS/FIELD/ALSB
DE
INT1
INT2*
AP
LRCLK
SCLK/INT2*
MCLK/INT2*
AUDIO OUTPUT FORMATTER
HDCP
EEPROM
SAMPLER
EQUALIZER
DPLL
CEC
CONTROLLER
ADV7611
09305-002
GENERAL DESCRIPTION
The ADV7611 is offered in automotive, professional (no
HDCP), and industrial versions. The operating temperature
o
range is −40
C to +85oC.
The UG-180 contains critical information that must be used in
conjunction with the ADV7611.
The ADV7611 is a high quality, single input HDMI®-capable
receiver. It incorporates an HDMI-capable receiver that
supports all mandatory 3D TV defined in HDMI 1.4a. The
ADV7611 supports formats up to UXGA 60 Hz at 8 bit.
It integrates a CEC controller that supports the capability
discovery and control (CDC) feature.
The ADV7611 has an audio output port for the audio data
extracted from the HDMI stream. The HDMI receiver has an
advanced mute controller that prevents audible extraneous
noise in the audio output.
DETAILED FUNCTIONAL BLOCK DIAGRAM
The following audio formats are accessible:
• A stream from the I
2
S serializer (two audio channels)
• A stream from the S/PDIF serializer (two uncompressed
channels or N compressed channels, for example, AC3)
• DST stream
The HDMI port has dedicated 5 V detect and Hot Plug™ assert
pins. The HDMI receiver also includes an integrated equalizer
that ensures the robust operation of the interface with long cables.
The ADV7611 contains one main component processor (CP),
that processes the video signals from the HDMI receiver. It
provides features such as contrast, brightness and saturation
adjustments, STDI detection block, free run, and synchronization
alignment controls.
Fabricated in an advanced CMOS process, the ADV7611 is
provided in a 10 mm × 10 mm, 64-lead surface-mount LQFP_EP,
RoHS-compliant package and is specified over the −40°C to
+85°C temperature range.
Figure 2. Detailed Functional Block Diagram
Rev. D | Page 3 of 16
ADV7611 Data Sheet
VIH
Other digital inputs
2
V
Output Capacitance
C
20
pF
Digital I/O Power Supply
DVDDIO
3.14
3.3
3.46
V
Comparator Supply Current
I
Power-Down Mode 1
1.3
1.7
mA
SPECIFICATIONS
At DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V,
T
to T
MIN
ELECTRICAL CHARACTERISTICS
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUTS1
Input High Voltage VIH XTALN and XTALP 1.2 V
Input Low Voltage VIL XTALN a nd XTALP 0.4 V
VIL Other digital inputs 0.8 V
Input Current IIN
Other digital inputs ±10 µA
Input Capacitance CIN 10 pF
DIGITAL INPUTS (5 V TOLERANT)1, 2
Input High Voltage VIH 2.6 V
Input Low Voltage VIL 0.8 V
Input Current IIN −82 +82 µA
DIGITAL OUTPUTS1
Output High Voltage VOH 2.4 V
Output Low Voltage VOL 0.4 V
High Impedance Leakage
HPA_A/INT2 pin ±82 µA
Other 10 µA
POWER REQUIREMENTS
Digital Core Power Supply DVDD 1.71 1.8 1.89 V
= −40°C to +85°C, unless otherwise noted.
MAX
I
LEAK
Current
3, 4
OUT
RESET pin
±45 ±60 µA
VS/FIELD/ALSB pin ±35 ±60 µA
PLL Power Supply PVDD 1.71 1.8 1.89 V
Terminator Power Supply TVDD 3.14 3.3 3.46 V
Comparator Power Supply CVDD 1.71 1.8 1.89 V
Digital Core Supply Current I
Digital I/O Supply Current I
PLL Supply Current I
Terminator Supply Current I
Comparator Supply Current I
UXGA 60 Hz at 8 bit 95.7 188.1 mA
DVDD
UXGA 60 Hz at 8 bit 12.9 178.5 mA
DVDDIO
UXGA 60 Hz at 8 bit 30.7 36.9 mA
PVDD
UXGA 60 Hz at 8 bit 50.9 57.6 mA
TVDD
UXGA 60 Hz at 8 bit 95.8 114.4 mA
CVDD
POWER-DOWN CURRENTS3, 5
Digital Core Supply Current I
Digital I/O Supply Current I
PLL Supply Current I
Terminator Supply Current I
Power-Up Time t
1
Data guaranteed by characterization.
2
The following pins are 5 V tolerant: DDCA_SCL, DDC_SDA, and RXA_5V.
3
Data recorded during lab characterization.
4
Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature.
5
Power-Down Mode 0 (IO map, Register 0x0C = 0x62), ring oscillator powered down (HDMI map, Register 0x48 = 0x01), and DDC pads off (HDMI map, Register 0x73 =
0x01).
Power-Down Mode 1 0.2 0.5 mA
DVDD_PD
DVDDIO_PD
Power-Down Mode 1 1.5 1.8 mA
PVDD_PD
Power-Down Mode 1 0.1 0.3 mA
TVDD_PD
CVDD_PD
25 ms
PWRUP
Power-Down Mode 1 1.3 1.7 mA
Rev. D | Page 4 of 16
Data Sheet ADV7611
DATA AND I2C TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CLOCK AND CRYSTAL
Crystal Frequency, XTALP 28.63636 MHz
Crystal Frequency Stability ±50 ppm
LLC Frequency Range1 13.5 165 MHz
I2C PORTS
RESET FEATURE
CLOCK OUTPUTS
DATA AND CONTROL OUTPUTS3
I2S PORT, MASTER MODE
1
Maximum LLC frequency is limited by the clock frequency of UXGA 60 Hz at 8 bit.
2
Data guaranteed by characterization.
3
With the DLL block on output clock bypassed.
4
DLL bypassed on clock path.
5 I2
SCL Frequency 400 kHz
SCL Minimum Pulse Width High2 t
SCL Minimum Pulse Width Low2
Start Condition Hold Time2
Start Condition Setup Time2
SDA Setup Time2
SCL and SDA Rise Time2
SCL and SDA Fall Time2
Stop Condition Setup Time2
600 ns
1
1.3 μs
t
2
600 ns
t
3
600 ns
t
4
100 ns
t
5
300 ns
t
6
300 ns
t
7
0.6 μs
t
8
Reset Pulse Width 5 ms
45:55 55:45 % duty
LLC Mark-Space Ratio2
t
9:t10
cycle
Data Output Transition Time
2, 4
t
SCLK Mark-Space Ratio2
End of valid data to negative clock edge 1.0 2.2 ns
t
11
Negative clock edge to start of valid data 0.0 0.3 ns
12
45:55 55:45 % duty
t
15:t16
cycle
End of valid data to negative SCLK edge 10 ns
LRCLK Data Transition Time2
LRCLK Data Transition Time2
I2S Data Transition Time
I2S Data Transition Time
S is accessible via the AP pin.
2, 5
2, 5
t
17
Negative SCLK edge to start of valid data 10 ns
t
18
t
19
Negative SCLK edge to start of valid data 5 ns
t
20
End of valid data to negative SCLK edge 5 ns
Rev. D | Page 5 of 16
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