ANALOG DEVICES ADV7441A Service Manual

10-Bit Integrated, Multiformat SDTV/HDTV Video Decoder,

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RGB Graphics Digitizer, and 2:1 Multiplexed

HDMI/DVI Interface

FEATURES

Multiformat decoder

Four 10-bit analog-to-digital converters (ADCs) ADC sampling rates up to 170 MHz Mux with 12 analog input channels SCART fast blank sampling support NTSC/PAL/SECAM color standards support 525p-/625p-component progressive scan formats support 720p-/1080i-/1080p-component HD formats support Digitizes RGB graphics from VGA to UXGA rates

(up to 1600 × 1200 @ 60 Hz) VBI data slicer (including teletext) Analog-to-HDMI fast switching mode

Dual High-Definition Multimedia Interface (HDMI) Rx

2:1 multiplexed HDMI receiver HDMI 1.3, DVI 1.0 225 MHz HDMI receiver Repeater support High-bandwidth digital content protection (HDCP 1.3) 36-bit deep color support S/PDIF (IEC60958-compatible) digital audio output Multichannel I Adaptive equalizer for cable lengths up to 30 meters Internal EDID RAM

General

Highly flexible output interface STDI function support standard identification 2 any-to-any 3 × 3 color-space conversion matrices Programmable interrupt request output pins

APPLICATIONS

Advanced TVs

PDP HDTVs LCD TVs (HDTV ready) LCD/DLP® rear projection HDTVs CRT HDTVs LCoS® HDTVs

Audio/video receivers (AVR) LCD/DLP front projectors HDTV STBs with PVR DVD recorders with progressive scan input support

2

S audio output (up to 8 channels)

ADV7441A

GENERAL DESCRIPTION

The ADV7441A is a high quality multiformat video decoder and graphics digitizer with an integrated 2:1 multiplexed HDMI™ receiver.

The ADV7441A contains two main processing sections. The first section is the standard definition processor (SDP), which processes all types of PAL, NTSC, and SECAM signals. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The ADV7441A can keep the HDCP link between a HDMI source and the selected HDMI port active in analog mode operation. This allows for fast switching between the analog and HDMI modes.

As a decoder, the ADV7441A can convert PAL, NTSC, and SECAM composite or S-Video signals into a digital ITU-R BT.656 format. It can also decode a component RGB or YPrPb video signal into a digital YCrCb or RGB pixel output stream. The ADV7441A supports the 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i component video standards as well as many other HD and SMPTE standards. SCART and overlay functionality are enabled by the ability of the ADV7441A to process CVBS and standard definition RGB signals simultaneously. As a graphics digitizer, the ADV7441A can digitize RGB graphics signals from VGA to UXGA rates and convert them to a digital RGB or YCrCb pixel output stream.

The ADV7441A incorporates a dual-input HDMI 1.3-compatible receiver that supports HDTV formats up to 1080p and display resolutions up to UXGA. The reception of encrypted video is possible with the inclusion of HDCP. The inclusion of adaptive equalization in the HDMI receiver ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has advanced audio functionality, including a mute controller that prevents audible extraneous noise in the audio output.

To facilitate professional applications, where HDCP processing and decryption is not required, a derivative part of the ADV7441A is available. This allows users who are not HDCP adopters to purchase the ADV7441A. See the Ordering Guide for details.

Fabricated using an advanced CMOS process, the ADV7441A is available in a space-saving, 144-lead, surface-mount, RoHScompliant, plastic LQFP and is specified over the −40°C to +85°C temperature range.

Rev.

B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other rights of third parties that may result from its use. Specifications subject to chan ge without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

7/08—Rev. SpA to Rev. B

5/08—Rev. Sp0 to Rev. SpA

Changes to General Description Section ...................................... 1

Change to Clamp Level (When Locked) Parameter, Table 3 ...... 7

Changes to Standard Definition Processor Pixel Data Output

Modes Section ................................................................................. 14

Changes to Component Processor Pixel Data Output

Modes Section ................................................................................. 14

Changes to Table 8 .......................................................................... 18

Added Table 9 .................................................................................. 18

Added Table 10 ............................................................................... 19

Added Table 11 ............................................................................... 20

Added AD9388A/ADV7441A Evaluation System Section ....... 25

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 26

10/07—Revision Sp0: Initial Version

Rev. B | Page 2 of 28

ADV7441A

A

0

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FUNCTIONAL BLOCK DIAGRAM

DATA

PIXEL

P0 TO P9

10

DATA

ANCILLARY

DATA

ANCILLARY

FORMATTER

VBI DATA PROCESSOR

VBI

DECODER

COMPONENT PROCESSOR

DIGITAL PROCESSING BLOCK

SYNC EXTRACT

AV

STANDARD

AND

SYNC SOURCE

CODE

IDENTIFICATION

POLARITY DET ECT

INSERTION

OFFSET

ADDRESS

AND

GAIN

®

CONTROL

CGMS DETECT ION

FINE

MACROVISIO N

DIGITIAL

DELAY

PROGRAM

6914-001

P10 TO P19

P20 TO P29

10

GBR

HSYNC DEPTH

ACTIVE PEAK AND

CLAMP

NOISE AND

CALIBRATION

FB

INT1

OUTPUT FORMATTE R

LUMA

2D COMB

RE-

LUMA

GAIN

CONTRO L

STANDARD DEFINITION PROCESSOR

LUMA

FILTER

HS/CS

VS/FIELD

DE/FIELD

AV

(0x04 MAX)

SAMPLE

CODE

INSERTION

RE-

SAMPLE

CONTROL

LINE

LENGTH

PREDICTOR

LLC

SFL/

SYNC_OUT/

INT2

FAST BLANK OVERLAY CONTROL

CTI

C-DNR

CHROMA

2D COMB

(0x04 MAX)

RE-

SAMPLE

CHROMA

FREE RUN

SYNTHESIZED

GAIN

CHROMA

LLC CONTRO L

CONTRO L

FILTER

OUTPUT CONTROL

S

2

LRCLK

SCLK

I

GLOBAL

CONTRO L

STANDARD

AUTODETECTION

SPDIF

MCLKOUT

FINE

CHA

CHB

COLOR SPACE

CHC

FILTERS

CONVERT ER

CHD

10

ADC3

CLAMP

CY

DOWNSAMPLING

DECIMATION AND

CONTROL

HS/CS, VS

LLC

GENERATION

AND CLOCK

GENERATION

SYNC PROCESSING

SYNC

DATA

EMBEDDED

PROCESSOR

CHA

CHB

CHC

10

ADC2

ADC1

ADC0

CLAMP

ANALOG INTERFACE

INPUT

MATRIX

LUMA

DIGITAL

MUX

CONTROL AND DATA

SYNC

CLAMP

CONTROL

C

2

I

CONTROL

INTERFACE

EXTRACT

FILTER

FSC

RECOVERY

SAMPLER

DEMOD

CHROMA

VBI DATA

RECOVERY

DETECTION

MACROVISION

FINE

CLAMP

DIGITAL

CHROMA

CONVERSION 4:2:2 TO 4: 4:4

PACKET

XOR

VS

HS

DE

HDMI DECODE

ALIGNMENT

DATA RECOVERY

MUX

PLL

SAMPLER

EQUALIZER

MUX

EEPROM

HDCP

ENGINE

HDCP

CONTRO LLER

EQUALIZER

AUDIO

PROCESSING

PACKET/

MEMORY

INFOFRAME

PROCESSOR

MCL

MDA

DDCB_SCL

EDID/REPEATER

DDCB_SD DDCA_SD DDCA_SCL

CVBS

SOY

RGB

YPrPb

CVBS

YC AND

SOG

VS_IN

HS_IN/CS_IN

FB

SCL

SDA

ALSB

Figure 1.

Rev. B | Page 3 of 28

RXA_0

RXA_1

RXA_2

RXB_0

RXB_1

RXA_C

RXB_C

RXB_2

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

STATIC PERFORMANCE

1

2

Symbol Test Conditions Min Typ Max Unit

Resolution (Each ADC) N 10 Bits Integral Nonlinearity INL BSL 27 MHz (@ a 10-bit level) −0.5/+2 −4/+6 LSB BSL 54 MHz (@ a 10-bit level) −0.5/+2 LSB BSL 74 MHz (@ a 10-bit level) −0.5/+1.5 LSB BSL 110 MHz (@ a 10-bit level) −0.7/+2 LSB BSL 170 MHz (@ an 8-bit level) −0.25/+0.5 LSB Differential Nonlinearity DNL At 27 MHz (@ a 10-bit level) −0.5/+0.5 −0.95/+2 LSB At 54 MHz (@ a 10-bit level) ±0.5 LSB At 74 MHz (@ a 10-bit level) ±0.5 LSB At 110 MHz (@ a 10-bit level) ±0.5 LSB At 170 MHz (@ an 8-bit level) −0.25/+0.2 LSB

DIGITAL INPUTS

Input High Voltage

3

V

2 V

IH

HS_IN/CS_IN, VS_IN low trigger mode 0.7 V Input Low Voltage

3

V

0.8 V

IL

HS_IN/CS_IN, VS_IN low trigger mode 0.3 V Input Current IIN

Pin 21 (RESET

)

−60 +60 μA

All input pins other than Pin 21 −10 +10 μA Input Capacitance

4

CIN 10 pF

DIGITAL OUTPUTS

Output High Voltage Output Low Voltage High Impedance Leakage Current I Output Capacitance

POWER REQUIREMENTS

5

V

4

C

4

VOH I

I

OL

10 μA

LEAK

20 pF

OUT

= 0.4 mA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

Digital Core Power Supply DVDD 1.62 1.8 1.98 V Digital I/O Power Supply DVDDIO 2.97 3.3 3.63 V PLL Power Supply PVDD 1.71 1.8 1.89 V Analog Power Supply AVDD 1.71 1.8 1.89 V Terminator Power Supply TVDD 3.135 3.3 3.465 V Comparator Power Supply CVDD 1.71 1.8 1.89 V Digital Core Supply Current I

CVBS input sampling @ 54 MHz

DVDD

Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Digital I/O Supply Current I

CVBS input sampling @ 54 MHz

DVDDIO

Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz

6

141 252 mA

7, 8

242 329 mA

7, 8

6

7, 8

20 34 mA

140 189 mA

6

152 205 mA

6

203 263 mA

242 326 mA 16 48 mA 17 37 mA

6

16 50 mA

6

42 61 mA 17 34 mA

Rev. B | Page 4 of 28

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Parameter

HDMI Comparators I TMDS PLL and Equalizer Graphics RGB sampling @ 108 MHz Supply Current SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Analog Supply Current Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Terminator Supply Current I Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Audio and Video PLL Supply Current I Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Power-Down Current I Power-Up Time t

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

All ADC linearity tests were performed at input range full scale − 12.5% and at zero scale + 12.5%.

3

Pin 1, Pin 105, Pin 106, and Pin 144 are 5 V tolerant.

4

Guaranteed by characterization.

5

The VOH and VOL levels were obtained using the default drive strength value (0x15) in User Map Register 0xF4.

6

Current measurements for analog inputs were made with HDMI/analog simultaneous mode disabled (User Map Register 0xBA, Bit 7 programmed with Value 0) and

with no HDMI sources connected to the part.

7

Current measurements for HDMI inputs were made with a source connected to the active HDMI port and with no source connected to the inactive HDMI port.

8

Audio stream is a noncompressed stereo audio sampling frequency of fS = 48 kHz, and MCLKOUT = 256 fS.

9

Analog current measurements for CVBS were made with only ADC0 powered up; for RGB, with only ADC0, ADC1, and ADC2 powered up; for SCART FB, with all ADCs

powered up; and for HDMI mode, with all ADCs powered off.

10

The terminator supply current may vary with the HDMI source in use.

1

9

Symbol Test Conditions Min Typ Max Unit

6

CVBS input sampling @ 54 MHz

CVDD

I

CVBS input sampling @ 54 MHz

AVDD

CVBS input sampling @ 54 MHz

TVDD

CVBS input sampling @ 54 MHz

PVDD

11.6 mA

PWRDN

25 ms

PWRUP

6

7, 8

86 105 mA

7, 8

6

63 102 mA

6

174 278 mA

7, 8

6

12 18 mA

6

12 18 mA

7, 8, 10

6

7, 8

to T

MIN

56 78 mA 56 78 mA

6

56 79 mA

6

56 79 mA

95 118 mA

6

225 348 mA

6

180 284 mA 0 2 mA 0 2 mA

6

12 18 mA

6

12 18 mA 42 47 mA 63 69 mA 18 23 mA 14 21 mA

6

17 23 mA

6

19 24 mA 10 19 mA 15 20 mA

).

MAX

Rev. B | Page 5 of 28

ADV7441A

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VIDEO SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 2.

1, 2

Parameter

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulated in five steps 0.3 Degrees Differential Gain DG CVBS input, modulated in five steps 0.6 % Luma Nonlinearity LNL CVBS input, five steps 0.8 %

NOISE SPECIFICATIONS

SNR Unweighted Luma flat field 63.1 dB

Analog Front-End Crosstalk

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 % Vertical Lock Range 40 70 Hz FSC Subcarrier Lock Range ±1.3 kHz Color Lock-In Time 60 Lines Synchronization Depth Range Color Burst Range 5 200 % Vertical Lock Time 2 Fields Horizontal Lock Time 100 Lines

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 Degrees Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error

Chroma Luma Intermodulation

LUMA SPECIFICATIONS

Luma Brightness Accuracy Luma Contrast Accuracy

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

Guaranteed by characterization.

3

Nominal synchronization depth is 300 mV at 100% of the synchronization depth range.

3

Symbol Test Conditions Min Typ Max Unit

20 200 %

Luma ramp 61.8

0.1 Degrees

0.3 %

CVBS, 0.5 V input 1 % CVBS, 0.5 V input 1 %

to T

).

MIN

MAX

60 dB

dB

Rev. B | Page 6 of 28

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ANALOG AND HDMI SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 3.

1, 2

Parameter

Test Conditions Min Typ Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance (Except Pin 74) Clamps switched off 10 MΩ Input Impedance of Pin 74 20 kΩ Common-Mode Level (CML) 0.88 V ADC Full-Scale Level CML + 0.5 V ADC Zero-Scale Level CML − 0.5 V ADC Dynamic Range 1 V

Clamp Level (When Locked) CVBS input CML – 0.122 V SCART RGB input (R, G, B signals) CML – 0.167 V S-Video input (Y signal) CML– 0.122 V S-Video input (C signal) CML V Component input (Y signal) CML − 0.120 V Component input (Pr signal) CML V Component input (Pb signal) CML V PC RGB input (R, G, B signals) CML − 0.120 V

Large Clamp Source Current SDP only 8 mA

Large Clamp Sink Current SDP only 8 mA

Fine Clamp Source Current SDP only 0.25 μA

Fine Clamp Sink Current SDP only 0.4 μA HDMI SPECIFICATIONS

Intrapair (Positive-to-Negative) Differential

3

0.4 t

Input Skew

Channel-to-Channel Differential Input Skew 0.2 t

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

Guaranteed by characterization.

3

Guaranteed by design.

4

t

is 1/10 the pixel period t

bit

5

t

is the period of the TMDS clock.

pixel

.

to T

MAX

).

MIN

5

+ 1.78 ns

pixel

4

bit

Rev. B | Page 7 of 28

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TIMING CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 4.

Parameter

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency 28.6363 MHz Crystal Frequency Stability ±50 ppm Horizontal Sync Input Frequency 14.8 110 kHz LLC Frequency Range 12.825 170 MHz

I2C PORTS (FAST MODE)

xCL Frequency xCL Minimum Pulse Width High xCL Minimum Pulse Width Low Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs xDA Setup Time xCL and xDA Rise Times xCL and xDA Fall Times Setup Time for Stop Condition t8 0.6 μs

I2C PORTS (NORMAL MODE)

xCL Frequency xCL Minimum Pulse Width High xCL Minimum Pulse Width Low Hold Time (Start Condition) t3 4 μs Setup Time (Start Condition) t4 4.7 μs xDA Setup Time xCL and xDA Rise Times xCL and xDA Fall Times Setup Time for Stop Condition t8 4 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC Mark Space Ratio t9:t10 45:55 55:45 % duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transition Time SDR (SDP)5t11 Negative clock edge to start of valid data 3.4 ns t Data Output Transition Time SDR (CP)6t13 End of valid data to negative clock edge 2 ns t

I2S PORT (MASTER MODE)

SCLK Mark Space Ratio t15:t16 45:55 55:45 % duty cycle LRCLK Data Transition Time t17 End of valid data to negative SCLK edge 10 ns t I2Sx Data Transition Time t MCLKOUT Frequency 4.096 24.576 MHz

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

Guaranteed by characterization.

3

Refers to all I2C pins (DDC and control port).

4

The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S.

5

SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4.

6

CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4.

7

The suffix x refers to pin names ending with 0, 1, 2, and 3.

1, 2

3

4

t

4

t

4

t

4

t

3

4

100 kHz

4

t

4

t

4

t

4

t

4

t

7

Symbol Test Conditions Min Typ Max Unit

400 kHz

0.6 μs

1

1.3 μs

2

100 ns

5

t6 300 ns

300 ns

7

4 μs

1

4.7 μs

2

250 ns

5

1000 ns

6

300 ns

7

End of valid data to negative clock edge 2.4 ns

12

Negative clock edge to start of valid data 0.5 ns

14

Negative SCLK edge to start of valid data 10 ns

18

t

19

Negative SCLK edge to start of valid data 5 ns

20

End of valid data to negative SCLK edge 5 ns

to T

).

MIN

MAX

Rev. B | Page 8 of 28

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TIMING DIAGRAMS

Figure 2. I

t

5

2

C Timing

t

3

xDA

t

6

1

xCL

t

2

NOTES

1. THE PREF IX x REFERS T O PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S.

t

7

t

3

t

4

t

8

06914-002

LLC

P0 TO P29, VS,

HS, DE/FIELD,

FL/SYNC_OUT

t

9

t

12

t

10

t

11

06914-003

Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)

LLC

P0 TO P29, VS,

HS, DE/FI ELD

t

9

t

13

Figure 4. Pixel Port and Control SDR Output Timing (CP Core)

t

10

t

14

06914-004

t

15

SCLK

t

16

t

17

LRCLK

t

18

t

19

MSB MSB – 1

t

20

MSB

t

19

MSB – 1

t

20

2

Figure 5. I

S Timing

Rev. B | Page 9 of 28

t

19

LSBMSB

t

20

06914-007

2

I

S MODE

I2Sx

MODE

I2Sx

MODE

LEFT-JUSTIFIED

RIGHT-JUSTIFIED

NOTES

1. THE SUFF IX x REFE RS TO PI N NAMES ENDING WITH 0, 1, 2, AND 3.

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ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

AVDD to AGND 2.2 V DVDD to DGND 2.2 V PVDD to PGND 2.2 V DVDDIO to DGND 4 V CVDD to CGND 2.2 V TVDD to TGND 4 V DVDDIO to AVDD −0.3 V to +3.6 V DVDDIO to TVDD −3.6 V to +3.6 V DVDDIO to DVDD −2 V to +2 V CVDD to DVDD −2 V to +0.3 V PVDD to DVDD −2 V to +0.3 V AVDD to CVDD −2 V to +2 V AVDD to PVDD −2 V to +2 V AVDD to DVDD −2 V to +0.3 V AVDD to TVDD −3.6 V to +0.3 V TVDD to DVDD −2 V to +2 V Digital Inputs

Voltage to DGND DGND − 0.3 V to DVDDIO + 0.3 V

Digital Outputs

Voltage to DGND DGND − 0.3 V to DVDDIO + 0.3 V

Analog Inputs

Voltage to AGND AGND − 0.3 V to AVDD + 0.3 V

Maximum Junction

Temperature (T Storage Temperature Range −65°C to +150°C Infrared Reflow,

Soldering (20 sec)

J_MAX

)

125°C

260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Table 6.

Package Type Ψ

144-Lead LQFP (ST-144) 1.62 °C/W

1

Junction-to-package surface thermal resistance.

1

Unit

JT

PACKAGE THERMAL PERFORMANCE

To reduce power consumption during ADV7441A operation, turn off unused ADCs.

On a four-layer PCB that includes a solid ground plane, the value of θ PCB metal and, therefore, variations in PCB heat conductivity, the value of θ

The most efficient measurement technique is to use the surface temperature of the package to estimate the die temperature, because this is not affected by the variance associated with the value of θ

The maximum junction temperature (T be exceeded. The following equation calculates the junction temperature using the measured surface temperature of the package and applies only when no heat sink is used on DUT:

where:

T

is the surface temperature of the package expressed in degrees

S

Celsius.

Ψ

JT

W

TOTAL

(DVDDIO × IDVDDIO) + (PVDD × IPVDD) + (CVDD × ICVDD) + (TVDD × ITVDD)}.

Contact an Analog Devices, Inc., sales representative or send an e-mail to video.products@analog.com for more information on package thermal performance.

is 25.3°C/W. However, due to variations within the

JA

may differ for various PCBs.

JA

.

JA

) of 125°C must not

J_MAX

T

= TS + (ΨJT × W

J_MAX

TOTAL

)

is the junction-to-package surface thermal resistance.

= {(AV D D × IAVDD) + (DVDD × IDVDD) +

ESD CAUTION

Rev. B | Page 10 of 28

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVDD

CGND

TVDD

RXA_CN

RXA_CP

TGND

RXA_0N

RXA_0P

TGND

RXA_1N

RXA_1P

TGND

RXA_2N

RXA_2P

TVDD

RTERM

CVDD

CGND

TVDD

RXB_CN

RXB_CP

TGND

RXB_0N

RXB_0P

TGND

RXB_1N

RXB_1P

TGND

RXB_2N

RXB_2P

TVDD

CGND

CVDD

DVDD

DGND

DDCB_SCL

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

DDCB_SDA

SPDIF

I2S0 I2S1 I2S2 I2S3

LRCLK

SCLK

MCLKOUT

EXT_CLAMP

SDA

SCL

ALSB

DGND

DVDDIO

DE/FIELD

HS/CS

VS/FIELD

FL/SYNC_OUT/INT2

INT1

RESET

DGND

DVDD

DGND

DVDDIO

P10

1

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P0

25

P1

26

P2

27

P3

28

P4

29

P5

30

P6

31

P7

32

P8

33

P9

34

35

36

37

48

49

50

ADV7441A

TOP VIEW

(Not to Scale)

51

52

56

57

58

62

63

64

65

66

67

68

69

108

TEST5

107

TEST4

106

DDCA_SDA

105

DDCA_SCL

104

CVDD

103

CGND

102

AUDIO_ELPF

101

PVDD

100

PGND

99

AIN6

98

AIN12

97

SOY

96

AIN5

95

AIN11

94

AIN4

93

AIN10

92

REFP

91

TEST3

90

REFN

89

TEST2

88

AVDD

87

AGND

86

CML

85

REFOUT

84

AVDD

83

AGND

82

AGND

81

AIN3

80

AIN9

79

AIN2

78

AIN8

77

AIN1

76

AIN7

75

SOG

74

FB

73

TEST0

70

71

72

P1138P1239P1340P1441P1542P1643P1744P1845P1946P2047P21

EXT_CLK

DGND

LLC

DVDDIO

P2253P2354P2455P25

DGND

DVDD

P2659P2760P2861P29

VS_IN

XTAL

DGND

XTAL1

HS_IN/CS_IN

ELPF

PVDD

PGND

DVDDIO

PGND

Figure 6. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type1Description

14, 22, 34, 49, 56,

DGND G Digital Ground.

64, 143 82, 83, 87 AGND G Analog Ground. 69, 72, 100 PGND G PLL Ground. 103, 110, 126, 140 CGND G Comparator Ground. 114, 117, 120,

TGND G Terminator Ground.

130, 133, 136 15, 35, 50, 67 DVDDIO P Digital I/O Supply Voltage (3.3 V). 23, 57, 142 DVDD P Digital Core Supply Voltage (1.8 V). 84, 88 AVDD P Analog Supply Voltage (1.8 V). 68, 71, 101 PVDD P Audio and Video PLL Supply Voltage (1.8 V). 104, 109, 125, 141 CVDD P HDMI Comparator, TMDS PLL, and Equalizer Supply Voltage (1.8 V). 111, 123, 127, 139 TVDD P Terminator Supply Voltage (3.3 V). 74 FB I Fast Blank. Fast switch overlay between CVBS and RGB analog signals. 73, 91, 108 TEST0, TEST3, TEST5 I Test Pins. Do not connect. 89 TEST2 O Test Pin. Do not connect.

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Pin No. Mnemonic Type1Description

107 TEST4 I/O Test Pin. Do not connect. 76 to 81, 93 to 96,

98, 99 24 to 33, 36 to 47,

52 to 55, 58 to 61 19 INT1 O

20 SFL/SYNC_OUT/INT2 O

17 HS/CS O Horizontal Synchronization Output Signal (HS). Output by the SDP and CP.

18 VS/FIELD O Vertical Synchronization Output Signal (VS). Output by the SDP and CP.

16 DE/FIELD O Data Enable Signal (DE). Indicates active pixel data.

11 SDA I/O I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. 12 SCL I

13 ALSB I This pin sets the second LSB of the slave address for each ADV7441A register map. 21

51 LLC O Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz. 65 XTAL1 O

66 XTAL I

70 ELPF O The recommended external loop filter must be connected to this ELPF pin. 102 AUDIO_ELPF O The recommended external loop filter must be connected to this AUDIO_ELPF pin. 85 REFOUT O Internal Voltage Reference Output. 86 CML O Common-Mode Level for the Internal ADCs. 90 REFN O Internal Voltage Reference Output. 92 REFP O Internal Voltage Reference Output. 63 HS_IN/CS_IN I

62 VS_IN I

75 SOG I Synchronization-on-Green Input. This pin is used in embedded synchronization mode. 97 SOY I Synchronization-on-Luma Input. This pin is used in embedded synchronization mode. 112 RXA_CN I Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_CP I Digital Input Clock True of Port A in the HDMI Interface. 115 RXA_0N I Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0P I Digital Input Channel 0 True of Port A in the HDMI Interface. 118 RXA_1N I Digital Input Channel 1 Complement of Port A in the HDMI Interface. 119 RXA_1P I Digital Input Channel 1 True of Port A in the HDMI Interface. 121 RXA_2N I Digital Input Channel 2 Complement of Port A in the HDMI Interface. 122 RXA_2P I Digital Input Channel 2 True of Port A in the HDMI Interface.

AIN1 to AIN12 I Analog Video Input Channels.

P0 to P29 O Video Pixel Output Port.

Interrupt Signal. Can be active low or active high. The set of events that triggers an interrupt is under user control.

Subcarrier Frequency Lock (SFL). Contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.

Sliced Synchronization Output Signal (SYNC_OUT). Available only in CP mode. Interrupt Signal (INT2).

Composite Synchronization (CS). A single signal containing both horizontal and vertical synchronization pulses.

Field Synchronization Output Signal (FIELD). Field synchronization output signal in all interlaced video modes.

2

C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for

I the control port.

RESET

I

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7441A circuitry.

This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In crystal mode, the crystal must be a fundamental crystal.

Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V

28.63636 MHz clock oscillator source to clock the ADV7441A.

HS Input Signal. Used in analog mode for 5-wire timing mode. CS Input Signal. Used in analog mode for 4-wire timing mode. For optimal performance, a 100 Ω series resistor is recommended on the HS_IN/CS_IN pin.

VS Input Signal. Used in analog mode for 5-wire timing mode. For optimal performance, a 100 Ω series resistor is recommended on the VS_IN pin.

Rev. B | Page 12 of 28

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Pin No. Mnemonic Type1Description

128 RXB_CN I Digital Input Clock Complement of Port B in the HDMI Interface. 129 RXB_CP I Digital Input Clock True of Port B in the HDMI Interface. 131 RXB_0N I Digital Input Channel 0 Complement of Port B in the HDMI Interface. 132 RXB_0P I Digital Input Channel 0 True of Port B in the HDMI Interface. 134 RXB_1N I Digital Input Channel 1 Complement of Port B in the HDMI Interface. 135 RXB_1P I Digital Input Channel 1 True of Port B in the HDMI Interface. 137 RXB_2N I Digital Input Channel 2 Complement of Port B in the HDMI Interface. 138 RXB_2P I Digital Input Channel 2 True of Port B in the HDMI Interface. 106 DDCA_SDA I/O HDCP Slave Serial Data Port A. 1 DDCB_SDA I/O HDCP Slave Serial Data Port B. 105 DDCA_SCL I HDCP Slave Serial Clock Port A. 144 DDCB_SCL I HDCP Slave Serial Clock Port B. 2 SPDIF O SPDIF Digital Audio Output. 3 I2S0 O I2S Audio (Channel 1 and Channel 2). 4 I2S1 O I2S Audio (Channel 3 and Channel 4). 5 I2S2 O I2S Audio (Channel 5 and Channel 6). 6 I2S3 O I2S Audio (Channel 7 and Channel 8). 7 LRCLK O Data Output Clock for Left and Right Audio Channels. 8 SCLK O Audio Serial Clock Output. 9 MCLKOUT O Audio Master Clock Output. 10 EXT_CLAMP I

48 EXT_CLK I

124 RTERM I Sets internal termination resistance. Connect this pin to TGND using a 500 Ω resistor.

1

G = ground, P = power, I = input, O = output.

External Clamp Signal Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A.

Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A.

Rev. B | Page 13 of 28

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FUNCTIONAL OVERVIEW

The following overview provides a brief description of the functionality of the ADV7441A. More details are available in the Theory of Operation section.

ANALOG FRONT END

The analog front end of the ADV7441A provides four high quality 10-bit ADCs to enable 10-bit video decoding, a multiplexer with 12 analog input channels to enable multisource connection without the requirement of an external multiplexer, and four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal. SCART functionality and standard definition RGB overlay with CVBS are controlled by the FB input.

HDMI RECEIVER

The ADV7441A is compatible with the HDMI 1.3 specification. The ADV7441A supports all HDTV formats up to 1080p and all display resolutions up to UXGA (1600 × 1200 @ 60 Hz).

The device includes the following features:

• Adaptive front-end equalization for HDMI operation with

cable lengths up to 30 meters.

• Synchronization conditioning for higher performance in

strenuous conditions.

• Audio mute for removing extraneous noise.

• Programmable data island packet interrupt generator.

STANDARD DEFINITION PROCESSOR PIXEL DATA OUTPUT MODES

The ADV7441A features the following SDP output modes:

• 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time

codes and/or HS, VS, and FIELD.

• 16-/20-bit YCrCb 4:2:2 with embedded time codes and/or

HS, VS, and FIELD.

• 24-/30-bit YCrCb 4:4:4 with embedded time codes and/or

HS, VS, and FIELD.

COMPOSITE AND S-VIDEO PROCESSING

The ADV7441A supports NTSC (M/J/4.43), PAL (B/D/I/G/H/ M/N/Nc/60), and SECAM (B/D/G/K/L) standards for CVBS and S-Video formats. Superadaptive 2D, 5-line comb filters for NTSC and PAL provide superior chrominance and luminance separation for composite video.

The composite and S-Video processing functionality also includes fully automatic detection of switching among worldwide standards (PAL/NTSC/SECAM); automatic gain control (AGC) with white peak mode to ensure that the video is processed without compromising the video processing range; Adaptive Digital Line Length Tracking (ADLLT™); and proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners. The IF filter block compensates for high frequency luma attenuation due to the tuner SAW filter.

Other features include chroma transient improvement (CTI); luminance digital noise reduction (DNR); color controls for hue, brightness, saturation, contrast; Cr and Cb offset controls; certified Macrovision copy protection detection on composite and S-Video for all worldwide formats (PAL/NTSC/SECAM); 4× oversampling (54 MHz) for CVBS, S-Video, and YUV modes; line-locked clock output (LLC); support for letterbox detection; a free-run output mode for stable timing when no video input is present; a vertical blanking interval data processor; teletext; a video programming system (VPS); vertical interval time codes (VITC); closed captioning (CC) and extended data service (EDS); wide-screen signaling (WSS); a copy generation management system (CGMS); clocking from a single 28.63636 MHz crystal; and subcarrier frequency lock (SFL) output for downstream video encoders.

The differential gain of the ADV7441A is 0.6% typical, and differential phase is 0.3° typical.

COMPONENT PROCESSOR PIXEL DATA OUTPUT MODES

The ADV7441A features single data rate outputs as follows:

• 8-/10-bit 4:2:2 YCrCb for 525i and 625i.

• 16-/20-bit 4:2:2 YCrCb for all standards.

• 24-/30-bit 4:4:4 YCrCb/RGB for all standards.

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COMPONENT VIDEO PROCESSING

The ADV7441A supports 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats; automatic adjustments for gain (contrast) and offset (brightness); manual adjustment controls; analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, and CS; and YCrCb-to-RGB and RGB-to-YCrCb conversions by any-toany, 3 × 3, color-space conversion matrices.

In addition, the ADV7441A features brightness, saturation, and hue controls. Standard identification (STDI) enables detection of the component format at the system level, and a synchronization source polarity detector (SSPD) determines the source and polarity of the synchronization signals that accompany the input video.

Certified Macrovision copy protection detection is available on component formats (525i, 625i, 525p, and 625p).

When no video input is present, free-run output mode provides stable timing.

The ADV7441A supports user-defined pixel sampling for nonstandard video sources and arbitrary pixel sampling for nonstandard video sources.

RGB GRAPHICS PROCESSING

The ADV7441A provides 170 MSPS conversion rate support of RGB input resolutions up to 1600 × 1200 @ 60 Hz (UXGA) and automatic or manual clamp and gain controls for graphics models.

The RGB graphics processing functionality features contrast and brightness controls, automatic detection of synchronization source and polarity by the SSPD block, standard identification enabled by the STDI block, and user-defined pixel sampling support for nonstandard video sources.

Additional RGB graphics processing features of the ADV7441A include the following:

• Sampling PLL clock with 500 ps p-p jitter at 170 MSPS.

• 32-phase DLL support of optimum pixel clock sampling.

• Color-space conversion of RGB to YCrCb and decimation

to a 4:2:2 format for videocentric back-end IC interfacing.

• Data enable (DE) output signal supplied for direct

connection to the HDMI/DVI transmitter IC.

GENERAL FEATURES

The ADV7441A features HS, VS, and FIELD output signals with programmable position, polarity, and width; and programmable interrupt request output pins, INT1 and INT2.

The part also offers low power consumption: 1.8 V digital core,

1.8 V analog, and 3.3 V digital input/output and low power powerdown mode.

The ADV7441A operates over a temperature range of −40°C to +85°C and is available in a 144-lead, 20 mm × 20 mm, RoHScompliant LQFP.

Rev. B | Page 15 of 28

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THEORY OF OPERATION

ANALOG FRONT END

The ADV7441A analog front end comprises four 10-bit ADCs that digitize the analog video signal before applying it to the SDP or CP. The analog front end uses differential channels connected to each ADC to ensure high performance in mixed-signal applications.

The analog front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7441A. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping in either the CP or SDP.

The ADCs are configured to run in 4× oversampling mode when decoding composite and S-Video inputs. For component 525i, 625i, 525p, and 625p sources, 2× oversampling is performed, but 4× oversampling is available for component 525i and 625i. All other video standards are 1× oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing (AA) filters with the benefit of an increased signalto-noise ratio (SNR).

The ADV7441A supports simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed and output, as controlled by the I the FB pin.

2

C registers and

HDMI RECEIVER

The HDMI receiver on the ADV7441A incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cables, especially those with long lengths and high frequencies. It is capable of equalizing for cable lengths up to 30 meters and, therefore, can achieve robust receiver performance at even the highest HDMI data rates.

With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7441A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.3 protocol.

The HDMI receiver also offers advanced audio functionality. The receiver contains an audio mute controller that can detect a variety of selectable conditions that may result in audible extraneous noise in the audio output. Upon detection of these conditions, the audio data can be ramped to prevent audio clicks and pops.

STANDARD DEFINITION PROCESSOR

The SDP section is capable of decoding a large selection of baseband video signals in composite, S-Video, and YUV formats. The video standards supported by the SDP include PAL (B/D/I/G/H/60/M/N/Nc), NTSC (M/J/4.43), and SECAM (B/D/G/K/L). The ADV7441A automatically detects the video standard and processes it accordingly. The SDP has a 5-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to a tuner SAW filter.

The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue.

The ADV7441A implements the patented ADLLT algorithm to track varying video line lengths from sources such as VCRs. ADLLT enables the ADV7441A to track and decode poor quality video sources, such as VCRs, and noisy sources, such as tuner outputs, VCD players, and camcorders. The SDP also contains a CTI processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image.

The SDP can process a variety of VBI data services, such as teletext, closed captioning (CC), wide-screen signaling (WSS), a video programming system (VPS), vertical interval time codes (VITC), a copy generation management system (CGMS), and an extended data service (XDS). The ADV7441A SDP section has a Macrovision 7.1 detection circuit that allows it to detect Type I, Type II, and Type III protection levels. The decoder is fully robust to all Macrovision signal inputs.

Rev. B | Page 16 of 28

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COMPONENT PROCESSOR (CP)

The component processor section is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards.

The CP section of the ADV7441A contains an AGC block. This block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); however, manual adjustment controls are also supported. If no embedded synchronization is present, the video gain can be set manually.

A fully programmable any-to-any 3 × 3 color-space converter is placed before the CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color-space converter.

A second fully programmable any-to-any 3 × 3 color space converter is placed in the back end of the CP core. This color space converter features advanced color controls such as contrast, saturation, brightness, and hue controls.

The output section of the CP is highly flexible. It can be configured in single data rate mode (SDR) with one data packet per clock cycle. In SDR mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In these modes, HS/CS, VS/FIELD, and DE/FIELD (where applicable) timing reference signals are provided.

The CP section contains circuitry to enable the detection of Macrovision-encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals.

VBI DATA PROCESSOR

VBI extraction of CGMS data is performed by the VBI data processor (VDP) section of the AD7441A for interlaced, progressive, and high definition scanning rates. The data extracted is read back over the I

For more detailed product information about the ADV7441A, send an e-mail to video.products@analog.com or contact a local Analog Devices sales representative.

2

C interface.

Rev. B | Page 17 of 28

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PIXEL OUTPUT FORMATTING

Note that unused pins of the pixel output port are driven with a low voltage.

Table 8. Standard Definition Pixel Port Modes (P19 to P0)

Data Port Pins P[19:0]

Processor Mode/Format

SDP

Table 9. Standard Definition Pixel Port Modes (P29 to P20)

Processor Mode/Format

SDP

Mode 1

Video output 8-bit 4:2:2

Mode 2

Video output 10-bit 4:2:2

Mode 3

Video output 16-bit 4:2:2

Mode 4

Video output 20-bit 4:2:2

Mode 5

Video output 24-bit 4:4:4

Mode 6

Video output 30-bit 4:4:4

Mode 1

Video output 8-bit 4:2:2

Mode 2

Video output 10-bit 4:2:2

Mode 3

Video output 16-bit 4:2:2

Mode 4

Video output 20-bit 4:2:2

Mode 5

Video output 24-bit 4:4:4

Mode 6

Video output 30-bit 4:4:4

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YCrCb[7:0]

YCrCb[9:0]

Y[7:0]

Y[9:0] Cb[9:0]

Y[7:0]

Y[9:0] Cb[9:0]

29 28 27 26 25 24 23 22 21 20

– – – – – – – – – –

– – – – – – – – – – – –

– – – – – – – – – –

– –

Data Port Pins P[29:20]

Cr[7:0]

Cr[9:0]

CrCb[7:0]

Cb[7:0]

– –

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Table 10. Component Processor Pixel Output Pin Map (P19 to P0)

Output of Data Port Pins P[19:0]

Processor1Mode/Format

CP

Mode 1

Video output 8-bit 4:2:2

2

Mode 2

Video output 10-bit 4:2:2

2

Mode 3

Video output 12-bit 4:2:2

2

Mode 4

Video output 12-bit 4:2:2

2

Mode 5

Video output 12-bit 4:2:2

2

Mode 6

Video output 16-bit 4:2:2

3, 4

Mode 7

Video output 20-bit 4:2:2

3, 4

Mode 8

Video output 20-bit 4:2:22

Mode 9

Video output 24-bit 4:2:2

3, 4

Mode 10

Video output 24-bit 4:2:2

3, 4

Mode 11

Video output 24-bit 4:2:2

3, 4

Mode 12

Video output 24-bit 4:4:4

3, 4

Mode 13

Video output 24-bit 4:4:4

3, 4

Mode 14

Video output 24-bit 4:4:4

3, 4

Mode 15

Video output 24-bit 4:4:4

3, 4

Mode 16

Video output 30-bit 4:4:4

3, 4

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

YCrCb[7:0]

YCrCb[9:0]

YCrCb[11:2]

YCrCb[11:4]

CHA[7:0] (default data is Y[7:0])

– – – – – – – – – – – –

– – – – – – – – – –

– – – – – – – – – – – –

– –

YCrCb[3:0]

CHB/CHC[7:0] (default data is Cr/Cb[7:0])

– – – – – –

CHA[9:0] (default data is Y[9:0]) CHB/CHC[9:0] (default data is Cr/Cb[9:0])

CHA[9:2] (default data is Y[9:2])

– –

CHB/CHC[9:2] (default data is Cr/Cb[9:2])

Y[11:2] CrCb[11:2]

Y[11:4]

– –

CrCb[11:4]

Y[11:4]

– –

Y[3:0] CrCb[3:0]

CHA[7:0] (default data is G[7:0] or Y[7:0])

– –

CHB[7:0] (default data is R[7:0] or Cr[7:0])

CHC[7:0] (default data is B[7:0] or

Cb[7:0])

CHC[7:0] (default data is B[7:0] or Cb[7:0])

– –

CHA[7:0] (default data is G[7:0] or Y[7:0])

CHC[7:0] (default data is B[7:0] or Cb[7:0])

– –

CHB[7:0] (default data is R[7:0] or Cr[7:0])

CHA[9:0] (default data is G[9:0] or Y[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0])

– –

Rev. B | Page 19 of 28

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Output of Data Port Pins P[19:0]

Processor1Mode/Format

CP

1

CP processor uses digitizer or HDMI as input.

2

Maximum pixel clock rate of 54 MHz.

3

Maximum pixel clock rate of 170 MHz (analog digitizer).

4

Maximum pixel clock rate of 165 MHz (HDMI).

Mode 17

Video output 30-bit 4:4:4

3, 4

Mode 18

Video output 30-bit 4:4:4

3, 4

Mode 19

Video output 30-bit 4:2:2

3, 4

Table 11. Component Processor Pixel Output Pin Map (P29 to P20)

Processor

CP

1

Mode/Format Mode 1

Video output 8-bit 4:2:2

CP

Mode 2

Video output 10-bit 4:2:2

CP

Mode 3

Video output 12-bit 4:2:2

CP

Mode 4

Video output 12-bit 4:2:2

CP

Mode 5

Video output 12-bit 4:2:2

CP

Mode 6

Video output 16-bit 4:2:2

CP

Mode 7

Video output 20-bit 4:2:2

CP

Mode 8

Video output 20-bit 4:2:2

CP

Mode 9

Video output 24-bit 4:2:2

CP

Mode 10

Video output 24-bit 4:2:2

CP

Mode 11

Video output 24-bit 4:2:2

CP

Mode 12

Video output 24-bit 4:4:4

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHA[9:0] (default data is G[9:0] or Y[9:0]) CHC[9:0] (default data is B[9:0] or Cb[9:0])

CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHA[9:0] (default data is G[9:0] or Y[9:0])

CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0])

Output of Data Port Pins P[29:20]

29 28 27 26 25 24 23 22 21 20

– – – – – – – – – –

2

– – – – – – – – – –

2

– – – – – –

2

– – – –

2

YCrCb[1:0]

YCrCb[3:0]

– – – – – – – – – –

2

– – – – – – – – – –

3, 4

– – – – – – – – – –

3, 4

Y[1:0] CrCb[1:0]

3, 4

– –

3, 4

CrCb[1:0]

– – – – – –

– –

Y[1:0]

CrCb[3:0] Y[3:0]

3, 4

CrCb[11:4]

3, 4

CHC[7:0] (for example, B[7:0] or Cb[7:0])

3, 4

– –

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Processor

CP

1

CP processor uses digitizer or HDMI as input.

2

Maximum pixel clock rate of 54 MHz.

3

Maximum pixel clock rate of 170 MHz (analog digitizer).

4

Maximum pixel clock rate of 165 MHz (HDMI).

1

Mode/Format Mode 13

Video output 24-bit 4:4:4

3, 4

Mode 14

Video output 24-bit 4:4:4

3, 4

Mode 15

Video output 24-bit 4:4:4

3, 4

Mode 16

Video output 30-bit 4:4:4

3, 4

Mode 17

Video output 30-bit 4:4:4

3, 4

Mode 18

Video output 30-bit 4:4:4

3, 4

Mode 19

Video output 30-bit 4:2:2

3, 4

29 28 27 26 25 24 23 22 21 20

CHB[7:0] (for example, R[7:0] or Cr[7:0])

CHA[7:0] (for example, G[7:0] or Y[7:0])

Output of Data Port Pins P[29:20]

– –

CHC[9:0] (for example, B[9:0] or Cb[9:0])

CHB[9:0] (for example, R[9:0] or Cr[9:0])

CHA[9:0] (for example, G[9:0] or Y[9:0])

Rev. B | Page 21 of 28

ADV7441A

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REGISTER MAP ARCHITECTURE

The ADV7441A registers are controlled via a 2-wire serial (I2C-compatible) interface. The ADV7441A has eight maps, each with a unique

2

I

C address. The state of the ALSB pin (Pin 13) sets Bit 2 of each register map address in Tab le 1 2 .

Table 12. Register Map Addresses

Default Address

Register Map

with ALSB = Low

User Map 0x40 0x42 Not programmable N/A User Map 1 0x44 0x46 Programmable User Map 2, Register 0xEB User Map 2 0x60 0x62 Programmable User Map, Register 0x0E VDP Map 0x48 0x4A Programmable User Map 2, Register 0xEC Reserved Map 0x4C 0x4E Programmable User Map 2, Register 0xEA HDMI Map 0x68 0x6A Programmable User Map 2, Register 0xEF Repeater KSV Map 0x64 0x66 Programmable User Map 2, Register 0xED EDID Map 0x6C 0x6E Programmable User Map 2, Register 0xEE

Default Address with ALSB = High

Programmable Address

Location Where Address Can Be Programmed

VDP MAPUSER MAP 2USER MAP 1USER MAP

SCL

SDA

SA: 0x40

PROGRAMMABLE

SA:

PROGRAMMABLE

Figure 7. Register Map Access Through Main I

SA:

PROGRAMMABLE

SA:

EDID MAPHDMI MAP

SA:

PROGRAMMABLE

REPEATER

KSV MAP

2

C Port

PROGRAMMABLE

SA:

PROGRAMMABLE

RESERVED MAP

06914-008

Rev. B | Page 22 of 28

ADV7441A

www.BDTIC.com/IC

TYPICAL CONNECTION DIAGRAM

Figure 8. Typical Connection Diagram

Rev. B | Page 23 of 28

06914-009

ADV7441A

www.BDTIC.com/IC

RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS

Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 9 and Figure 10.

70

ELPF

1.69kΩ

AUDIO_ELPF

10nF

102

1.5kΩ

8nF

82nF

Figure 9. ELPF Components

PVDD = 1.8V

6914-010

Figure 10. AUDIO_ELPF Components

80nF

PVDD = 1.8V

6914-011

Rev. B | Page 24 of 28

ADV7441A

www.BDTIC.com/IC

AD9388A/ADV7441A EVALUATION PLATFORM

Analog Devices has developed a new evaluation platform for

AD9388A

the /ADV7441A decoders. The evaluation platform consists of a motherboard and two daughterboards. The motherboard features a Xilinx FPGA for digital processing and muxing functions. The motherboard also features three AD9742s (12-bit DACs) from Analog Devices. This allows the user to drive a VGA monitor with just the motherboard and front-end board.

Table 13. Front-End Modular Board Details

Front-End Modular Board Model On-Board Decoder HDCP License Required

EVAL-ADV7441AFEZ_1 EVAL-ADV7441AFEZ_2 EVAL-AD9388AFEZ_1 EVAL-AD9388AFEZ_2 EVAL-AD9388AFEZ_3

ADV7441ABSTZ-170 Yes ADV7441ABSTZ-5P No AD9388ABSTZ-170 Yes AD9388ABSTZ-5P No AD9388ABSTZ-A5 Yes

The backend of the platform can be connected to a specially developed video output board from Analog Devices. This modular board features an ADV7341 encoder and AD9889B HDMI transmitter.

The front end of the platform consists of an EVALAD9388AFEZ_x or EVAL-ADV7441AFEZ_x board. This board feeds the digital outputs from the decoder to the FPGA on the motherboard. The EVAL-AD9388AFEZ_x or EVALADV7441AFEZ_x board comes with one of the pin-compatible decoders shown in Tabl e 13 .

EVAL-AD9388AFEZ_x OR ADV7441AFEZ_x

VIDEO INPUT BOARD

AD9388A/ADV7441A

DECODER

ANALOG AND DIGITAL VIDEO INPUTS

AVI 168-PIN CONNECTOR

ATV MOTHERBOARD

Xilinx FPGA

AVO 168-PIN CONNECTOR

VIDEO OUTPUT BOARD

AD9889B ADV7341

AUDIO 96-PIN CO NNECTOR

VGA

OUTPUT

CVBS

Y/C

HDMI

Figure 11. Functional Block Diagram of Evaluation Platform

Rev. B | Page 25 of 28

YPrPb

06914-012

ADV7441A

www.BDTIC.com/IC

OUTLINE DIMENSIONS

22.20

0.75

0.60

0.45

1.60 MAX

144

1

PIN 1

22.00 SQ

21.80

TOP VIEW

(PINS DOWN)

109

108

20.20

20.00 SQ

19.80

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09 7°

3.5° 0°

0.08 COPLANARIT Y

36

37

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-BFB

0.50 BSC

LEAD PITCH

0.27

0.22

0.17

73

72

051706-A

Figure 12. 144-Lead Low Profile Quad Flat Package [LQFP]

(ST-144)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7441ABSTZ-170 ADV7441ABSTZ-110 ADV7441ABSTZ-5P EVAL- ADV7441AFEZ_1 EVAL- ADV7441AFEZ_2

1

Z = RoHS Compliant Part.

2

This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC for licensing requirements) to

purchase any components with internal HDCP keys.

3

Speed grade: 5 = 170MHz. HDCP functionality: P = no HDCP functionality (pro version).

4

Professional version for nonHDCP encrypted applications. Purchaser is not required to be a HDCP adopter.

5

Front-end board for new evaluation platform; fitted with ADV7441ABSTZ-170 decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on

evaluation platform.

6

Front-end board for new evaluation platform; fitted with ADV7441ABSTZ-5P decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on

evaluation platform.

1, 2

−40°C to +85°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144

1, 2

1, 3 , 4

−40°C to +85°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144

1, 2, 5

1, 4, 6

−40°C to +85°C 144-Lead Low Profile Quad Flat Package [LQFP] ST-144

Front End Evaluation Board Front End Evaluation Board

Rev. B | Page 26 of 28

ADV7441A

www.BDTIC.com/IC

NOTES

Rev. B | Page 27 of 28

ADV7441A

www.BDTIC.com/IC

NOTES

Rev. B | Page 28 of 28

ANALOG DEVICES ADV7441A Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VIDEO SPECIFICATIONS

ANALOG AND HDMI SPECIFICATIONS

TIMING CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

PACKAGE THERMAL PERFORMANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FUNCTIONAL OVERVIEW

ANALOG FRONT END

HDMI RECEIVER

STANDARD DEFINITION PROCESSOR PIXEL DATA OUTPUT MODES

COMPOSITE AND S-VIDEO PROCESSING

COMPONENT PROCESSOR PIXEL DATA OUTPUT MODES

COMPONENT VIDEO PROCESSING

RGB GRAPHICS PROCESSING

GENERAL FEATURES

THEORY OF OPERATION

ANALOG FRONT END

HDMI RECEIVER

STANDARD DEFINITION PROCESSOR

COMPONENT PROCESSOR (CP)

VBI DATA PROCESSOR

PIXEL OUTPUT FORMATTING

REGISTER MAP ARCHITECTURE

TYPICAL CONNECTION DIAGRAM

RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS

AD9388A/ADV7441A EVALUATION PLATFORM

OUTLINE DIMENSIONS

ORDERING GUIDE