ANALOG DEVICES ADV7441A Service Manual

10-Bit Integrated, Multiformat SDTV/HDTV Video Decoder,

www.BDTIC.com/IC

RGB Graphics Digitizer, and 2:1 Multiplexed

HDMI/DVI Interface

FEATURES

Multiformat decoder

Four 10-bit analog-to-digital converters (ADCs) ADC sampling rates up to 170 MHz Mux with 12 analog input channels SCART fast blank sampling support NTSC/PAL/SECAM color standards support 525p-/625p-component progressive scan formats support 720p-/1080i-/1080p-component HD formats support Digitizes RGB graphics from VGA to UXGA rates

(up to 1600 × 1200 @ 60 Hz) VBI data slicer (including teletext) Analog-to-HDMI fast switching mode

Dual High-Definition Multimedia Interface (HDMI) Rx

2:1 multiplexed HDMI receiver HDMI 1.3, DVI 1.0 225 MHz HDMI receiver Repeater support High-bandwidth digital content protection (HDCP 1.3) 36-bit deep color support S/PDIF (IEC60958-compatible) digital audio output Multichannel I Adaptive equalizer for cable lengths up to 30 meters Internal EDID RAM

General

Highly flexible output interface STDI function support standard identification 2 any-to-any 3 × 3 color-space conversion matrices Programmable interrupt request output pins

APPLICATIONS

Advanced TVs

PDP HDTVs LCD TVs (HDTV ready) LCD/DLP® rear projection HDTVs CRT HDTVs LCoS® HDTVs

Audio/video receivers (AVR) LCD/DLP front projectors HDTV STBs with PVR DVD recorders with progressive scan input support

2

S audio output (up to 8 channels)

ADV7441A

GENERAL DESCRIPTION

The ADV7441A is a high quality multiformat video decoder and graphics digitizer with an integrated 2:1 multiplexed HDMI™ receiver.

The ADV7441A contains two main processing sections. The first section is the standard definition processor (SDP), which processes all types of PAL, NTSC, and SECAM signals. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The ADV7441A can keep the HDCP link between a HDMI source and the selected HDMI port active in analog mode operation. This allows for fast switching between the analog and HDMI modes.

As a decoder, the ADV7441A can convert PAL, NTSC, and SECAM composite or S-Video signals into a digital ITU-R BT.656 format. It can also decode a component RGB or YPrPb video signal into a digital YCrCb or RGB pixel output stream. The ADV7441A supports the 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i component video standards as well as many other HD and SMPTE standards. SCART and overlay functionality are enabled by the ability of the ADV7441A to process CVBS and standard definition RGB signals simultaneously. As a graphics digitizer, the ADV7441A can digitize RGB graphics signals from VGA to UXGA rates and convert them to a digital RGB or YCrCb pixel output stream.

The ADV7441A incorporates a dual-input HDMI 1.3-compatible receiver that supports HDTV formats up to 1080p and display resolutions up to UXGA. The reception of encrypted video is possible with the inclusion of HDCP. The inclusion of adaptive equalization in the HDMI receiver ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has advanced audio functionality, including a mute controller that prevents audible extraneous noise in the audio output.

To facilitate professional applications, where HDCP processing and decryption is not required, a derivative part of the ADV7441A is available. This allows users who are not HDCP adopters to purchase the ADV7441A. See the Ordering Guide for details.

Fabricated using an advanced CMOS process, the ADV7441A is available in a space-saving, 144-lead, surface-mount, RoHScompliant, plastic LQFP and is specified over the −40°C to +85°C temperature range.

Rev.

B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other rights of third parties that may result from its use. Specifications subject to chan ge without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

7/08—Rev. SpA to Rev. B

5/08—Rev. Sp0 to Rev. SpA

Changes to General Description Section ...................................... 1

Change to Clamp Level (When Locked) Parameter, Table 3 ...... 7

Changes to Standard Definition Processor Pixel Data Output

Modes Section ................................................................................. 14

Changes to Component Processor Pixel Data Output

Modes Section ................................................................................. 14

Changes to Table 8 .......................................................................... 18

Added Table 9 .................................................................................. 18

Added Table 10 ............................................................................... 19

Added Table 11 ............................................................................... 20

Added AD9388A/ADV7441A Evaluation System Section ....... 25

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 26

10/07—Revision Sp0: Initial Version

Rev. B | Page 2 of 28

ADV7441A

A

0

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FUNCTIONAL BLOCK DIAGRAM

DATA

PIXEL

P0 TO P9

10

DATA

ANCILLARY

DATA

ANCILLARY

FORMATTER

VBI DATA PROCESSOR

VBI

DECODER

COMPONENT PROCESSOR

DIGITAL PROCESSING BLOCK

SYNC EXTRACT

AV

STANDARD

AND

SYNC SOURCE

CODE

IDENTIFICATION

POLARITY DET ECT

INSERTION

OFFSET

ADDRESS

AND

GAIN

®

CONTROL

CGMS DETECT ION

FINE

MACROVISIO N

DIGITIAL

DELAY

PROGRAM

6914-001

P10 TO P19

P20 TO P29

10

GBR

HSYNC DEPTH

ACTIVE PEAK AND

CLAMP

NOISE AND

CALIBRATION

FB

INT1

OUTPUT FORMATTE R

LUMA

2D COMB

RE-

LUMA

GAIN

CONTRO L

STANDARD DEFINITION PROCESSOR

LUMA

FILTER

HS/CS

VS/FIELD

DE/FIELD

AV

(0x04 MAX)

SAMPLE

CODE

INSERTION

RE-

SAMPLE

CONTROL

LINE

LENGTH

PREDICTOR

LLC

SFL/

SYNC_OUT/

INT2

FAST BLANK OVERLAY CONTROL

CTI

C-DNR

CHROMA

2D COMB

(0x04 MAX)

RE-

SAMPLE

CHROMA

FREE RUN

SYNTHESIZED

GAIN

CHROMA

LLC CONTRO L

CONTRO L

FILTER

OUTPUT CONTROL

S

2

LRCLK

SCLK

I

GLOBAL

CONTRO L

STANDARD

AUTODETECTION

SPDIF

MCLKOUT

FINE

CHA

CHB

COLOR SPACE

CHC

FILTERS

CONVERT ER

CHD

10

ADC3

CLAMP

CY

DOWNSAMPLING

DECIMATION AND

CONTROL

HS/CS, VS

LLC

GENERATION

AND CLOCK

GENERATION

SYNC PROCESSING

SYNC

DATA

EMBEDDED

PROCESSOR

CHA

CHB

CHC

10

ADC2

ADC1

ADC0

CLAMP

ANALOG INTERFACE

INPUT

MATRIX

LUMA

DIGITAL

MUX

CONTROL AND DATA

SYNC

CLAMP

CONTROL

C

2

I

CONTROL

INTERFACE

EXTRACT

FILTER

FSC

RECOVERY

SAMPLER

DEMOD

CHROMA

VBI DATA

RECOVERY

DETECTION

MACROVISION

FINE

CLAMP

DIGITAL

CHROMA

CONVERSION 4:2:2 TO 4: 4:4

PACKET

XOR

VS

HS

DE

HDMI DECODE

ALIGNMENT

DATA RECOVERY

MUX

PLL

SAMPLER

EQUALIZER

MUX

EEPROM

HDCP

ENGINE

HDCP

CONTRO LLER

EQUALIZER

AUDIO

PROCESSING

PACKET/

MEMORY

INFOFRAME

PROCESSOR

MCL

MDA

DDCB_SCL

EDID/REPEATER

DDCB_SD DDCA_SD DDCA_SCL

CVBS

SOY

RGB

YPrPb

CVBS

YC AND

SOG

VS_IN

HS_IN/CS_IN

FB

SCL

SDA

ALSB

Figure 1.

Rev. B | Page 3 of 28

RXA_0

RXA_1

RXA_2

RXB_0

RXB_1

RXA_C

RXB_C

RXB_2

ADV7441A

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

STATIC PERFORMANCE

1

2

Symbol Test Conditions Min Typ Max Unit

Resolution (Each ADC) N 10 Bits Integral Nonlinearity INL BSL 27 MHz (@ a 10-bit level) −0.5/+2 −4/+6 LSB BSL 54 MHz (@ a 10-bit level) −0.5/+2 LSB BSL 74 MHz (@ a 10-bit level) −0.5/+1.5 LSB BSL 110 MHz (@ a 10-bit level) −0.7/+2 LSB BSL 170 MHz (@ an 8-bit level) −0.25/+0.5 LSB Differential Nonlinearity DNL At 27 MHz (@ a 10-bit level) −0.5/+0.5 −0.95/+2 LSB At 54 MHz (@ a 10-bit level) ±0.5 LSB At 74 MHz (@ a 10-bit level) ±0.5 LSB At 110 MHz (@ a 10-bit level) ±0.5 LSB At 170 MHz (@ an 8-bit level) −0.25/+0.2 LSB

DIGITAL INPUTS

Input High Voltage

3

V

2 V

IH

HS_IN/CS_IN, VS_IN low trigger mode 0.7 V Input Low Voltage

3

V

0.8 V

IL

HS_IN/CS_IN, VS_IN low trigger mode 0.3 V Input Current IIN

Pin 21 (RESET

)

−60 +60 μA

All input pins other than Pin 21 −10 +10 μA Input Capacitance

4

CIN 10 pF

DIGITAL OUTPUTS

Output High Voltage Output Low Voltage High Impedance Leakage Current I Output Capacitance

POWER REQUIREMENTS

5

V

4

C

4

VOH I

I

OL

10 μA

LEAK

20 pF

OUT

= 0.4 mA 2.4 V

SOURCE

= 3.2 mA 0.4 V

SINK

Digital Core Power Supply DVDD 1.62 1.8 1.98 V Digital I/O Power Supply DVDDIO 2.97 3.3 3.63 V PLL Power Supply PVDD 1.71 1.8 1.89 V Analog Power Supply AVDD 1.71 1.8 1.89 V Terminator Power Supply TVDD 3.135 3.3 3.465 V Comparator Power Supply CVDD 1.71 1.8 1.89 V Digital Core Supply Current I

CVBS input sampling @ 54 MHz

DVDD

Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Digital I/O Supply Current I

CVBS input sampling @ 54 MHz

DVDDIO

Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz

6

141 252 mA

7, 8

242 329 mA

7, 8

6

7, 8

20 34 mA

140 189 mA

6

152 205 mA

6

203 263 mA

242 326 mA 16 48 mA 17 37 mA

6

16 50 mA

6

42 61 mA 17 34 mA

Rev. B | Page 4 of 28

ADV7441A

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Parameter

HDMI Comparators I TMDS PLL and Equalizer Graphics RGB sampling @ 108 MHz Supply Current SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Analog Supply Current Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Terminator Supply Current I Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Audio and Video PLL Supply Current I Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz Power-Down Current I Power-Up Time t

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

All ADC linearity tests were performed at input range full scale − 12.5% and at zero scale + 12.5%.

3

Pin 1, Pin 105, Pin 106, and Pin 144 are 5 V tolerant.

4

Guaranteed by characterization.

5

The VOH and VOL levels were obtained using the default drive strength value (0x15) in User Map Register 0xF4.

6

Current measurements for analog inputs were made with HDMI/analog simultaneous mode disabled (User Map Register 0xBA, Bit 7 programmed with Value 0) and

with no HDMI sources connected to the part.

7

Current measurements for HDMI inputs were made with a source connected to the active HDMI port and with no source connected to the inactive HDMI port.

8

Audio stream is a noncompressed stereo audio sampling frequency of fS = 48 kHz, and MCLKOUT = 256 fS.

9

Analog current measurements for CVBS were made with only ADC0 powered up; for RGB, with only ADC0, ADC1, and ADC2 powered up; for SCART FB, with all ADCs

powered up; and for HDMI mode, with all ADCs powered off.

10

The terminator supply current may vary with the HDMI source in use.

1

9

Symbol Test Conditions Min Typ Max Unit

6

CVBS input sampling @ 54 MHz

CVDD

I

CVBS input sampling @ 54 MHz

AVDD

CVBS input sampling @ 54 MHz

TVDD

CVBS input sampling @ 54 MHz

PVDD

11.6 mA

PWRDN

25 ms

PWRUP

6

7, 8

86 105 mA

7, 8

6

63 102 mA

6

174 278 mA

7, 8

6

12 18 mA

6

12 18 mA

7, 8, 10

6

7, 8

to T

MIN

56 78 mA 56 78 mA

6

56 79 mA

6

56 79 mA

95 118 mA

6

225 348 mA

6

180 284 mA 0 2 mA 0 2 mA

6

12 18 mA

6

12 18 mA 42 47 mA 63 69 mA 18 23 mA 14 21 mA

6

17 23 mA

6

19 24 mA 10 19 mA 15 20 mA

).

MAX

Rev. B | Page 5 of 28

ADV7441A

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VIDEO SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 2.

1, 2

Parameter

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulated in five steps 0.3 Degrees Differential Gain DG CVBS input, modulated in five steps 0.6 % Luma Nonlinearity LNL CVBS input, five steps 0.8 %

NOISE SPECIFICATIONS

SNR Unweighted Luma flat field 63.1 dB

Analog Front-End Crosstalk

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 % Vertical Lock Range 40 70 Hz FSC Subcarrier Lock Range ±1.3 kHz Color Lock-In Time 60 Lines Synchronization Depth Range Color Burst Range 5 200 % Vertical Lock Time 2 Fields Horizontal Lock Time 100 Lines

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 Degrees Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error

Chroma Luma Intermodulation

LUMA SPECIFICATIONS

Luma Brightness Accuracy Luma Contrast Accuracy

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

Guaranteed by characterization.

3

Nominal synchronization depth is 300 mV at 100% of the synchronization depth range.

3

Symbol Test Conditions Min Typ Max Unit

20 200 %

Luma ramp 61.8

0.1 Degrees

0.3 %

CVBS, 0.5 V input 1 % CVBS, 0.5 V input 1 %

to T

).

MIN

MAX

60 dB

dB

Rev. B | Page 6 of 28

ADV7441A

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ANALOG AND HDMI SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 3.

1, 2

Parameter

Test Conditions Min Typ Max Unit

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance (Except Pin 74) Clamps switched off 10 MΩ Input Impedance of Pin 74 20 kΩ Common-Mode Level (CML) 0.88 V ADC Full-Scale Level CML + 0.5 V ADC Zero-Scale Level CML − 0.5 V ADC Dynamic Range 1 V

Clamp Level (When Locked) CVBS input CML – 0.122 V SCART RGB input (R, G, B signals) CML – 0.167 V S-Video input (Y signal) CML– 0.122 V S-Video input (C signal) CML V Component input (Y signal) CML − 0.120 V Component input (Pr signal) CML V Component input (Pb signal) CML V PC RGB input (R, G, B signals) CML − 0.120 V

Large Clamp Source Current SDP only 8 mA

Large Clamp Sink Current SDP only 8 mA

Fine Clamp Source Current SDP only 0.25 μA

Fine Clamp Sink Current SDP only 0.4 μA HDMI SPECIFICATIONS

Intrapair (Positive-to-Negative) Differential

3

0.4 t

Input Skew

Channel-to-Channel Differential Input Skew 0.2 t

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

Guaranteed by characterization.

3

Guaranteed by design.

4

t

is 1/10 the pixel period t

bit

5

t

is the period of the TMDS clock.

pixel

.

to T

MAX

).

MIN

5

+ 1.78 ns

pixel

4

bit

Rev. B | Page 7 of 28

ADV7441A

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TIMING CHARACTERISTICS

AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted.

Table 4.

Parameter

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency 28.6363 MHz Crystal Frequency Stability ±50 ppm Horizontal Sync Input Frequency 14.8 110 kHz LLC Frequency Range 12.825 170 MHz

I2C PORTS (FAST MODE)

xCL Frequency xCL Minimum Pulse Width High xCL Minimum Pulse Width Low Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs xDA Setup Time xCL and xDA Rise Times xCL and xDA Fall Times Setup Time for Stop Condition t8 0.6 μs

I2C PORTS (NORMAL MODE)

xCL Frequency xCL Minimum Pulse Width High xCL Minimum Pulse Width Low Hold Time (Start Condition) t3 4 μs Setup Time (Start Condition) t4 4.7 μs xDA Setup Time xCL and xDA Rise Times xCL and xDA Fall Times Setup Time for Stop Condition t8 4 μs

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC Mark Space Ratio t9:t10 45:55 55:45 % duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transition Time SDR (SDP)5t11 Negative clock edge to start of valid data 3.4 ns t Data Output Transition Time SDR (CP)6t13 End of valid data to negative clock edge 2 ns t

I2S PORT (MASTER MODE)

SCLK Mark Space Ratio t15:t16 45:55 55:45 % duty cycle LRCLK Data Transition Time t17 End of valid data to negative SCLK edge 10 ns t I2Sx Data Transition Time t MCLKOUT Frequency 4.096 24.576 MHz

1

The minimum/maximum specifications are guaranteed over the −40°C to +85°C temperature range (T

2

Guaranteed by characterization.

3

Refers to all I2C pins (DDC and control port).

4

The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S.

5

SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4.

6

CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4.

7

The suffix x refers to pin names ending with 0, 1, 2, and 3.

1, 2

3

4

t

4

t

4

t

4

t

3

4

100 kHz

4

t

4

t

4

t

4

t

4

t

7

Symbol Test Conditions Min Typ Max Unit

400 kHz

0.6 μs

1

1.3 μs

2

100 ns

5

t6 300 ns

300 ns

7

4 μs

1

4.7 μs

2

250 ns

5

1000 ns

6

300 ns

7

End of valid data to negative clock edge 2.4 ns

12

Negative clock edge to start of valid data 0.5 ns

14

Negative SCLK edge to start of valid data 10 ns

18

t

19

Negative SCLK edge to start of valid data 5 ns

20

End of valid data to negative SCLK edge 5 ns

to T

).

MIN

MAX

Rev. B | Page 8 of 28

ADV7441A

S

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TIMING DIAGRAMS

Figure 2. I

t

5

2

C Timing

t

3

xDA

t

6

1

xCL

t

2

NOTES

1. THE PREF IX x REFERS T O PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S.

t

7

t

3

t

4

t

8

06914-002

LLC

P0 TO P29, VS,

HS, DE/FIELD,

FL/SYNC_OUT

t

9

t

12

t

10

t

11

06914-003

Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)

LLC

P0 TO P29, VS,

HS, DE/FI ELD

t

9

t

13

Figure 4. Pixel Port and Control SDR Output Timing (CP Core)

t

10

t

14

06914-004

t

15

SCLK

t

16

t

17

LRCLK

t

18

t

19

MSB MSB – 1

t

20

MSB

t

19

MSB – 1

t

20

2

Figure 5. I

S Timing

Rev. B | Page 9 of 28

t

19

LSBMSB

t

20

06914-007

2

I

S MODE

I2Sx

MODE

I2Sx

MODE

LEFT-JUSTIFIED

RIGHT-JUSTIFIED

NOTES

1. THE SUFF IX x REFE RS TO PI N NAMES ENDING WITH 0, 1, 2, AND 3.

ANALOG DEVICES ADV7441A Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VIDEO SPECIFICATIONS

ANALOG AND HDMI SPECIFICATIONS

TIMING CHARACTERISTICS

TIMING DIAGRAMS