ANALOG DEVICES ADV7403 Service Manual

12-Bit, Integrated, Multiformat SDTV/HDTV

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Video Decoder and RGB Graphics Digitizer

FEATURES

Four Noise Shaped Video® 12-bit ADCs sampling up to

140 MHz (140 MHz speed grade only) 12 analog input channel mux SCART fast blank support Internal antialias filters NTSC/PAL/SECAM color standards support 525p-/625p-component progressive scan 720p-/1080i-component HDTV support Digitizes RGB graphics up to 1280 × 1024 @ 75 Hz (SXGA)

(140 MHz speed grade only) 24-bit digital input port supports data from DVI/HDMI Rx IC Any-to-any, 3 × 3 color-space conversion matrix Industrial temperature range (−40°C to +85°C) 12-bit 4:4:4/10-/8-bit 4:2:2 DDR pixel output interface Programmable interrupt request output pin VBI data slicer (including teletext)

APPLICATIONS

LCD/DLP™ rear projection HDTVs PDP HDTVs CRT HDTVs LCD/DLP front projectors LCD TV (HDTV ready) HDTV STBs with PVR Hard-disk-based video recorders Multiformat scan converters DVD recorders with progressive scan input support AVR receiver

support

ADV7403

GENERAL DESCRIPTION

The ADV7403 is a high quality, single chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-video into a digital ITU-R BT.656 format. The ADV7403 also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many other HD and SMPTE standards. Graphic digitization is also supported by the ADV7403; it is capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ADV7403’s ability to simultaneously process CVBS and standard definition RGB signals. The mixing of these signals is controlled by the fast blank pin.

The ADV7403 contains two main processing sections. The first

he standard definition processor (SDP), which processes all

is t PAL, NTSC, and SECAM signal types. The second is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. For more specific descriptions of the ADV7403 features, see the

nctionality and Detailed Description sections.

Fu

Detailed

Rev. SpA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

CP Pixel Data Output Modes ................................................... 13

Electrical Characteristics ................................................................. 4

Video Specifications......................................................................... 6

Timing Characteristics..................................................................... 7

Analog Specifications....................................................................... 8

Absolute Maximum Ratings............................................................ 9

Stress Ratings ................................................................................ 9

Package Thermal Performance................................................... 9

Thermal Specifications ................................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Timing Diagrams............................................................................ 12

Detailed Functionality ................................................................... 13

Analog Front End....................................................................... 13

SDP Pixel Data Output Modes ................................................. 13

Composite and S-Video Processing......................................... 13

Component Video Processing.................................................. 14

RGB Graphics Processing ......................................................... 14

Digital Video Input Port............................................................ 14

General Features......................................................................... 14

Detailed Description...................................................................... 15

Analog Front End....................................................................... 15

Standard Definition Processor ................................................. 15

Component Processor ............................................................... 15

Pixel Input/Output Formatting .................................................... 17

Recommended External Loop Filter Components.................... 19

Typical C o n necti on D i a g ram ....................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

9/05—Rev. Sp0 to Rev. SpA

Deleted EDTV.....................................................................Universal

Added AVR Receiver to Applications Section .............................. 1

Change to Crystal Normal Frequency Typ Value in Table 3 ...... 7

Changes to Figure 2 ....................................................................... 10

Changes to Function Descriptions of Pin 37 and Pin 38 .......... 11

Change Pin 70 Type........................................................................ 11

Change to Crystal MHz Unit Value............................................. 13

Added Pixel Input Information to Table 9 and Table 10........... 17

Changes to Figure 9........................................................................ 20

4/05—Revision Sp0: Initial Version

Rev. SpA | Page 2 of 24

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FUNCTIONAL BLOCK DIAGRAM

P29–P20

P19–P10

P9–P0

PIXEL

DATA

HS

VS

FIELD/DE

LLC1

SFL/

8

OUTPUT FIFO AND FORMATTER

8

SYNCOUT

INT

VBI DATA RECOVERY

STANDARD

AUTODETECTION

STANDARD DEFINITION PROCESSOR

DETECTION

MACROVISION

CVBS/Y

Y

LUMA

(5H MAX)

2D COMB

LUMA

RESAMPLE

LUMA

FILTER

20

AND

FAST

BLANK

AV CODE

OVERLAY

CONTROL

INSERTION

Cb

(4H MAX)

2D COMB

RESAMPLE

FILTER

DEMOD

Cr

Y

Cr

Cb

CGMS DATA

COMPONENT PROCESSOR

MACROVISION

ACTIVE PEAK

Cb

CONTROL

RESAMPLE

SYNC

EXTRACT

SC

F

RECOVERY

Cr

CHROMA

C

CVBS

EXTRACTION

DETECTION

AND

AGC

30

12

AV CODE

INSERTION

OFFSET

CONTROL

GAIN

CONTROL

FINE

CLAMP

DIGITAL

12

ADV7403

ANTI-

DATA

PREPROCESSOR

A/DCLAMP

ALIAS

121212

FILTER

12

AIN1

12

COLORSPACE

CONVERSION

AND

FILTERS

DECIMATION

DOWNSAMPLING

12

SOY

888

XTAL1

XTAL

DIGITAL INPUT

P40–P31

PORT

DVI or HDMI

24

P1–P0

P11–P10

P29–P20

05431-001

A/DCLAMP

ANTI-

ALIAS

FILTER

MUX

INPUT

CVBS

AIN12

S-VIDEO

YPrPb

TO

ALIAS

SCART–

FILTER

(RGB + CVBS)

GRAPHICS RGB

ALIAS

FILTER

FB

SCLK

SERIAL INTERFACE

SDA

SCLK2

CONTROL AND VBI DATA

SDA2

STDI

SSPD

CLOCK GENERATION

SYNC PROCESSING AND

ALSB

DCLK_IN

SOG

VS_IN

DE_IN

HS_IN

Figure 1.

Rev. SpA | Page 3 of 24

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ELECTRICAL CHARACTERISTICS

@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. Operating temperature range, a otherwise noted.

Table 1.

Parameter

STATIC PERFORMANCE

Resolution (each ADC) N 12 Bits Integral Nonlinearity INL BSL at 27 MHz (at a 12-bit level) ±2.0 ±8.0 LSB Integral Nonlinearity INL BSL at 54 MHz (at a 12-bit level) −2.0/+2.5 LSB Integral Nonlinearity INL BSL at 74 MHz (at a 10-bit level) ±1.0 LSB Integral Nonlinearity INL BSL at 110 MHz (at a 10-bit level) −3.0/+3.0 LSB Integral Nonlinearity INL BSL at 135 MHz (at an 8-bit level) Differential Nonlinearity DNL At 27 MHz (at a 12-bit level) −0.7/+0.85 −0.99/+2.5 LSB Differential Nonlinearity DNL At 54 MHz (at a 12-bit level) −0.75/+0.9 LSB Differential Nonlinearity DNL At 74 MHz (at a 10-bit level) ±0.75 LSB Differential Nonlinearity DNL At 110 MHz (at a 10-bit level) −0.7/+5.0 LSB Differential Nonlinearity DNL At 135 MHz (at an 8-bit level)6

DIGITAL INPUTS

Input High Voltage Input Low Voltage Input High Voltage V Input Low Voltage V Input Current I All other input pins −10 +10 μA Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current I All other output pins 10 μA Output Capacitance

POWER REQUIREMENTS

Digital Core Power Supply DVDD 1.65 1.8 2 V Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V PLL Power Supply PVDD 1.71 1.8 1.89 V Analog Power Supply AVDD 3.15 3.3 3.45 V Digital Core Supply Current IDVDD CVBS input sampling at 54 MHz 105 mA Graphics RGB sampling at 135 MHz 137 mA SCART RGB FB sampling at 54 MHz 106 mA Digital I/O Supply Current IDVDDIO CVBS input sampling at 54 MHz 4 mA Graphics RGB sampling at 135 MHz 19 mA PLL Supply Current IPVDD CVBS input sampling at 54 MHz 11 mA Graphics RGB sampling at135 MHz 12 mA Analog Supply Current Graphics RGB sampling at 135 MHz 242 mA SCART RGB FB sampling at 54 MHz 269 mA Power-Down Current IPWRDN 2.25 mA Green Mode Power-Down IPWRDNG Sync bypass function 16 mA Power-Up Time TPWRUP 20 ms

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00.

1, , 2 3

4, 5

7

8

10

11

10

13

to T

MIN

: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).

MAX

Symbol Test Conditions Min Typ Max Unit

6

±1.3 LSB

LSB

V V

C

V V

C

IH

IL

IH

IL

IN

OH

OL

LEAK

OUT

−0.8/+2.5

2 V

0.8 V HS_IN, VS_IN low trigger mode 0.7 V HS_IN, VS_IN low trigger mode 0.3 V Pins listed in Note 9 −60 +60 μA

10 pF

ISOURCE = 0.4 mA 2.4 V ISINK = 3.2 mA 0.4 V Pins listed in Note 12 60 μA

20 pF

IAVDD CVBS input sampling at 54 MHz 99 mA

Rev. SpA | Page 4 of 24

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4

All ADC linearity tests performed at input range of full scale − 12.5%, and at zero scale + 12.5%.

5

Max INL and DNL specifications obtained with part configured for component video input.

6

Specification for ADV7403KSTZ-140 only.

7

To obtain specified VIH level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,

then V

on Pin 38 = 1.2 V.

IH

8

To obtain specified VIL level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,

then V

on Pin 38 = 0.4 V.

IL

9

Pins 1, 2, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 78, 79, 83, 84, 87, 88, 95, 96, 97, 100.

10

Guaranteed by characterization.

11

VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.

12

Pins 3, 13, 14, 19, 24, 29, 30, 31, 32, 33, 34, 45.

13

Analog current measurements for CVBS made with ADC0 powered up only, For RGB, ADC0, ADC1, and ADC2 powered up only, for SCART FB, all ADCs powered up.

Rev. SpA | Page 5 of 24

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VIDEO SPECIFICATIONS

@ AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted.

Table 2.

Parameter

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulated 5 step 0.4 degree Differential Gain DG CVBS input, modulated 5 step 0.4 % Luma Nonlinearity LNL CVBS input, 5 step 0.4 %

NOISE SPECIFICATIONS

SNR Unweighted Luma ramp 61 64 dB SNR Unweighted Luma flat field 64 65 dB Analog Front End Crosstalk 60 dB

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 % Vertical Lock Range 40 70 Hz FSC Subcarrier Lock Range ±1.3 kHz Color Lock in Time 60 line Sync Depth Range Color Burst Range 5 200 % Vertical Lock Time 2 field Horizontal Lock Time 100 line

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 degree Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.4 % Chroma Phase Error 0.3 degree Chroma Luma Intermodulation 0.1 %

LUMA SPECIFICATIONS

Luma Brightness Accuracy CVBS, 1 V input 1 % Luma Contrast Accuracy CVBS, 1 V input 1 %

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

Guaranteed by characterization.

4

Nominal sync depth is 300 mV at 100% sync depth range.

1, , 2 3

4

to T

MIN

: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).

MAX

Symbol Test Conditions Min Typ Max Unit

20 200 %

Rev. SpA | Page 6 of 24

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TIMING CHARACTERISTICS

@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted.

Table 3.

Parameter

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency 28.63636 MHz Crystal Frequency Stability ±50 ppm Horizontal Sync Input Frequency 14.8 110 kHz LLC1 Frequency Range

I2C PORT

SCLK Frequency 400 kHz SCLK Min Pulse Width High t SCLK Min Pulse Width Low t Hold Time (Start Condition) t Setup Time (Start Condition) t SDA Setup Time t SCLK and SDA Rise Time t SCLK and SDA Fall Time t Setup Time for Stop Condition t

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio t9:t

DATA and CONTROL OUTPUTS

Data Output Transition Time SDR (SDP)

Data Output Transition Time SDR (CP)

Data Output Transition Time DDR (CP)

DATA and CONTROL INPUTS Input Setup Time (Digital Input Port) t DE_IN, data inputs 2.2 ns Input Hold Time (Digital Input Port) t

DE_IN, data inputs 2 ns

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

Guaranteed by characterization.

4

Maximum LLC1 frequency is 110 MHz for ADV7403BSTZ-110.

5

TTL input values are 0 V to 3 V, with rise/fall times ≥3 ns, measured between the 10% and 90% points.

6

SDP timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4.

7

CP timing figures obtained using max drive strength value (0xFF) in Register Subaddress 0xF4.

8

DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.

1, , 2 3

4

5

to T

MIN

: −40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).

MAX

Symbol Test Conditions Min Typ Max Unit

12.825 140 MHz

1

2

3

4

5

6

7

8

10

6

t

11

6

t

12

7

t

13

7

t

14

7, 8

t

15

7, 8

t

16

7, 8

t

17

7, 8

t

18

19

20

0.6 μs

1.3 μs

0.6 μs

0.6 μs 100 ns 300 ns 300 ns

0.6 μs

45:55 55:45

Negative clock edge to start of

3.6 ns

valid data End of valid data to negative

2.4 ns

clock edge End of valid data to negative

2.8 ns

clock edge Negative clock edge to start of

0.1 ns

valid data Positive clock edge to end of

−4 + TLLC1/4 ns

valid data Positive clock edge to start of

0.25 + TLLC1/4 ns

valid data Negative clock edge to end of

−2.95 + TLLC1/4 ns

valid data Negative clock edge to start of

−0.5 + TLLC1/4 ns

valid data

HS_IN, VS_IN 9 ns

HS_IN, VS_IN 7 ns

% duty cycle

Rev. SpA | Page 7 of 24

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ANALOG SPECIFICATIONS

@ AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6V , typically 1 V p-p.

Table 4.

Parameter

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF Input Impedance Input Impedance of Pin 51 (FB) 20 kΩ CML 1.86 V ADC Full-Scale Level CML + 0.8 V V ADC Zero-Scale Level CML − 0.8 V V ADC Dynamic Range 1.6 V Clamp Level (When Locked) CVBS input CML − 0.292 V V SCART RGB input (R, G, B signals) CML − 0.4 V V S-Video input (Y signal) CML − 0.292 V V S-Video input (C signal) CML – 0 V V Component input (Y, Pr, Pb signals) CML – 0.3 V V PC RGB input (R, G, B signals) CML − 0.3 V V Large Clamp Source Current SDP only 0.75 mA Large Clamp Sink Current SDP only 0.9 mA Fine Clamp Source Current SDP only 17 μA Fine Clamp Sink Current SDP only 17 μA

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

Guaranteed by characterization.

4

Except Pin 51 (FB).

1, , 2 3

4

to T

MIN

:−40°C to +85°C (0°C to 70°C temperature range for ADV7403KSTZ-140).

MAX

Test Conditions Min Typ Max Unit

Clamps switched off 10 MΩ

Rev. SpA | Page 8 of 24

ANALOG DEVICES ADV7403 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

ELECTRICAL CHARACTERISTICS

VIDEO SPECIFICATIONS

TIMING CHARACTERISTICS

ANALOG SPECIFICATIONS