Datasheet ADV7401 Datasheet (ANALOG DEVICES)

10-Bit, Integrated, Multiformat SDTV/HDTV

www.BDTIC.com/ADI

Video Decoder and RGB Graphics Digitizer

FEATURES

Four 10-bit ADCs sampling up to 140 MHz

(140 MHz speed grade only)
12 analog input channel mux
SCART fast blank support
Internal antialias filters
NTSC/PAL/SECAM color standards support
525p-/625p-component progressive scan
720p-/1080i-component HDTV support
Digitizes R

(140 MHz speed grade only)
24-bit digital input port supports data from DVI/HDMI Rx IC
Any-to-any, 3 × 3 color-space conversion matrix
Industrial temperature range (−40°C to +85°C)
12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface
Programmable interrupt request output pin
VBI data slicer (including teletext)

GB graphics up to 1280 × 1024 @ 75 Hz (SXGA)

APPLICATIONS

LCD/DLP™ rear projection HDTVs
PDP HDTVs
CRT HDTVs
LCD/DLP front projectors
LCD TV (HDTV ready)
HDTV STBs with PVR
Hard-disk-based video recorders
Multiformat scan converters
DVD recorders with progressive scan input support
AVR receiver

support

ADV7401

GENERAL DESCRIPTION

The ADV7401 is a high quality, single chip, multiformat video
decoder and graphics digitizer. This multiformat decoder
supports the conversion of PAL, NTSC, and SECAM standards
in the form of composite or S-video into a digital ITU-R BT.656
format. The ADV7401 also supports the decoding of a
component RGB/YPrPb video signal into a digital YCrCb or
RGB pixel output stream. The support for component video
includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,
1250i, and many other HD and SMPTE standards. Graphic
digitization is also supported by the ADV7401; it is capable of
digitizing RGB graphics signals from VGA to SXGA rates and
converting them into a digital RGB or YCrCb pixel output
stream. SCART and overlay functionality are enabled by the
ADV7401’s ability to simultaneously process CVBS and
standard definition RGB signals. The mixing of these signals is
controlled by the fast blank pin.

The ADV7401 contains two main processing sections. The first

standard definition processor (SDP), which processes all

is the
PAL, NTSC, and SECAM signal types. The second is the
component processor (CP), which processes YPrPb and RGB
component formats, including RGB graphics. For more specific
descriptions of the ADV7401 features, see the Detailed
Functionality and Detailed Description sections.

Rev. SpA

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADV7401

www.BDTIC.com/ADI

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

CP Pixel Data Output Modes ................................................... 13

Electrical Characteristics ................................................................. 4

Video Specifications......................................................................... 6

Timing Characteristics..................................................................... 7

Analog Specifications....................................................................... 8

Absolute Maximum Ratings............................................................ 9

Stress Ratings ................................................................................ 9

Package Thermal Performance................................................... 9

Thermal Specifications ................................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Timing Diagrams............................................................................ 12

Detailed Functionality ................................................................... 13

Analog Front End....................................................................... 13

SDP Pixel Data Output Modes ................................................. 13

Composite and S-Video Processing......................................... 13

Component Video Processing.................................................. 14

RGB Graphics Processing ......................................................... 14

Digital Video Input Port............................................................ 14

General Features......................................................................... 14

Detailed Description...................................................................... 15

Analog Front End....................................................................... 15

Standard Definition Processor (SDP)...................................... 15

Component Processor ............................................................... 15

Pixel Input/Output Formatting .................................................... 17

Recommended External Loop Filter Components.................... 18

Typical C o n necti on D i a g ram ....................................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

9/05—Rev. Sp 0 to Rev. SpA

Deleted EDTV.....................................................................Universal

Added AVR Receiver to Applications Section .............................. 1

Changes to Table 3............................................................................ 7

Changes to Figure 2........................................................................ 10

Changes to Function Descriptions of Pin 37 and Pin 38 .......... 11

Change Pin 70 Type........................................................................ 11

Change to Crystal MHz Unit Value............................................. 13

Added Pixel Input Information to Table 9 and Table 10........... 17

4/05—Revision Sp0: Initial Version

Rev. SpA | Page 2 of 20

ADV7401

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FUNCTIONAL BLOCK DIAGRAM

P29–P22

P19–P12

P9–P2

PIXEL

DATA

HS

VS

FIELD/DE

LLC1

SFL/

8

8

OUTPUT FIFO AND FORMATTER

8

SYNCOUT

INT

VBI DATA RECOVERY

STANDARD

AUTODETECTION

STANDARD DEFINITION PROCESSOR

DETECTION

MACROVISION

CVBS/Y

Y

LUMA

(5H MAX)

2D COMB

LUMA

RESAMPLE

LUMA

FILTER

EXTRACTION

DETECTION

AND

AGC

24

10

AV CODE

INSERTION

OFFSET

CONTROL

GAIN

CONTROL

FINE

CLAMP

DIGITAL

10

10

16

AND

FAST

BLANK

AV CODE

OVERLAY

CONTROL

INSERTION

(4H MAX)

RESAMPLE

FILTER

DEMOD

Y

Cr

Cb

CGMS DATA

COMPONENT PROCESSOR

MACROVISION

ACTIVE PEAK

Cb

Cr

CONTROL

RESAMPLE

SYNC

EXTRACT

SC

F

RECOVERY

Cr

CHROMA

CVBS

Cb

2D COMB

CHROMA

CHROMA

CHROMA

C

10

ADV7401

ANTI-

DATA

PREPROCESSOR

A/DCLAMP

ALIAS

101010

FILTER

12

AIN1

10

COLORSPACE

CONVERSION

AND

FILTERS

DECIMATION

DOWNSAMPLING

10

10

10

SOY

888

XTAL1

XTAL

DIGITAL INPUT

P40–P31

PORT

DVI or HDMI

24

P1–P0

P11–P10

P29–P20

05340-001

A/DCLAMP

A/DCLAMP

A/DCLAMP

ANTI-

ANTI-

ANTI-

ALIAS

FILTER

MUX

INPUT

CVBS

AIN12

S-VIDEO

YPrPb

TO

ALIAS

SCART–

FILTER

(RGB + CVBS)

GRAPHICS RGB

ALIAS

FILTER

FB

SCLK

SERIAL INTERFACE

SDA

SCLK2

CONTROL AND VBI DATA

SDA2

STDI

CLOCK GENERATION

SSPD

SYNC PROCESSING AND

ALSB

DCLK_IN

SOG

VS_IN

DE_IN

HS_IN

Figure. 1.

Rev. SpA | Page 3 of 20

ADV7401

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ELECTRICAL CHARACTERISTICS

@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.
Operating temperature range, unless otherwise noted.

Table 1.

Parameter

STATIC PERFORMANCE

Resolution (each ADC) N 10 Bits
Integral Nonlinearity INL BSL at 27 MHz (at a 10-bit level) ±0.6 ±2.5 LSB
Integral Nonlinearity INL BSL at 54 MHz (at a 10-bit level) −0.6/+0.7 LSB
Integral Nonlinearity INL BSL at 74 MHz (at a 10-bit level) ±1.4 LSB
Integral Nonlinearity INL BSL at 110 MHz (at an 8-bit level)
Integral Nonlinearity INL BSL at 135 MHz (at an 8-bit level)
Differential Nonlinearity DNL At 27 MHz (at a 10-bit level) −0.2/+0.25 −0.99/+2.5 LSB
Differential Nonlinearity DNL At 54 MHz (at a 10-bit level) −0.2/+0.25 LSB
Differential Nonlinearity DNL At 74 MHz (at a 10-bit level) ±0.9 LSB
Differential Nonlinearity DNL At 110 MHz (at an 8-bit level)
Differential Nonlinearity DNL At 135 MHz (at an 8-bit level)

DIGITAL INPUTS

Input High Voltage
Input Low Voltage
Input High Voltage V
Input Low Voltage V
Input Current I
All other input pins −10 +10 μA
Input Capacitance

DIGITAL OUTPUTS

Output High Voltage
Output Low Voltage
High Impedance Leakage Current I
All other output pins 10 μA
Output Capacitance

POWER REQUIREMENTS

Digital Core Power Supply DVDD 1.65 1.8 2 V
Digital I/O Power Supply DVDDIO 3.0 3.3 3.6 V
PLL Power Supply PVDD 1.71 1.8 1.89 V
Analog Power Supply AVDD 3.15 3.3 3.45 V
Digital Core Supply Current IDVDD CVBS input sampling at 54 MHz 105 mA
Graphics RGB sampling at 135 MHz 137 mA
SCART RGB FB sampling at 54 MHz 106 mA
Digital I/O Supply Current IDVDDIO CVBS input sampling at 54 MHz 4 mA
Graphics RGB sampling at 135 MHz 19 mA
PLL Supply Current IPVDD CVBS input sampling at 54 MHz 11 mA
Graphics RGB sampling at 135 MHz 12 mA
Analog Supply Current
Graphics RGB sampling at 135 MHz 242 mA
SCART RGB FB sampling at 54 MHz 269 mA
Power-Down Current IPWRDN 2.25 mA
Green Mode Power-Down IPWRDNG Sync bypass function 16 mA
Power-Up Time TPWRUP 20 ms

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00.

4

All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale + 12.5%.

1, , 2 3

4, 5

8

9

10

8

12

12

8

8

14

to T

MIN

: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).

MAX

6

±0.9 LSB

7

±1.5 LSB

6

7

−0.2/+1.5 LSB

−0.9/+3.0 LSB

V
V

C

V
V

C

IH

IL

IH

IL

IN

IN

OH

OL

LEAK

OUT

2 V

0.8 V
HS_IN, VS_IN low trigger mode 0.7 V
HS_IN, VS_IN low trigger mode 0.3 V
Pins listed in Note 11 −60 +60 μA

10 pF

I

= 0.4 mA 2.4 V

SOURCE

I

= 3.2 mA 0.4 V

SINK

Pins listed in Note 13 60 μA

20 pF

IAVDD CVBS input sampling at 54 MHz 99 mA

Rev. SpA | Page 4 of 20

Symbol Test Conditions Min Typ Max Unit

ADV7401

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5

Max INL and DNL specifications obtained with part configured for component video input.

6

Specification for ADV7401BSTZ-110 and ADV7401KSTZ-140 only.

7

Specification for ADV7401KSTZ-140 only.

8

Guaranteed by characterization.

9

To obtain specified VIH level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,

then V

on Pin 38 = 1.2 V.

IH

10

To obtain specified VIL level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,

then V

on Pin 38 = 0.4 V.

IL

11

Pins 1, 2, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 79, 83, 84, 87, 88, 95, 96, 97, 100.

12

VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.

13

Pins 3, 13, 14, 19, 24, 29, 30, 31, 32, 33, 34, 45.

14

Analog current measurements for CVBS made with ADC0 powered up only, For RGB, ADC0, ADC1 and ADC2 powered up only, for SCART FB, all ADCs powered up.

Rev. SpA | Page 5 of 20

ADV7401

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VIDEO SPECIFICATIONS

@ AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.

Table 2.

Parameter

NONLINEAR SPECIFICATIONS

Differential Phase DP CVBS input, modulated 5 step 0.5 degree
Differential Gain DG CVBS input, modulated 5 step 0.5 %
Luma Nonlinearity LNL CVBS input, 5 step 0.5 %

NOISE SPECIFICATIONS

SNR Unweighted
SNR Unweighted Luma flat field 58 60 dB

Analog Front End Crosstalk

LOCK TIME SPECIFICATIONS

Horizontal Lock Range −5 +5 %
Vertical Lock Range 40

FSC Subcarrier Lock Range ±1.3 kHz
Color Lock in Time 60 line
Sync Depth Range
Color Burst Range 5 200 %
Vertical Lock Time 2 field
Horizontal Lock Time 100 line

CHROMA SPECIFICATIONS

Hue Accuracy HUE 1 degree
Color Saturation Accuracy CL_AC 1 %
Color AGC Range 5 400 %
Chroma Amplitude Error 0.5 %
Chroma Phase Error

Chroma Luma Intermodulation

LUMA SPECIFICATIONS

Luma Brightness Accuracy
Luma Contrast Accuracy

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

Guaranteed by characterization.

4

Nominal sync depth is 300 mV at 100% sync depth range.

1, , 2 3

4

to T

MIN

: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).

MAX

Symbol Test Conditions Min Typ Max Unit

Luma ramp 54 56

60 dB

70 Hz

20 200 %

0.4 degree

0.2 %

CVBS, 1 V input 1 %
CVBS, 1 V input 1 %

dB

Rev. SpA | Page 6 of 20

ADV7401

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TIMING CHARACTERISTICS

@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.

Table 3.

Parameter

SYSTEM CLOCK AND CRYSTAL

Crystal Nominal Frequency 28.63636 MHz
Crystal Frequency Stability ±50 ppm
Horizontal Sync Input Frequency 14.8 110 kHz
LLC1 Frequency Range

I2C PORT

SCLK Frequency 400 kHz
SCLK Min Pulse Width High t
SCLK Min Pulse Width Low t
Hold Time (Start Condition) t
Setup Time (Start Condition) t
SDA Setup Time t
SCLK and SDA Rise Time t
SCLK and SDA Fall Time t
Setup Time for Stop Condition t

RESET FEATURE

Reset Pulse Width 5 ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio t9:t

DATA and CONTROL OUTPUTS

Data Output Transition Time SDR (SDP)

Data Output Transition Time SDR (SDP)

Data Output Transition Time SDR (CP)

Data Output Transition Time SDR (CP)

Data Output Transition Time DDR (CP)

Data Output Transition Time DDR (CP)

Data Output Transition Time DDR (CP)

Data Output Transition Time DDR (CP)

DATA and CONTROL INPUTS

Input Setup Time (Digital Input Port) t
DE_IN, data inputs 2.2 ns
Input Hold Time (Digital Input Port) t

DE_IN, data inputs 2 ns

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

Guaranteed by characterization.

4

Maximum LLC1 frequency is 80 MHz for ADV7401BSTZ-80 and is 110 MHz for ADV7401BSTZ-110.

5

TTL input values are 0 V to 3 V, with rise/fall times ≤3 ns, measured between the 10% and 90% points.

6

SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.

7

CP timing figures obtained using max drive strength value (0xFF) in register subaddress 0xF4.

8

DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.

1, , 2 3

4

5

5

to T

MIN

: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).

MAX

Symbol Test Conditions Min Typ Max Unit

12.825 140 MHz

1

2

3

4

5

6

7

8

6

t

11

6

t

12

7

t

13

7

t

14

7, 8

t

15

7, 8

t

16

7, 8

t

17

7, 8

t

18

19

20

0.6 μs

1.3 μs

0.6 μs

0.6 μs
100 ns
300 ns
300 ns

0.6 μs

45:55 55:45 % duty cycle

10

Negative clock edge

3.6 ns

to start of valid data
End of valid data to

2.4 ns

negative clock edge
End of valid data to

2.8 ns

negative clock edge
Negative clock edge

0.1 ns

to start of valid data
Positive clock edge to

−4 + TLLC1/4 ns

end of valid data
Positive clock edge to

0.25 + TLLC1/4 ns

start of valid data
Negative clock edge

−2.95 + TLLC1/4 ns

to end of valid data
Negative clock edge

−0.5 + TLLC1/4 ns

to start of valid data

HS_IN, VS_IN 9 ns

HS_IN, VS_IN 7 ns

Rev. SpA | Page 7 of 20

ADV7401

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ANALOG SPECIFICATIONS

@ AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature
range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.

Table 4.

Parameter

CLAMP CIRCUITRY

External Clamp Capacitor 0.1 μF
Input Impedance
Input Impedance of Pin 51 (FB) 20 kΩ
CML 1.86 V
ADC Full-Scale Level CML + 0.8 V V
ADC Zero-Scale level CML − 0.8 V V
ADC Dynamic Range 1.6 V
Clamp Level (When Locked) CVBS input CML – 0.292 V V
SCART RGB input (R, G, B signals) CML – 0.4 V V
S-Video input (Y signal) CML – 0.292 V V
S-Video input (C signal) CML – 0 V V
Component input (Y, Pr, Pb signals) CML – 0.3 V V
PC RGB input (R, G, B signals) CML – 0.3 V V
Large Clamp Source Current SDP only 0.75 mA
Large Clamp Sink Current SDP only 0.9 mA
Fine Clamp Source Current SDP only 17 μA
Fine Clamp Sink Current SDP only 17 μA

1

The min/max specifications are guaranteed over this range.

2

Temperature range T

3

Guaranteed by characterization.

4

Except Pin 51 (FB).

1, , 2 3

4

to T

MIN

: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).

MAX

Test Conditions Min Typ Max Unit

Clamps switched off 10 MΩ

Rev. SpA | Page 8 of 20

ADV7401

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ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

AVDD to AGND 4 V
DVDD to DGND 2.2 V
PVDD to AGND 2.2 V
DVDDIO to DGND 4 V
DVDDIO to AVDD −0.3 V to +0.3 V
PVDD to DVDD −0.3 V to +0.3 V
DVDDIO to PVDD −0.3 V to +2 V
DVDDIO to DVDD −0.3 V to +2 V
AVDD to PVDD −0.3 V to +2 V
AVDD to DVDD −0.3 V to +2 V
Digital Inputs Voltage to

DGND

Digital Outputs Voltage to

DGND
Analog Inputs to AGND AGND − 0.3 V to AVDD + 0.3 V
Maximum Junction

Temperature (T
Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering

(20 sec)

J MAX

)

DGND − 0.3 V to DVDDIO + 0.3 V

DGND − 0.3 V to DVDDIO + 0.3 V

125°C

260°C

STRESS RATINGS

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the part the user is
advised to turn off any unused ADCs .

The junction temperature must always stay below the

mum junction temperature (T

maxi
equation shows how to calculate the junction temperature:

T

= T

J

+ (θJA × W

A Max

Max

)

where:

T

= 85°C.

A Max

θ

= 30°C/W.

JA

= ((AVDD × IAVDD) + (DVDD × IDVDD) +

W

Max

(DVDDIO × IDVDDIO) + (PVDD × IPVDD)).

) of 125°C. This

J MAX

THERMAL SPECIFICATIONS

Table 6.

Thermal Characteristics Symbol Test Conditions Typ Unit

Junction-to-Case Thermal Resistance θ
Junction-to-Ambient Thermal Resistance θ

JC

JA

4-layer PCB with solid ground plane 7 °C/W
4-layer PCB with solid ground plane (still air) 30 °C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. SpA | Page 9 of 20

ADV7401

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN
_

3

3
P

100

E
D

/
D
L
E

S

I
F

V

99

98

6

6

5

4

1

3

3

3

P

P

P

P

95

97

96

94

D
D

9

7

8

V

1

1

1

D

P

P

P

93

92

91

90

D
N

7

G

3
P

D

898887

S
C

/
N

N

I

I

_

_

8

S

S

3

V

H

P

86

85

1
K
L

0

9

C

4

3

S

P

P

84

82

83

T

N

1

E

B

I

_

A

S

E

L

D

D

A

S

81

80

79

Y

S
E

O
S

R

787776

6
N

I
A

1

P32
P31

INT

CS/HS

DGND

DVDDIO

P15
P14
P13
P12

DGND

DVDD

P29
P28

SFL/SYNC_OUT

SCLK2

DGND

DVDDIO

SDA2

P11
P10

P27

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

P9

23

P8

24
25

P7

PIN 1

26

P6

ADV7401

LQFP

TOP VIEW

(Not to Scale)

27

P5

31

29

30

28

P4

P26

P25

32

P2333P2234P21

P24

37

38

36

LLC1

39

XTAL

DVDD

XTAL1

35

DCLK_IN

40

DGND

42

41

P3

P2

43

P144P0

45

P20

46

ELPF

47

PVDD

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type Function

5, 11, 17, 40, 89 DGND G Digital Ground.
49, 50, 60, 66 AGND G Analog Ground.
6, 18 DVDDIO P Digital I/O Supply Voltage (3.3 V).
12, 39, 90 DVDD P Digital Core Supply Voltage (1.8 V).
63 AVDD P Analog Supply Voltage (3.3 V).
47, 48 PVDD P PLL Supply Voltage (1.8 V).
51 FB I

54, 56, 58, 72, 74, 76, 53, 55,

AIN1 to AIN12 I Analog Video Input Channels.

Fast Switch Overlay Input. This pin switches between CVBS and RGB
analog signal

s.

57, 71, 73, 75
42, 41, 28, 27, 26, 25, 23, 22,

P2 to P9, P12 to P19 O Video Pixel Output Port.

10, 9, 8, 7, 94, 93, 92, 91
33, 32, 31, 30, 29, 24, 14, 13 P22 to P29 I/O Video Input/Output Port
44, 43, 21, 20, 45, 34, 2, 1,

100, 97, 96, 95, 88, 87, 84, 83
3

P0 to P1, P10 to P11,
P20 to P21, P31 to P40

INT

I Video Pixel Input Port.

O

Interrupt. This pin can be active low or ac
bits change this pin triggers. The set of events that triggers an interrupt
is under user control.

75

AIN12

74

AIN5

73

AIN11

72

AIN4

71

AIN10

70

TEST0

69

CAPC2

68

CAPC1

67

BIAS

66

AGND

65

CML

64

REFOUT

63

AVDD

62

CAPY2

61

CAPY1

60

AGND

59

TEST1

58

AIN3

57

AIN9

56

AIN2

55

AIN8

54

AIN1

53

AIN7

52

SOG

51

FB

48

49

PVDD

AGND50AGND

05340-002

tive high. When SDP/CP status

Rev. SpA | Page 10 of 20

ADV7401

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Pin No. Mnemonic Type Function

4 HS/CS O

99 VS O Vertical Synchronization Output Signal (SDP and CP modes).
98 FIELD/DE O

81, 19 SDA1, SDA2 I/O

82, 16 SCLK1, SCLK2 I

80 ALSB I

78

36 LLC1 O

38 XTAL I

37 XTAL1 O

46 ELPF O The recommend external loop filter must be connected to this ELPF pin.
70 TEST0 NC This pin should be left unconnected or alternatively tied to AGND.
59 TEST1 O This pin should be left unconnected.
15 SFL/SYNC_OUT O

64 REFOUT O Internal Voltage Reference Output.
65 CML O Common-Mode Level Pin (CML) for the internal ADCs.
61, 62 CAPY1, CAPY2 I ADC Capacitor Network.
68, 69 CAPC1, CAPC2 I ADC Capacitor Network.
67 BIAS O

86 HS_IN/CS_IN I

85 VS_IN I VS Input Signal. Used in CP mode for 5-wire timing mode.
79 DE_IN I

35 DCLK_IN I

52 SOG I Sync on Green Input. Used in embedded sync mode.
77 SOY I Sync on Luma Input. Used in embedded sync mode.

RESET

I

HS is a Horizontal Synchronization Output Signal (SDP and CP modes).
CS is a Digital Composite Synchroniz
while in CP mode).

Field Synchronization Output Signal (all
pin also can be enabled as a Data Enable signal (DE) in CP mode to allow
direct connection to a HDMI/DVI Tx IC.

2

C Port Serial Data Input/Output Pins. SDA1 is the data line for the

I
control port and SDA2 is the data line for the VBI readback port.

2

C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock

I
line for the control port and SCLK2 is the clock line for the VBI data
readback port.

This pin selects the I
readback ports. ALSB set to Logic 0 sets the address for a write to control
port of 0x40 and the readback address for the VBI port of 0x21. ALSB set
to a logic high sets the address for a write to control port of 0x42 and the
readback address for the VBI port of 0x23.

System Reset Input, Active Low. A minimum low reset pulse width of 5
ms is required to reset the ADV7401 circuitry.

LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz
to 140 MHz for ADV7401KSTZ-1
ADV7401BSTZ-110; 12.825 MHz to 80 MHz for ADV7401BSTZ-80).

Input pin for 28.63636 MHz crystal, or can be overdriven by an external

3.3 V 28.63636 MHz clock oscillator source to clock the ADV7401.
This pin should be connected to the 28.63636 MHz crystal or left as a no

connect if an external 3.3 V 28.63636 MHz clock oscillator source
to clock the ADV7401. In crystal mode, the crystal must be a
fundamental crystal.

Subcarrier Frequency Lock (SFL). This pin contains a seri
which can be used to lock the subcarrier frequency when this decoder is
connected to any Analog Devices digital video encoder. SYNC_OUT is
the sliced sync output signal available only in CP mode.

External Bias Setting Pin. Connect the recommend
between pin and ground.

Can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to e
mode.

Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI Rx IC).

Clock Input Signal. Used in 24-bit digital input m
processing 24-bit RGB data from a DVI Rx IC) and also in digital CVBS
input mode.

2

C address for the ADV7401 control and VBI

ation Signal (and can be selected

interlaced video modes). This

40; 12.825 MHz to 110 MHz for

is used

al output stream

ed resistor (1.35 kΩ)

xtract timing in a 5-wire or 4-wire RGB

ode (for example,

Rev. SpA | Page 11 of 20

ADV7401

www.BDTIC.com/ADI

TIMING DIAGRAMS

SDA1/SDA2

SCLK1/SCLK2

t

3

t

t

6

1

t

2

t

7

Figure 3. I

t

5

2

C Timing

t

3

t

4

t

8

05340-003

LLC1

P2–P9, P12–P19,

P22–P29

LLC1

P2–P9, P12–P19,

P22–P29, VS, HS,

FIELD/DE,

SFL/SYNC_OUT

t

9

t

t

10

t

11

12

Figure 4. Pixel Port and Control SDR Output Timing (SD Core)

t

9

t

13

t

10

t

14

Figure 5. Pixel Port and Control SDR Output Timing (CP Core)

LLC1

05340-004

05340-005

t

16

t

P6–P9,

P12–P19

15

Figure 6. Pixel Port and Control DDR Output Timing (CP Core)

DCLK_IN

t

20

t

19

CONTROL

INPUTS

P0–P1, P10–P11,

P20–P21, P22–P29,

P31–P32, P33–P40

HS_IN
VS_IN
DE_IN

t9t

10

Figure 7. Digital Input Port and Control Input Timing

Rev. SpA | Page 12 of 20

t

18

t

17

05340-006

05340-008

ADV7401

www.BDTIC.com/ADI

DETAILED FUNCTIONALITY

ANALOG FRONT END

• Four high quality 10-bit ADCs enable true 8-bit video

decoder

• 12 analog input channel mux enables multisource

nnection without the requirement of an external mux

co

• Four current and voltage clamp control loops ensure any

dc o

ffsets are removed from the video signal

• SCART functionality and SD RGB overlay on CVBS

ntrolled by fast blank input

co

• Four internal antialias filters to remove out-of-band noise

o

n standard definition input video signals

SDP PIXEL DATA OUTPUT MODES

• 8-bit ITU-R BT.656 4:2:2 YCrCb with embedded time

codes and/or HS, VS, and FIELD

• 16-bit YCrCb with embedded time codes and/or HS, VS,

a

nd FIELD

• Proprietary architecture for locking to weak, noisy, and

un

stable sources from VCRs and tuners

• IF filter block compensates for high frequency luma

ttenuation due to tuner SAW filter

a

• Chroma transient improvement (CTI)

• Luminance digital noise reduction (DNR)

• Color controls include hue, brightness, saturation, contrast,

a

nd Cr and Cb offset controls

• Certified Macrovision copy protection detection on

mposite and S-video for all worldwide formats

co
(PAL/NTSC/SECAM)

• 4× oversampling (54 MHz) for CVBS, S-video, and YUV

des

mo

• Line-locked clock output (LLC)

• Letterbox detection supported

• 24-bit YCrCb with embedded time codes and/or HS, VS,

nd FIELD

a

CP PIXEL DATA OUTPUT MODES

• Single data rate (SDR) 8-bit 4:2:2 YCrCb for 525i, 625i

• Single data rate (SDR) 16-bit 4:2:2 YCrCb for all standards

• Single data rate (SDR) 24-bit 4:4:4 YCrCb/RGB for all

st

andards

• Double data rate (DDR) 8-bit 4:2:2 YCrCb for all standards

• Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all

andards

st

COMPOSITE AND S-VIDEO PROCESSING

• Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N,

60) and SECAM B/D/G/K/L standards in the form of
CVBS and S-video

• Superadaptive 2D 5-line comb filters for NTSC and PAL

ive superior chrominance and luminance separation for

g
composite video

• Full automatic detection and autoswitching of all

w

orldwide standards (PAL/NTSC/SECAM)

• Free-run output mode provides stable timing when no

eo input is present

vid

• Vertical blanking interval data processor

l eTe x t

Te
Video Programming System (VPS)
Vertical Interval Time Codes (VITC)
Closed captioning (CC) and extended data service (EDS)
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Gemstar™ 1×/2× electronic program guide compatible

• Clo

• Subcarrier frequency lock (SFL) output for downstream

• Differential gain typically 0.5%

• Differential phase typically 0.5°

cked from a single 28.63636 MHz crystal

vide

o encoder

• Automatic gain control with white peak mode ensures the

v

ideo is always processed without loss of the video

processing range

• Adaptive digital line length tracking (ADLLT™)

Rev. SpA | Page 13 of 20

ADV7401

www.BDTIC.com/ADI

COMPONENT VIDEO PROCESSING

• Formats supported include 525i, 625i, 525p, 625p, 720p,

1080i, and many other HDTV formats

• Automatic adjustments include gain (contrast) and offset

brightness); manual adjustment controls are also

(
supported

• Support for analog component YPrPb/RGB video formats

th embedded sync or with separate HS, VS, or CS

wi

• Any-to-any, 3 × 3 color space conversion matrix supports

CrCb-to-RGB and RGB-to-YCrCb

Y

DIGITAL VIDEO INPUT PORT

• Supports raw 8-bit CVBS data from digital tuner

• Support for 24-bit RGB input data from DVI Rx chip,

o

utput converted to YCrCb 4:2:2

• Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p,

1080i

, 720p, VGA to SXGA @ 60 Hz input data from

HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb

GENERAL FEATURES

• HS, VS, and FIELD output signals with programmable

position, polarity, and width

• Standard identification (STDI) enables system level

co

mponent format detection

• Synchronization source polarity detector (SSPD) deter-

nes the source and polarity of the synchronization

mi
signals that accompany the input video

• Certified Macrovision copy protection detection on

mponent formats (525i, 625i, 525p, and 625p)

co

• Free-run output mode provides stable timing when no

eo input is present

vid

• Arbitrary pixel sampling support for nonstandard video

urces

so

RGB GRAPHICS PROCESSING

• 140 MSPS conversion rate supports RGB input resolutions

up to 1280 × 1024 @ 75 Hz (SXGA); (110 MSPS conversion
rate for ADV7401BSTZ-110); (80 MSPS conversion rate for
ADV7401BSTZ-80)

• Automatic or manual clamp and gain controls for graphics

mo

des

• Contrast and brightness controls

INT

• Programmable interrupt request output pin,

SDP/CP status changes

• Supports two I

• Low power consumption: 1.8 V digital core, 3.3 V analog

a

nd digital I/O, low power power-down mode, and green

PC mode

• Industrial temperature range (−40°C to +85°C)

t ADV7401KSTZ-140)

(excep

• 140 MHz sp

• 100-lead, 14

2

C host port interfaces (control and VBI)

eed grade (ADV7401KST-140)

mm × 14 mm, Pb-free LQFP

, signals

• 32-phase DLL allows optimum pixel clock sampling

• Automatic detection of sync source and polarity by SSPD

ock

bl

• Standard identification is enabled by STDI block

• RGB can be color space converted to YCrCb and

decimated to a 4:2:2 format for video centric backend IC
interfacing

• Data enable (DE) output signal supplied for direct

nnection to HDMI/DVI Tx IC

co

• Arbitrary pixel sampling support for nonstandard video

urces

so

Rev. SpA | Page 14 of 20

ADV7401

www.BDTIC.com/ADI

DETAILED DESCRIPTION

ANALOG FRONT END

The ADV7401 analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the
SDP or CP (see Ta b le 8 for sampling rates). The analog front
end uses dif
performance in a mixed-signal application.

The front end also includes a 12-channel input mux that enables
mu

ltiple video signals to be applied to the ADV7401. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping in either the CP or SDP.

Optional antialiasing filters are positioned in front of each
ADC. T
definition video signals, removing spurious, out-of-band noise.

The ADCs are configured to run in 4× oversampling mode

en decoding composite and S-video inputs; 2× oversampling

wh
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
anti-aliasing filters with the benefit of an increased signal-to­noise ratio (SNR).

The ADV7401 can support simultaneous processing of CVBS
and RGB st
ibility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under control of I
registers and the fast blank pin.

Table 8. Maximum ADC Sampling Rates

Model Maximum ADC Sampling Rate

ADV7401BSTZ-80 80 MHz
ADV7401BSTZ-110 110 MHz
ADV7401KSTZ-140 140 MHz

ferential channels to each ADC to ensure high

hese filters can be used to band-limit standard

andard definition signals to enable SCART compat-

2

C

STANDARD DEFINITION PROCESSOR (SDP)

The SDP section is capable of decoding a large selection of
baseband video signals in composite S-video and YUV formats.
The video standards supported by the SDP include PAL
B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43, and
SECAM B/D/G/K/L. The ADV7401 can automatically detect
the video standard and process it accordingly.

The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to tuner SAW filter.

The SDP has specific luminance and chrominance parameter

trol for brightness, contrast, saturation, and hue.

con

The ADV7401 implements a patented adaptive-digital-line­len

gth-tracking (ADLLT) algorithm to track varying video
line lengths from sources such as a VCR. ADLLT enables the
ADV7401 to track and decode poor quality video sources
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The SDP also contains a chroma transient
improvement (CTI) processor. This processor increases the
edge rate on chroma transitions, resulting in a sharper
video image.

The SDP can process a variety of VBI data services, such as

leText, closed captioning (CC), wide screen signaling (WSS),

Te
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS),
Gemstar 1×/2×, and extended data service (XDS). The
ADV7401 SDP section has a Macrovision 7.1 detection circuit
that allows it to detect Types I, II, and III protection levels. The
decoder is also fully robust to all Macrovision signal inputs.

COMPONENT PROCESSOR

The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1250i, VGA up to SXGA @ 75 Hz (ADV7401KSTZ-140
only), and many other standards not listed here.

The CP section of the ADV7401 contains an AGC block.

en no embedded sync is present, the video gain can be set

Wh
manually. The AGC section is followed by a digital clamp
circuit that ensures the video signal is clamped to the correct
blanking level. Automatic adjustments within the CP include
gain (contrast) and offset (brightness); manual adjustment
controls are also supported.

A fully programmable, any-to-any, 3 × 3 color space conversion

rix is placed between the analog front end and the CP

mat
section. This enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standards of color space can be
implemented using the color space converter.

The SDP has a 5-line superadaptive 2D comb filter that gives
sup

erior chrominance and luminance separation when decod­ing a composite video signal. This highly adaptive filter auto­matically adjusts its processing mode according to video
standard and signal quality with no user intervention required.

Rev. SpA | Page 15 of 20

ADV7401

www.BDTIC.com/ADI

The output section of the CP is highly flexible. It can be config­ured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edges of the clock. In SDR
mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these
modes HS, VS, and FIELD/DE (where applicable) timing refer­ence signals are provided. In DDR mode, the ADV7401 can be
configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb
pixel output interface with corresponding timing signals.

The ADV7401 is capable of supporting an external DVI/
HDMI r
16-bit 4:2:2 bit data (either graphics RGB or component video
YCrCb), accompanied by HS, VS, DE, and a fully synchronous
clock signal. The data is processed in the CP and output as
16-bit 4:2:2 YCrCb data.

eceiver. The digital interface expects 24-bit 4:4:4 or

The CP section contains circuitry to enable the detection of
Ma

crovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.

VBI extraction of CGMS data is performed by the CP section
of

the ADV7401 for interlaced, progressive, and high definition

scanning rates. The data extracted can be read back over the

2

I

C interface. For more detailed product information about the
ADV7401, contact your local ADI sales office or email

[e-mail].

Rev. SpA | Page 16 of 20

ADV7401

www.BDTIC.com/ADI

PIXEL INPUT/OUTPUT FORMATTING

Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)

Processor, Format, Pixel Port Pins P[19:0]
and Mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDP

Video out, 8-bit,
4:2:2

SDP

Video out,
16-bit, 4:2:2

SDP

Video out,
24-bit, 4:4:4

SM-SDP

Digital tuner

input[1]
CP 8-bit, 4:2:2, DDR D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - - - - ­CP

12-bit, 4:4:4, RGB

D7 D6 D5 D4 D3 D2 D1 D0 - - D11 D10 D9 D8 - - - - - -

DDR
CP

Video out,

CHA[7:0]

16-bit, 4:2:2
CP

Video out,

CHA[7:0]

24-bit, 4:4:4
SM-CP

HDMI receiver

CHA[7:0]
support, 24-bit,
4:4:4 input

SM-CP

HDMI receiver

CHA[7:0]
support, 16-bit,
pass-through

Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)

Processor, Format, Pixel Port Pins P[40:31], P[29:20]
and Mode 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20

SDP

Video out, 8-bit,

- - - - - - - - - - - - - - - - - - - -

4:2:2

SDP

Video out, 16-bit,

- - - - - - - - - - - - - - - - - - - -

4:2:2

SDP

Video out, 24-bit,

- - - - - - - - - - Cr[7:0]

4:4:4

SM-SDP

Digital tuner
input[1]

CP 8-bit, 4:2:2, DDR - - - - - - - - - - - - - - - - - - - -

YCrCb[7:0]

Y[7:0]

OUT

Y[7:0]

OUT

OUT

- - - - - - - - - - - -

- - CrCb[7:0]

- - Cb[7:0]

Output choices are the same as video out 16-bit or pseudo 8-bit DDR

(for example, Y[7:0]) - - CHB/C[7:0]

OUT

(for example, G[7:0]) - - CHB[7:0]

OUT

(for example, Y[7:0]) R[5:4]

OUT

(for example, Y[7:0]) - - CHB/C[7:0]

OUT

DCVBS[7:0]

IN

IN

- - - - - - - - - - - -

CHB/C[7:0]

(for example, Cr/Cb[7:0]) - -

OUT

(for example, B[7:0]) - -

OUT

(for example, Cr/Cb[7:0]) R[1:0]

OUT

(for example, Cr/Cb[7:0]) - -

OUT

OUT

OUT

OUT

- -

- -

IN

- -

CP

12-bit, 4:4:4, RGB

- - - - - - - - - - - - - - - - - - - -

DDR

CP

Video out, 16-bit,

- - - - - - - - - - - - - - - - - - - -

4:2:2

CP

Video out, 24-bit,

- - - - - - - - - - CHC[7:0]

4:4:4 input

SM-CP

HDMI receiver

G[7:0]

IN

support, 24-bit,
4:4:4 input

SM-CP

HDMI receiver

CHA[7:0]

IN

support, 16-bit,
pass-through

Rev. SpA | Page 17 of 20

(for example, R[7:0]) - -

OUT

R[7:6]

IN

B[7:0]

- - CHB/C[7:0]

IN

IN

R[3:2]

IN

- -

ADV7401

www.BDTIC.com/ADI

RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS

The external loop filter components for the ELPF pin should
be placed as close as possible to the respective pins. Figure 8

he recommended component values.

shows t

PIN 46–ELPF

1.69kΩ

10nF

82nF

PVDD = 1.8V

Figure 8. ELPF Components

05340-007

Rev. SpA | Page 18 of 20

ADV7401

T

www.BDTIC.com/ADI

TYPICAL CONNECTION DIAGRAM

LLC1

HSVSFIELD

HS_IN

VS_IN

Ω

Ω

100

100

4

99

HS

RESET

SFL/SYNC_OU

Ω

Ω

Ω

Ω

33

100

100

100

10kΩ

DVDDIO

K1

98

86

85

15

SFL/SYNC_OUT

D1

K2

BAT54C

DVSS

89

DVSS

40

DVSS

11

DVSSIO

17

DGND

DVSSIO

5

PVSS

50

PVSS

49

AVSS

AGND

60

AVSS

66

TEST0

70

BZX399-C3V3



VS

FIELD

VREF/VS_IN

HREF/HS_IN

FB

TEST1

51

59

DVDD_1.8V

DVDDIO

VP[00:41]

VP0341

VP0242

VP0143

SCLK

VP0626

Ω

33

10nF

VP0527

Ω

33

SDA2

1.69kΩ

1

47pF

1

47pF

VP0044

VP0428

Ω

Ω

Ω

Ω

Ω

Ω

33

33

33

33

33

100

36

P0

LLC1

SCLK2

ALSB

RESET

100Ω

100Ω

SDA

SCLK

DGND

5.6kΩ

VP4179

VP4083

VP3984

VP3887

VP3788

VP3695

VP3596

VP3497

VP33100

VP321

VP312

VP303

VP2913

VP2814

VP2724

VP2629

VP2530

VP2431

VP2332

VP2233

VP2134

VP2045

VP1991

VP1892

VP1793

VP1694

VP157

VP148

VP139

VP1210

VP1120

VP1021

VP0922

VP0823

VP0725

DCLCK_IN

Ω

Ω

Ω

Ω

Ω

Ω

Ω

33

33

33

33

33

33

33

P40

P39

P38

P37

P36

DE_IN

DVDDIO

18

DVDDIO

DVDDIO

10nF

F

μ

0.1

10nF

DGND

F

μ

0.1

U1 BYPASS CAPACITORS

10nF

F

μ

0.1

10nF

F

μ

0.1

U1 BYPASS CAPACITORS

DGND

10nF

F

μ

0.1

6

DVDD

90

DVDD

39

DVDD

12

DVDD_1.8V

PVDD_1.8V

AVDD

63

AVDD_3.3V

PVDD

48

PVDD

47

SOG

AIN1

AIN2

AIN3

U1

C94 1nF

AIN4

525456587274767771737553555769686261656467

INT

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

Ω

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

33

35

INT

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P35

P34

P33

P32

P31

DCLK_IN

P14

33

33

33

P13

P12

P11

Ω

33

33

33

33

P9P8P7P6P5P4P3P2P1

P10

ADV7401

AIN5

AIN6

SOY

AIN10

AIN11

AIN12

AIN7

AIN8

AIN9

CAPC2

CAPC1

CAPY2

CAPY1

CML

REFOUT

BIAS

XTAL

XTAL1

ELPF

2.7k

Ω

2.7k

Ω

F

μ

10

+

C22 1nF

10nF

F10

μ

0.1
F

μ

F

μ

F10

μ

0.1

0.1
F

μ

AGND

+

10nF

F10

μ

0.1
F

μ

F

F

μ

μ

0.1

0.1

AGND

AGND

SDA

383746818219168078

82nF

PVDD_1.8V

Y2

1MΩ

28.63636MHz

DVDDIO

10nF

AGND

F

μ

PVDD_1.8V

0.1

AGND

10nF

F

AVDD_3.3V

μ

0.1

U1 BYPASS CAPACITORS

AGND

0.1μF

0.1μF

0.1μF

0.1μF

0.1μF

0.1μF

56

Ω

75

Ω

75

Ω

75

Ω

75

Ω

75

Ω

75

Ω

75

Ω

75

Ω

75

Ω

GREEN

BLUE

RED

HS_IN

VS_IN

P5–2

P5–3

P5–1

P5–13

P5–14

Pr/Pb

13521246

PHONO3

AGND

P6–5

P6–6

P5–7

P5–8

P5–10

AGND

Pb/Pr

Y

P7

P4

SCART_21_PIN

0.1μF

0.1μF

0.1μF

RED/C

GREEN

F_BLNK

BLUE

16211

15

201918171615141312111098765432

19Ω

CVBS/Y
20

0.1μF

0.1μF

19Ω

Y

C

AGND

132

4

21

43

S-VIDEO

1

P8

MINI-DIN-4

0.1μF

19Ω

CVBS

56Ω

P9

AGND

LOAD CAP VALUES ARE DEPENDANT ON CRYSTAL ATTRIBUTES

1

RGB

GRAPHICS

Figure 9. ADV7401

05340-009

Rev. SpA | Page 19 of 20

ADV7401

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

VIEW A

ROTATED 90° CCW

SEATING
PLANE

1.60 MAX

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.08
COPLANARITY

25

VIEW A

1

26

16.20

16.00 SQ

15.80

PIN 1

TOP VIEW

(PINS DOWN)

0.50
BSC

LEAD PITCH

0.27

0.22

0.17

76100

75

14.20

14.00 SQ

13.80

51

50

COMPLIANT TO JEDEC STANDARDS MS-026-BED

051706-A

Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADV7401BSTZ-802

ADV7401BSTZ-1102

−40°C to +85°C

−40°C to +85°C

ADV7401KSTZ-1402 0°C to 70°C 100-Lead Low Profile Quad Flat Package (LQFP) ST-100
EVAL-ADV7401EBM Evaluation Board

1

The ADV7401 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each

device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255°C (±5°C). In addition,
it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at
conventional reflow temperatures of 220°C to 235°C.

2

Z = Pb-free part.

100-Lead Low Profile Quad Flat Package (LQFP) ST-100

100-Lead Low Profile Quad Flat Package (LQFP) ST-100

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05340–0–9/05(SpA)

Rev. SpA | Page 20 of 20