Analog Devices ADV7330 b Datasheet

Multiformat 11-Bit

H

B

Triple DAC Video Encoder

ADV7330

FEATURES
High Definition Input Formats
8-Bit or 16-Bit (4:2:2) Parallel YCrCb Compliant with:

SMPTE 293M (525p)
BTA T-1004 EDTV2 525p
ITU-R BT.1358 (525p/625p)
ITU-R BT.1362 (525p/625p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
Other High Definition Formats Using Async

Timing Mode

High Definition Output Formats

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision

®

Rev 1.1 (525p/625p)

CGMS-A (525p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-Bit or 16-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning

GENERAL FEATURES
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference
Three 11-Bit Precision Video DACs
2-Wire Serial I

2C®

Interface, Open Drain Configuration
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product

APPLICATIONS
SD/PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

STANDARD DEFINITION

Y7–Y0
C7–C0

SYNC_I/P

VSYNC_I/P

LANK_I/P

CLKIN

D
E
M
U
X

TIMING

GENERATOR

PLL

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

ADV7330

11-BIT

O
V

DAC
E
R
S

11-BIT

A

DAC

M
P
L

I

11-BIT

N

DAC
G

I2C

INTERFACE

GENERAL DESCRIPTION

The ADV®7330 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes three high speed video D/A
converters with TTL compatible inputs.

The ADV7330 has separate 8-bit or 16-bit input ports that
accept data in high definition or standard definition video
format. For all standards, external horizontal, vertical, and
blanking signals or EAV/SAV timing codes control the inser­tion of appropriate synchronization signals into the digital
data stream and therefore the output signal.

Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADV7330

DETAILED FEATURES
High Definition Programmable Features (720p/1080i)

2 Oversampling (148.5 MHz)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control

CGMS-A (720p/1080i)

Programmable Features (525p/625p)

8 Oversampling
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB/Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)

Standard Definition Programmable Features

16 Oversampling
Internal Test Pattern Generator

(Colorbars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable

Gain/Attenuation
PrPb SSAF™
Separate Pedestal Control on Component and

Composite/S-Video Outputs
VCR FF/RW Sync Mode

Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning

Standards Directly Supported

Frame Clk

Resolution Rate (Hz) Input (MHz) Standard

720  480 29.97 27 ITU-R BT.656
720  576 25 27 ITU-R BT.656
720  483 59.94 27 SMPTE 293M
720  480 59.94 27 BTA T-1004
720  576 50 27 ITU-R BT.1362
1280  720 60 74.25 SMPTE 296M
1920  1080 30 74.25 SMPTE 274M
1920  1080 25 74.25 SMPTE 274M*

Other standards are supported in Async Timing Mode.
*SMPTE 274M-1998: System No. 6

HSYNC
VSYNC
BLANK

CLKIN

SD/PS/HD

PIXEL INPUT

DEINTER-

LEAVE

DEINTER-

LEAVE

DETAILED FUNCTIONAL BLOCK DIAGRAM

Y

TEST

CR

PATTERN

CB

CB

TEST

CR

PATTERN

Y

TIMING

GENERATOR

SHARPNESS

AND

ADAPTIVE

FILTER

CONT

ROL

DNR

GAMMA

Y COLOR
CR COLOR
CB COLOR

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

INSERTION

4:2:2

TO

4:4:4

SYNC

U

UV SSAF

V

LUMA

CHROMA

FILTERS

AND

2 OVER-

SAMPLING

RGB

MATRIX

F

SC

MODULATION

CGMS

WSS

PS 8

HDTV 2

SD 16

DAC

DAC

DAC

REV. B–2–

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11

THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 11

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 13

REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 14

INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 27

Standard Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Progressive Scan or HDTV Mode . . . . . . . . . . . . . . . . . . 27

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 27

OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 28

TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 29

HD Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SD Real-Time Control, Subcarrier Reset, Timing Reset . 31

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 33

SD Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . 33

Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 35

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 36

COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 40

HD Y Level, Cr Level, Cb Level . . . . . . . . . . . . . . . . . . . 40

HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 40

SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 42

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

ADV7330

HD SHARPNESS FILTER CONTROL AND

ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . . . 44

HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . . 44

HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . 44

HD Sharpness Filter and Adaptive Filter Application

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

ADAPTIVE FILTER CONTROL APPLICATION . . . . . . 46

SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . 47

Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . 48

DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . 48

SAV/EAV STEP EDGE CONTROL . . . . . . . . . . . . . . . . . 48

BOARD DESIGN AND LAYOUT CONSIDERATIONS . 50

DAC Termination and Layout Considerations . . . . . . . . 50

VIDEO OUTPUT BUFFER AND OPTIONAL

OUTPUT FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 51

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 52

Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX 1—COPY GENERATION

MANAGEMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . 53

HD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . 53

SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 53

HD CGMS Data Registers . . . . . . . . . . . . . . . . . . . . . . . 53

Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 53

APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . . 55

APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . . 56

APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . . 57

APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . . 60

Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . . 60

Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . . 61

Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 63

Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 65

Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 66

APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . . 67

APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . . 68

HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 68

RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . . 74

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 76

REV. B

–3–

ADV7330–SPECIFICATIONS

(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; V
V

= 1.235 V, R

REF

= 3040 , R

SET

= 300 . All specifications T

LOAD

= 2.375 V to 3.6 V,

DD_IO

MIN

to T

MAX

(0C to 70C), unless otherwise noted.)

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE

1

(With No Oversampling Ratio)
Resolution 11 Bits
Integral Nonlinearity 1.5 LSB
Differential Nonlinearity

2

, +ve 0.5 LSB

Differential Nonlinearity2, –ve 1.0 LSB

DIGITAL OUTPUTS

Output Low Voltage, V

OL

Output High Voltage, V

OH

2.4 [2.0]

3

0.4 [0.4]

Three-State Leakage Current ±1.0 µAV

3

VI
VI

SINK

SOURCE

= 0.4 V, 2.4 V

IN

= 3.2 mA

= 400 µA

Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V
Input Low Voltage, V

IH

IL

Input Leakage Current 3 µAV
Input Capacitance, C

IN

2V

0.8 V
= 2.4 V

IN

2pF

ANALOG OUTPUTS

Full-scale Output Current 4.1 4.33 4.6 mA
Output Current Range 4.1 4.33 4.6 mA
DAC to DAC Matching 1.0 %
Output Compliance Range, V
Output Capacitance, C

OC

OUT

0 1.0 1.4 V

7pF

VOLTAGE REFERENCE

Internal Reference Range, V
External Reference Range, V
V

Current

REF

4

REF

REF

1.15 1.235 1.3 V

1.15 1.235 1.3 V

±10 µA

POWER REQUIREMENTS
Normal Power Mode

I

DD

5

170 190

6

mA SD (16×)
110 mA PS (8×)
95 mA HDTV (2×)

I

DD_IO

I

AA

7, 8

1.0 mA
24 28 mA

Sleep Mode

I

DD

I

AA

I

DD_IO

200 µA
10 µA
250 µA

Power Supply Rejection Ratio 0.01 %/%

NOTES

1

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

2

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.

3

Value in brackets for V

4

External current required to overdrive internal V

5

IDD, the circuit current, is the continuous current required to drive the digital core.

6

Guaranteed maximum by characterization.

7

IAA is the total current required to supply all DACs including the V

8

All DACs on.

Specifications subject to change without notice.

= 2.375 V to 2.75 V.

DD_IO

REF

.

circuitry and the PLL circuitry.

REF

REV. B–4–

ADV7330

(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; V

DYNAMIC SPECIFICATIONS

Parameter Min Typ Max Unit Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz
Chroma Bandwidth 5.8 MHz
SNR 65.6 dB Luma ramp unweighted

HDTV MODE

Luma Bandwidth 30 MHz
Chroma Bandwidth 13.75 MHz

STANDARD DEFINITION MODE

Hue Accuracy 0.4 Degrees
Color Saturation Accuracy 0.4 %
Chroma Nonlinear Gain 1.2 ±%Referenced to 40 IRE
Chroma Nonlinear Phase –0.2 ± Degrees
Chroma/Luma Intermodulation 0 ±%
Chroma/Luma Gain Inequality 97.0 ±%
Chroma/Luma Delay Inequality –1.1 ns
Luminance Nonlinearity 0.5 ±%
Chroma AM Noise 84 dB
Chroma PM Noise 75.2 dB
Differential Gain 0.20 % NTSC
Differential Phase 0.15 Degrees NTSC
SNR 59.1 dB Luma ramp

Specifications subject to change without notice.

R

= 3040 , R

SET

= 300 . All specifications T

LOAD

72 dB Flat field full bandwidth

77.7 dB Flat field full bandwidth

MIN

= 2.375 V to 3.6 V, V

DD_IO

to T

(0C to 70C), unless otherwise noted.)

MAX

REF

= 1.235 V,

REV. B

–5–

ADV7330

TIMING SPECIFICATIONS

(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; V
R

= 3040 , R

SET

= 300 . All specifications T

LOAD

= 2.375 V to 3.6 V, V

DD_IO

to T

MIN

(0C to 70C), unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Conditions

MPU PORT

1

SCLOCK Frequency 0 400 kHz
SCLOCK High Pulsewidth, t
SCLOCK Low Pulsewidth, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t

5

SDATA, SCLOCK Rise Time, t
SDATA, SCLOCK Fall Time, t
Setup Time (Stop Condition), t

1

2

3

4

6

7

8

0.6 µs

1.3 µs

0.6 µs After this period, the first clock is generated

0.6 µsRelevant for repeated start condition
100 ns

300 ns
300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

2

7ns

Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT

f

CLK

f

CLK

Clock High Time, t
Clock Low Time, t
Data Setup Time, t
Data Hold Time, t
SD Output Access Time, t
SD Output Hold Time, t
HD Output Access Time, t
HD Output Hold Time, t

PIPELINE DELAY

9

10

1

11

1

12

13

14

13

14

4

3

27 MHz Progressive scan mode

81 MHz HDTV mode/async mode
40 % of one clk cycle
40 % of one clk cycle

2.0 ns

2.0 ns

15 ns

5.0 ns

14 ns

5.0 ns

63 clk cycles SD (2×, 16×)

76 clk cycles SD component mode (16×)

35 clk cycles PS (1×)

41 clk cycles PS (8×)

36 clk cycles HD (2×, 1×)

NOTES

1

Guaranteed by characterization.

2

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of the DAC output full-scale transition.

3

Data: C [9:0]; Y [9:0], S[9:0].
Control: HSYNC_I/P, VSYNC_I/P, BLANK_I/P, HSYNC_O/P , VSYNC_O/P, BLANK_O/P.

4

SD, PS = 27 MHz, HD = 74.25 MHz.

Specifications subject to change without notice.

= 1.235 V,

REF

REV. B–6–

CLKIN

ADV7330

CONTROL

INPUTS

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Figure 1. HD/PS 4:2:2 Input Mode (HD: Input Mode 010) (PS: Input Mode 001)

CONTROL

INPUTS

HSYNC_I/P
VSYNC_I/P
BLANK_I/P

Y7–Y0

C7–C0

HSYNC_O/P
VSYNC_O/P
BLANK_O/P

CLKIN

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

t

t

9

10

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

t

11

t

9

t12

t

13

t

14

t

10

Cb0 Y0 Y1 Crxxx YxxxCr0

t

12

t

11

t

12

t

11

t

13

t

14

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Y7–Y0

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

Figure 2. PS 4:2:2 1× 8-Bit Interleaved at 27 MHz Hsync/Vsync Input Mode (Input Mode 100)

REV. B

–7–

ADV7330

CLKIN

t

9

t

10

3FF 00 XY Cb0* Y0 Cr0 Y100

t

12

t

11

*Y0, Cb, SEQUENCE AS PER SUBADDRESS 01h BIT 1

t

12

t

11

t

14

t

13

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Y7–Y0

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

Figure 3. PS 4:2:2 1× 8-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)

CLKIN

t9

t10

CONTROL

INPUTS

CONTROL

OUTPUTS

HSYNC_I/P
VSYNC_I/P
BLANK_I/P

Y7–Y0

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

t11

Cb0 Y0 Cr2 Y1 Cbxxx Cbxxx

t

12

t13

t

14

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

Figure 4. PS 4:2:2 1× 8-Bit Interleaved at 54 MHz Hsync/Vsync I/P Mode (Input Mode 011)

CLKIN

Y7–Y0

CONTROL

OUTPUTS

t

= CLOCK HIGH TIME

9

t

= CLOCK LOW TIME

10

t

= DATA SETUP TIME

11

t

= DATA HOLD TIME

12

t

9

t

10

3FF 00 00 XY Cb0 Y0 Cr0 Y1

t

12

t

11

t

13

t

14

Figure 5. PS 4:2:2 1× 8-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 011)

REV. B–8–

CONTROL

H

B

INPUTS

CLKIN

HSYNC_I/P
VSYNC_I/P
BLANK_I/P

ADV7330

t

t

t

10

9

12

IN SLAVE MODE

CONTROL

OUTPUTS

CONTROL

INPUTS

CONTROL

OUTPUTS

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

CLKIN

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

Y7–Y0

C7–C0

HSYNC_O/P
VSYNC_O/P
BLANK_O/P

SYNC_I/P

VSYNC_I/P

Y7–Y0

Cb Y

Cr

t

11

YCbY

t

13

t

14

Figure 6. 8-Bit SD Pixel Input Mode (Input Mode 000)

t

t

t

10

9

Y0

Cb0

12

Y1

Cr0

t

11

Y2

Cb2

t

13

t

14

Figure 7. 16-Bit SD Pixel Input Mode (Input Mode 000)

Y3

Cr2

IN MASTER/SLAVE
MODE

IN SLAVE MODE

IN MASTER/SLAVE
MODE

A

LANK_I/P

Y7–Y0

C7–C0

B

A = 16 CLK CYCLES FOR 525p
A = 12 CLK CYCLES FOR 626p
A = 44 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
A = 70 CLK CYCLES FOR 720p
AS RECOMMENDED BY STANDARD

B (MIN) = 122 CLK CYCLES FOR 525p
B (MIN) = 132 CLK CYCLES FOR 625p
B (MIN) = 236 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
B (MIN) = 300 CLK CYCLES FOR 720p

Y0 Y1

Cb0 Cr0

Y2 Y3

Cr1 Cb1

Figure 8. HD 4:2:2 Input Timing Diagram

REV. B

–9–

ADV7330

H

B

B

H

SYNC_I/P

VSYNC_I/P

A

LANK_I/P

Y7–Y0

A = 32 CLK CYCLES FOR 525p
A = 24 CLK CYCLES FOR 626p
AS RECOMMENDED BY STANDARD

Figure 9. PS 4:2:2, 1 × 8-Bit Interleaved Input Timing Diagram

SYNC_I/P

VSYNC_I/P

PAL = 24 CLK CYCLES

NTSC = 32 CLK CYCLES

LANK_I/P

Y7–Y0

*SELECTED BY ADDRESS 44h BIT 7

Figure 10. SD Timing Input for Timing Mode 1

t

3

SDA

B

B (MIN) = 244 CLK CYCLES FOR 525p
B (MIN) = 264 CLK CYCLES FOR 625p

PAL = 264 CLK CYCLES
NTSC = 244 CLK CYCLES

t

5

t

3

Cb Y

Cb Y

Cr Y

Cr Y

t

1

t

7

t

4

t

8

SCLK

t

6

t

2

Figure 11. MPU Port Timing Diagram

REV. B–10–

ADV7330

ABSOLUTE MAXIMUM RATINGS

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.0 V

AA

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.0 V

V

DD

V

to GND_IO . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

DD_IO

Digital Input Voltage to DGND . . . . –0.3 V to V

to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

V

AA

1, 2

DD_IO

+ 0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DGND to GND_IO . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to GND_IO . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Ambient Operating Temperature (T

) . . . . . . . . 0°C to 70°C

A

Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C

Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . . 260°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational section
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.

2

Analog output short circuit to any power supply or common can be of an indefinite
duration.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7330KST 0°C to 70°CLow Profile Quad Flat Package ST-64-2

THERMAL CHARACTERISTICS

␪JC = 11°C/W

= 47°C/W

␪

JA

The ADV7330 is a Pb-free, environmentally friendly product. It is
manufactured using the most up-to-date materials and processes.
The coating on the leads of each device is 100% pure Sn electro­plate. The device is suitable for Pb-free applications, and is able
to withstand surface-mount soldering at up to 255°C (±5°C).

In addition, it is backward compatible with conventional SnPb
soldering processes. This means that the electroplated Sn coating
can be soldered with Sn/Pb solder pastes at conventional reflow
temperatures of 220°C to 235°C.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7330 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. B

–11–

ADV7330

P

P

PIN CONFIGURATION

GND_IO

TEST14

TEST13

TEST12

TEST11

TEST10

TEST9

DGND

VDDTEST8

TEST7

TEST6

TEST5

TEST4

HSYNC_O/

VSYNC_O/P

49505152535455565758596061626364

1

V

DD_IO

2

TEST0

3

TEST1

4

Y0

5

Y1

6

Y2

7

Y3

8

Y4

9

Y5

10

V

DD

11

DGND

Y6

12

Y7

13

TEST2

14

TEST3

15

C0

16

NC = NO CONNECT

PIN 1
IDENTIFIER

2

C1

C2

C
I

ALSB

SDA

ADV7330

TOP VIEW

(Not to Scale)

SCLK

VSYNC_I/P

BLANK_I/P

HSYNC_I/P

C3C4C5C6C7

48

BLANK_O/

47

TEST16

46

V

REF

45

TEST15

44

NC

43

NC

42

NC

41

V

AA

40

AGND

39

DAC A

38

DAC B

37

DAC C

36

COMP

35

R

SET

34

EXT_LF

33

RESET

32313029282726252423222120191817

CLKIN

RTC_SCR_TR

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic I/O Function

11, 57 DGND G Digital Ground.

2, 3, 14, 15, TEST0–TEST14 I Not used, tie to DGND.
51–55, 58–63

40 AGND G Analog Ground.

32 CLKIN I Pixel Clock Input for HD (74.25 MHz Only, PS (27 MHz), SD (27 MHz)).
36 COMP O Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V

AA

.

39 DAC A O CVBS/GREEN/Y Analog Output.

38 DAC B O Chroma/BLUE/Pb Analog Output.

37 DAC C O Luma/RED/Pr Analog Output.
25 BLANK_I/P IVideo Blanking Control Signal. For HD and PS, this input is active high. For SD

input, this input is active low.

23 HSYNC_I/P IVideo Horizontal Sync Control Signal.
24 VSYNC_I/P IVideo Vertical Sync Control Signal.

4–9, 12, 13 Y7–Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved

progressive scan data. The LSB is set up on Pin Y0.

16–18, 26–30 C7–C0 I 8-Bit SD/Progressive Scan/HDTV Input Port. The LSB is set up on Pin C0.
33 RESET IThis input resets the on-chip timing generator and sets the ADV7330 into the default

register setting. Reset is an active low signal.

35 R

SET

IA 3040 Ω resistor must be connected from this pin to AGND and is used to control

the amplitudes of the DAC outputs.

22 SCLK I I

21 SDA I/O I

20 ALSB I TTL Address Input. This signal sets up the LSB of the I

1V

DD_IO

PPower Supply for Digital Inputs and Outputs.

2

C Port Serial Interface Clock Input.

2

C Port Serial Data Input/Output.

2

tied low, the I

C filter is activated, which reduces noise on the I2C interface.

2

C address. When this pin is

REV. B–12–

ADV7330

PIN FUNCTION DESCRIPTIONS (continued)

Pin Number Mnemonic I/O Function

10, 56 V

41 V

DD

AA

45, 47 TEST15, TEST16 O Not used, do not connect.

34 EXT_LF I External Loop Filter for the Internal PLL.

31 RTC_SCR_TR I Multifunctional Input: Real-Time Control (RTC) Input, Timing Reset Input,

48 BLANK_O/P O Video Blanking Control Signal. For HD and PS, this input is active high. For SD input,

50 HSYNC_O/P OVideo Horizontal Sync Control Signal.
49 VSYNC_O/P OVideo Vertical Sync Control Signal.

19 I

2

CIThis input pin must be tied high (V

64 GND_IO Digital Input/Output Ground.

42–44 NC No Connect.

46 V

TERMINOLOGY

REF

SD Standard definition video, conforming to ITU-R

BT.601/656.
HD High definition video, such as progressive scan or HDTV.
PS Progressive scan video, conforming to SMPTE 293M,

ITU-R BT.1358, BTA T-1004EDTC2, BTA1362

PDigital Power Supply.

PAnalog Power Supply.

Subcarrier Reset Input.

this output is active low.

) for the ADV7330 to interface over the I2C port.

DD_IO

I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output

(1.235 V).

HDTV High definition television video, conforming to SMPTE

274M or SMPTE 296M.
YCrCb SD, PS, or HD component digital video.
YPrPb SD, PS, or HD component analog video.

MPU PORT DESCRIPTION

The ADV7330 supports a 2-wire serial (I2C compatible) micro­processor bus driving multiple peripherals. This bus operates
in an Open Drain configuration. Two inputs, serial data
(SDA) and serial clock (SCL), carry information between any
devices connected to the bus. Each slave device is recognized by a
unique address. The ADV7330 has four possible slave ad­dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 12. The
LSB sets either a read or write operation. Logic 1 corresponds to
a read operation, while Logic 0 corresponds to a write operation.
A1 is set by setting the ALSB pin of the ADV7330 to Logic 0
or Logic 1. When ALSB is set to 1, there is greater input band­width on the I
on this bus. When ALSB is set to 0, there is reduced input
bandwidth on the I
than 50 ns will not pass into the I

2

C lines, which allows high speed data transfers

2

C lines, which means that pulses of less

2

C internal controller. This

mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 12. ADV7330 Slave Address = D4h

To control the various devices on the bus, the following proto­col must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA, while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are transferred from MSB down to LSB. The periph­eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known as
an acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
when the device monitors the SDA and SCL lines waiting for the
start condition and the correct transmitted address. The R/W
bit determines the direction of the data.

A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.

The ADV7330 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the device
address and the second byte as the starting subaddress. There
is a subaddress auto-increment facility. This allows data to be
written to or read from registers in ascending subaddress
sequence, starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.

REV. B

–13–

ADV7330

Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition.
If an invalid subaddress is issued by the user, the ADV7330 will
not issue an acknowledge and will return to the idle condition.
If in auto-increment mode the user exceeds the highest subaddress,
the following action will be taken:

1. In read mode, the highest subaddress register contents will
continue to be output until the master device issues a no
acknowledge. This indicates the end of a read. A no acknowl­edge condition is when the SDA line is not pulled low on the
ninth pulse.

2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no acknowledge will be issued
by the ADV7330, and the part will return to the idle condition.

Before writing to the subcarrier frequency registers, it is a require­ment that the ADV7330 reset at least once after power-up.

The four subcarrier frequency registers must be updated starting
with subcarrier frequency register 0 through subcarrier frequency
register 3. The subcarrier frequency will not update until the

last subcarrier frequency register byte has been received by
the ADV7330.

Figure 13 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 14 shows
bus write and read sequences.

REGISTER ACCESS

The MPU can write to or read from all of the registers of the
ADV7330 except the subaddress registers that are write-only
registers. The subaddress register determines which register the
next read or write operation accesses. All communications with
the part go through the bus start with an access to the subaddress
register. Then a read/write operation is performed from/to the
target address, which then increments to the next address until
a stop command on the bus is performed.

Register Programming

The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless other­wise stated.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write-only register. After
the part has been accessed over the bus and a read/write operation
is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.

WRITE

SEQUENCE

READ

SEQUENCE

SDATA

SCLOCK

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

9S1–7 8 9

1–7

89

P

Figure 13. Bus Data Transfer

S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P

LSB = 0

S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT
P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER

LSB = 1

A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER

Figure 14. Write and Read Sequence

REV. B–14–

ADV7330

p

p

SR7–

Register Bit Description

SR0

00h Power Mode Sleep Mode. With this control

01h Input Mode 0Disabled

enabled, the current consumption is
reduced to µA level. All DACs and the
internal PLL cct are disabled. I
registers can be read from and written
to in sleep mode.

PLL and Oversampling Control. This
control allows the internal PLL cct to
be powered down and the over­sampling to be switched off.

DAC C. Power On/Off. 0 DAC C Off

DAC B. Power On/Off. 0 DAC B Off

DAC A. Power On/Off. 0

BTA T-1004 or BT 1362
Compatibility.

Clock Edge 0

Reserved 0
Reserved 0

ut Mode 0 0 0 SD Input 38h

In

Reserved 0

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit

2

C

1 DAC B On

xxx

001 PS Input
010 HDTV Input
011 PS 54 MHz In
100 PS 27 MHz Input
101 Reserved
110 Reserved

111 Reserved

1 DAC A On

Register Setting

0

Sleep Mode Off FCh

0

1 Sleep Mode On

PLL On

0

1 PLL Off

1 DAC C On

DAC A Off

1Enabled

Cb Clocked on Rising
Edge

1Y Clocked on Rising Edge

Register Reset
Values (Shaded)

Reserved

Only for PS dual­edge clk mode

Only for PS
interleaved input at
27 MHz

ut

REV. B

–15–

ADV7330

y

p

p

SR7–

Register Bit Description Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Register Setting Reset Values

SR0

02h Mode Register 0 Reserved 00 Zero must be written

Test Pattern Black Bar 0

RGB Matrix 0 Disable

Sync on RGB

RGB/YUV Output 0 RGB component

SD Sync 0 No Sync Output

HD Sync

03h RGB Matrix 0
04h RGB Matrix 1 x x LSB for RV F0h

05h RGB Matrix 2 x x x x x x x x Bit 9–2 for GY 4Eh
06h RGB Matrix 3 x x x x x x x x Bit 9–2 for GU

07h RGB Matrix 4 x x x x x x x x Bit 9–2 for GV 24h
08h RGB Matrix 5 x x x x x x x x Bit 9–2 for BU
09h RGB Matrix 6 x x x x x x x x Bit 9–2 for RV 7Ch
0Ah xx xx xx xxReserved
0Bh

DAC A,B,C Output Level

0Ch Reserved 00h
0Dh Reserved
0Eh Reserved
0Fh Reserved 00h

NOTES

1

For more detail, refer to Appendix 7.

2

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

2

Positive Gain to DAC Output Voltage 0 0 0 0 0 0 0 0 0% 00h

Negative Gain to DAC Output Voltage 1 1 0 0 0 0 0 0 –7.5%

1

1 Output SD Syncs on

0No Sync Output
1 Output HD Syncs on

xx LSB for GU

00 00 00 010.018%
00 00 00 100.036%

00 11 11 117.382%
01 00 00 007.5%

11 00 00 01–7.382%
10 00 00 10–7.364%

11 11 11 11–0.018%

0No S

1

1YUV component

xx LSB for GV

1 Enabled

1 Enable Programmable

xx

xx LSB for BU

to these bits

Disabled

Programmable RGB
Matrix

RGB Martix

nc

Sync on all RGB
Outputs

Out

uts

uts

Out

HSYNC_O/P,
VSYNC_O/P,
BLANK_O/P

HSYNC_O/P,
VSYNC_O/P,
BLANK_O/P

LSB for GY

………

… …….

20h

11h, Bit 2 must
also be enabled

03h

0Eh

92h

00h
00h

REV. B–16–

SR7–

g

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

SR0

10h HD Mode

Register 1

11h HD Mode

Register 2

HD Output Standard 0 0 EIA770.2 Output 00h

01EIA770.1 Output
10Output levels for Full Input

HD Input Control Signals 0 0

01 EAV/SAV codes
10 Async Timing Mode

HD 625p 0 525p

HD 720p 0 1080i

HD BLANK Polarity 0 BLANK Active High

HD Macrovision for 525p/625p 0 Macrovision Off

HD Pixel Data Valid 0 Pixel Data Valid Off 00h

HD Test Pattern Enable 0 HD Test Pattern Off

HD Test Pattern Hatch/Field 0 Hatch

HD VBI Open 0 Disabled

HD Undershoot Limiter 0 0 Disabled

HD Sharpness Filter 0 Disabled

1 Macrovision On

1 Enabled

1 720p

1 BLANK Active Low

01 –11 IRE
10 –6 IRE
11 –1.5 IRE

11 Reserved

1 625p

1 Field/Frame

1 Enabled

11Reserved

1 Pixel Data Valid On

0 Reserved

1 HD Test Pattern On

e

Ran

HSYNC, VSYNC, BLANK

ADV7330

Values

REV. B

–17–

ADV7330

y

y

y

;

SR7–

Register Bit Description Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Register Setting Reset

SR0

12h HD Mode Register 3 000

13h HD Mode Register 4

14h HD Mode Register 5

15h HD Mode Register 6

NOTES

1

When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are

HD Y Delay with respect to falling
edge of HSYNC

HD Color Delay with respect to
falling edge of HSYNC

HD CGMS 0 Disabled

HD CGMS CRC

HD Cr/Cb Sequence

Reserved 00 must be written to this bit.
Reserved 0 0 must be written to this bit.
Sinc Filter on DAC A, B, C

Reserved 0 0 must be written to this bit.
HD Chroma SSAF

Reserved
HD Double Buffering

HD Timing Reset

1080i Frame Rate

Reserved

HD Vsync/Field Input

Lines/Frame

Reserved

HD RGB Input

HD Sync on PrPb 0

HD Color DAC Swap 0 DAC E = Pr; DAC F = Pb

HD Gamma Curve A/B 0 Gamma Curve A

HD Gamma Curve Enable 0 Disabled

HD Adaptive Filter Mode 0

HD Adaptive Filter Enable 0

1

0
1 Enabled

0
1

0

1

1

00 0

00 1
01 0
01 13 Clk Cycles
10 0

1

0
1

1

00 0

0

1

1

1

1 Mode B

0011 Clk Cycle
010
0113 Clk Cycles
100

0
1 Enabled

00 30 Hz/2200 Total Samples/Line
01 25 Hz/2640 Total Samples/Line

0

1 Enabled

1 Enabled

1

0 Clk Cycle

2 Clk C

cles

4 Clk Cycles
0 Clk Cycle

1 Clk Cycle

cles

2 Clk C

4 Clk C

cles

Enabled
Disabled

0

Cb after Falling Edge of HSYNC

1

Cr after Falling Edge of HSYNC

Disabled

Disabled
Enabled

Disabled

Enabled

xA low-high-low transition resets the

internal HD timing counters.

0 must be written to these bits.

Field Input

Vsync Input

Update Field/Line Counter

Field/Line Counter Free Running

0

0 must be written to this bit.

Disabled

Disabled

DAC E = Pb

Gamma Curve B

Enabled
Mode A

Disabled
Enabled

DAC F = Pr

free running and wrap around when external sync signals indicate so.

Values

00h

4Ch

00h

00h

REV. B–18–

ADV7330

SR7–

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

SR0

16h HD Y Level
17h HD Cr Level
18h HD Cb Level
19h Reserved 00h
1Ah Reserved 00h
1Bh Reserved
1Ch Reserved 00h
1Dh Reserved
1Eh Reserved 00h
1Fh
20h HD Sharpness Filter HD Sharpness Filter Gain Value A

Gain

21h HD CGMS Data 0 HD CGMS Data Bits 0 0 0 0 C19 C18 C17 C16 CGMS 19–16 00h
22h HD CGMS Data 1 HD CGMS Data Bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS 15–8 00h
23h HD CGMS Data 2 HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7–0 00h
24h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A0 00h
25h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A1 00h
26h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A2 00h
27h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A3 00h
28h HD Gamma A
29h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A5 00h
2Ah HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A6 00h
2Bh HD Gamma A
2Ch HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A8 00h
2Dh HD Gamma A
2Eh HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B0 00h
2Fh HD Gamma B HD Gamma Curve B Data Points
30h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B2 00h
31h HD Gamma B HD Gamma Curve B Data Points
32h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B4 00h
33h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B5 00h
34h HD Gamma B HD Gamma Curve B Data Points
35h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B7 00h
36h HD Gamma B HD Gamma Curve B Data Points
37h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B9 00h

NOTES

1

For the internal test pattern only.

1

1

1

Reserved 00h

HD Sharpness Filter Gain Value B

HD Gamma Curve A Data Points x x x x x x x x

HD Gamma Curve A Data Points x x x x x x x x A7 00h

HD Gamma Curve A Data Points x x x x x x x x A9 00h

xxxxx
xxxxxxxxCr Color Value 80h
xxxxx

0000 Gain B = 0

00 1

0

.. .. .. .. …….

11 1

0
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

xxxxxxxxB1 00h

xxxxxxxxB3 00h

xxxxxxxxB6 00h

xxxxxxxx

xx x

xx x

0000Gain A = 0 00h

00 1

0

.. .. .. .. ……

0111Gain A = +7
1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

Setting

Y Color Value

Cb Color Value

Gain A = +1

Gain B = +1

Gain B = +7

A4 00h

B8 00h

Reset
Values

A0h

80h

00h

00h

REV. B

–19–

ADV7330

SR7­SR0

38h HD Adaptive Filter HD Adaptive Filter Gain 1

39h HD Adaptive Filter HD Adaptive Filter Gain 2

3Ah HD Adaptive Filter HD Adaptive Filter Gain 3

3Bh HD Adaptive Filter HD Adaptive Filter Threshold A

3Ch HD Adaptive Filter HD Adaptive Filter Threshold B

3Dh HD Adaptive Filter HD Adaptive Filter Threshold C

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

Gain 1 Value A

HD Adaptive Filter Gain 1
Value B

Gain 2 Value A

HD Adaptive Filter Gain 2
Value B

Gain 3 Value A

HD Adaptive Filter Gain 3
Value B

Threshold A Value

Threshold B Value

Threshold C Value

Setting

0000Gain A = 0
0001Gain A = +1

.. .. .. .. ……

0111Gain A = +7
1000Gain A = –8

.. .. .. .. ……

0000 Gain B = 0
0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0000 Gain B = 0
0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0000 Gain B = 0
0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7
1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1
xxxxxxxxThreshold A

xxxxxxxxThreshold B

xxxxxxxxThreshold C

1111Gain A = –1

0000Gain A = 0
0001Gain A = +1

.. .. .. .. ……

0111Gain A = +7
1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

0000Gain A = 0
0001Gain A = +1

.. .. .. .. ……

0111Gain A = +7
1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

Reset
Values

00h

00h

00h

00h

00h

00h

REV. B–20–

ADV7330

SR7–

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

SR0

3Eh Reserved 00h

3Fh Reserved 00h

40h SD Mode Register 0 SD Standard 0 0 NTSC 00h

SD Luma Filter 0 0 0 LPF NTSC

001 LPF PAL

010 Notch NTSC

011 Notch PAL

100

101

110

111

SD Chroma Filter 0 0 0

00 1

01 0

01 1

10 0

10 1

11 0

11 1

41h Reserved 00h

42h SD Mode Register 1 SD PrPb SSAF 0

SD DAC Output 1 0

SD DAC Output 2 0

SD Pedestal 0

1

SD Square Pixel 0

1

SD VCR FF/RW Sync 0

1

SD Pixel Data Valid 0

1

SD SAV/EAV Step Edge Control 0

1

43h SD Mode Register 2 SD Pedestal YPrPb Output 0

SD Output Levels Y 0

SD Output Levels PrPb 0 0

01

10

11

SD VBI Open 0

1

SD CC Field Control 0 0

01

10

11

Reserved 0

01PAL B, D, G, H, I

10PAL M

11PAL N

SSAF Luma

Luma CIF

Luma QCIF

Reserved

1.3 MHz

0.65 MHz

1.0 MHz

2.0 MHz

Reserved

Chroma CIF

Chroma QCIF

3.0 MHz

Disabled

1

Enabled

Refer to the Output Configuration

1

section

1

Refer to the Output Configuration

section

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

No Pedestal on YPrPb

1

7.5 IRE Pedestal on YPrPb

Y = 700 mV/300 mV

1

Y = 714 mV/286 mV

700 mV p-p (PAL); 1000 mV p-p (NTSC)

700 mV p-p

1000 mV p-p

648 mV p-p

Disabled

Enabled

CC Disabled

CC on Odd Field Only

CC on Even Field Only

CC on Both Fields

Reserved

Values

08h

00h

REV. B

–21–

ADV7330

SR7–

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset

SR0

44h SD Mode Register 3

45h Reserved 00h
46h Reserved 00h
47h SD Mode Register 4

48h SD Mode Register 5

49h SD Mode Register 6

SD VSYNC-3H

SD RTC/TR/SCR* 00 Genlock Disabled

SD Active Video Length 0 720 Pixels

SD Chroma 0 Chroma Enabled

SD Burst 0 Enabled

SD Color Bars 0 Disabled

SD DAC Swap

SD PrPb Scale 0 Disabled

SD Y Scale 0 Disabled

SD Hue Adjust 0 Disabled

SD Brightness 0 Disabled

SD Luma SSAF Gain 0 Disabled

Reserved 0 0 must be written to this bit.
Reserved 0 0 must be written to this bit.
Reserved 0 0 must be written to this bit.
Reserved 00 must be written to this bit.

Reserved 00 must be written to this bit.
SD Double Buffering 0 Disabled

SD Input Format 0 8-Bit Input

Reserved 0 0 must be written to this bit.
SD Digital Noise Reduction 0 Disabled

SD Gamma Control 0 Disabled

SD Gamma Curve 0 Gamma Curve A

SD Undershoot Limiter 0 0 Disabled

Reserved 00 must be written to this bit.
SD Black Burst Output on DAC Luma 0 Disabled

SD Chroma Delay 0 0 Disabled

Reserved 0 0 must be written to this bit.
Reserved 0 0 must be written to this bit.

1 Enabled

0

1

1 Enabled

1 Gamma Curve B

1 Chroma Disabled

1 Disabled

1 Enabled

1 Enabled

01 4 Clk Cycles
10 8 Clk Cycles
11 Reserved

01 Subcarrier Reset
10 Timing Reset
11 RTC Enabled

1 710 (NTSC)/702 (PAL)

1 Enabled

1 Enabled

1 Enabled

1 16-Bit Input

1 Enabled

*See Figure 23, RTC Timing and Connections.

0

Disabled

1

VSYNC = 2.5 Lines (PAL)
VSYNC = 3 Lines (NTSC)

DAC B = Luma
DAC C = Chroma
DAC B = Chroma
DAC C = Luma

1 Enabled

1 Enabled

01–11 IRE
10–6 IRE
11–1.5 IRE

Values

00h

00h

00h

REV. B–22–

ADV7330

H

SR7–

Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values

SR0

4Ah SD Timing Register 0 SD Slave/Master Mode

SD Timing Mode

SD BLANK Input

SD Luma Delay

SD Min. Luma Value

SD Timing Reset x 0 0 0 0 0 0 0 A low-high-low transition will reset the

4Bh SD Timing Register 1

SD HSYNC Width 0 0

SD HSYNC to VSYNC Delay 0 0

SD HSYNC to VSYNC Rising x 0 T
Edge Delay (Mode 1 Only)

VSYNC Width (Mode 2 Only)

HSYNC to Pixel Data Adjust 0 0 0 Clk Cycles

4Ch

SD F

Register 0

SD F

SC

Register 1

SC

Register 2

SC

Register 3

SC

Phase

SC

4Dh SD F

4Eh SD F

4Fh

50h SD F

51h SD Closed Captioning Extended Data on Even Fields

52h SD Closed Captioning Extended Data on Even Fields

53h SD Closed Captioning Data on Odd Fields

54h SD Closed Captioning Data on Odd Fields

55h SD Pedestal Register 0 Pedestal on Odd Fields

56h SD Pedestal Register 1 Pedestal on Odd Fields

57h SD Pedestal Register 2 Pedestal on Even Fields

58h SD Pedestal Register 3 Pedestal on Even Fields

00 Mode 0

01 Mode 1

10 Mode 2

11 Mode 3

0 Enabled

1Disabled

00 No Delay

01 2 Clk Cycles

10 4 Clk Cycles

11 6 Clk Cycles

0– 40 IRE

1– 7.5 IRE

01 T

10

11 T

x1 T

00 1 Clk Cycle

01 4 Clk Cycles

10 16 Clk Cycles

11 128 Clk Cycles

01 1 Clk Cycle

10 2 Clk Cycles

11 3 Clk Cycles

xx xxxxxxSubcarrier Frequency Bit 7–0

xx xxxxxxSubcarrier Frequency Bit 15–8

xx xxxxxxSubcarrier Frequency Bit 23–16

xx xxxxxxSubcarrier Frequency Bit 31–24

xx xxxxxxSubcarrier Phase Bit 9–2

xx xxxxxxExtended Data Bit 7–0

xx xxxxxxExtended Data Bit 15–8

xx xxx xxxData Bit 7–0

xx xxxxxxData Bit 15–8

17 16 15 14 13 12 11 10

25 24 23 22 21 20 19 18

17 16 15 14 13 12 11 10

25 24 23 22 21 20 19 18

0Slave Mode

1 Master Mode

internal SD timing counters.

= 1 Clk Cycle

T

01T

10

11T

A

= 4 Clk Cycles

A

T

= 16 Clk Cycles

A

= 128 Clk Cycles

A

T

= 0 Clk Cycle

B

= 4 Clk Cycles

B

T

= 8 Clk Cycles

B

= 18 Clk Cycles

B

= T

C

= T

C

Setting any of these bits to 1 00h

will disable pedestal on the 00h

line number indicated by the 00h

bit settings. 00h

B

+ 32 µs

B

08h

00h

16h

7Ch

F0h

21h

00h

00h

00h

00h

00h

LINE 313 LINE 314LINE 1

SYNC

t

A

t

t

B

C

VSYNC

Figure 15. Timing Register 1 in PAL Mode

REV. B

–23–