Datasheet ADV7330 Datasheet (Analog Devices)

Multiformat 11-Bit

Triple DAC Video Encoder

ADV7330

FEATURES High Definition Input Formats 8-Bit or 16-Bit (4:2:2) Parallel YCrCb Compliant with:

SMPTE 293M (525p) BTA T-1004 EDTV2 525p ITU-R BT.1358 (525p/625p) ITU-R BT.1362 (525p/625p) SMPTE 274M (1080i) at 30 Hz and 25 Hz SMPTE 296M (720p) Other High Definition Formats Using Async

Timing Mode

High Definition Output Formats

YPrPb Progressive Scan (EIA-770.1, EIA-770.2) YPrPb HDTV (EIA 770.3) RGB, RGBHV CGMS-A (720p/1080i) Macrovision

Rev 1.1 (525p/625p)

CGMS-A (525p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-Bit or 16-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M/N Composite PAL M/N/B/D/G/H/I, PAL-60 SMPTE 170M NTSC Compatible Composite Video ITU-R BT.470 PAL Compatible Composite Video S-Video (Y/C) EuroScart RGB Component YPrPb (Betacam, MII, SMPTE/EBU N10) Macrovision Rev 7.1.L1 CGMS/WSS Closed Captioning

GENERAL FEATURES Programmable DAC Gain Control Sync Outputs in All Modes On-Board Voltage Reference Three 11-Bit Precision Video DACs 2-Wire Serial I

2C®

Interface, Open Drain Configuration Dual I/O Supply 2.5 V/3.3 V Operation Analog and Digital Supply 2.5 V On-Board PLL 64-Lead LQFP Package Lead (Pb) Free Product

APPLICATIONS SD/PS DVD Recorders/Players SD/Prog Scan/HDTV Display Devices SD/HDTV Set Top Boxes

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

STANDARD DEFINITION

Y7–Y0 C7–C0

SYNC_I/P

VSYNC_I/P

LANK_I/P

CLKIN

D E M U X

TIMING

GENERATOR

PLL

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

PROGRAMMABLE

RGB MATRIX

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

ADV7330

11-BIT

O V

DAC E R S

11-BIT

DAC

M P L

11-BIT

DAC G

I2C

INTERFACE

GENERAL DESCRIPTION

The ADV®7330 is a high speed, digital-to-analog encoder on a single monolithic chip. It includes three high speed video D/A converters with TTL compatible inputs.

The ADV7330 has separate 8-bit or 16-bit input ports that accept data in high definition or standard definition video format. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV timing codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signal.

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADV7330

DETAILED FEATURES High Definition Programmable Features (720p/1080i)

2 Oversampling (148.5 MHz) Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control

CGMS-A (720p/1080i)

Programmable Features (525p/625p)

8 Oversampling Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Frame) Individual Y and PrPb Output Delay Gamma Correction Programmable Adaptive Filter Control Fully Programmable YCrCb to RGB/Matrix Undershoot Limiter Macrovision Rev 1.1 (525p/625p) CGMS-A (525p)

Standard Definition Programmable Features

16 Oversampling Internal Test Pattern Generator

(Colorbars, Black Bar) Controlled Edge Rates for Sync, Active Video Individual Y and PrPb Output Delay Gamma Correction Digital Noise Reduction (DNR) Multiple Chroma and Luma Filters Luma-SSAF™ Filter with Programmable

Gain/Attenuation PrPb SSAF™ Separate Pedestal Control on Component and

Composite/S-Video Outputs VCR FF/RW Sync Mode

Macrovision Rev 7.1.L1 CGMS/WSS Closed Captioning

Standards Directly Supported

Frame Clk

Resolution Rate (Hz) Input (MHz) Standard

720  480 29.97 27 ITU-R BT.656 720  576 25 27 ITU-R BT.656 720  483 59.94 27 SMPTE 293M 720  480 59.94 27 BTA T-1004 720  576 50 27 ITU-R BT.1362 1280  720 60 74.25 SMPTE 296M 1920  1080 30 74.25 SMPTE 274M 1920  1080 25 74.25 SMPTE 274M*

Other standards are supported in Async Timing Mode. *SMPTE 274M-1998: System No. 6

HSYNC VSYNC BLANK

CLKIN

SD/PS/HD

PIXEL INPUT

DEINTER-

LEAVE

DEINTER-

LEAVE

DETAILED FUNCTIONAL BLOCK DIAGRAM

TEST

PATTERN

TEST

PATTERN

TIMING

GENERATOR

SHARPNESS

AND

ADAPTIVE

FILTER

CONT

ROL

DNR

GAMMA

Y COLOR CR COLOR CB COLOR

COLOR

CONTROL

CLOCK

CONTROL

AND PLL

INSERTION

4:2:2

4:4:4

SYNC

UV SSAF

LUMA

CHROMA

FILTERS

AND

2 OVER-

SAMPLING

RGB

MATRIX

MODULATION

CGMS

WSS

PS 8

HDTV 2

SD 16

DAC

REV. B–2–

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11

THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 11

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12

MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 13

Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 14

INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 27

Standard Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Progressive Scan or HDTV Mode . . . . . . . . . . . . . . . . . . 27

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 27

OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 28

TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 29

HD Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SD Real-Time Control, Subcarrier Reset, Timing Reset . 31

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 33

SD Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . 33

Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 35

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 36

COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 40

HD Y Level, Cr Level, Cb Level . . . . . . . . . . . . . . . . . . . 40

HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 40

SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 42

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

ADV7330

HD SHARPNESS FILTER CONTROL AND

ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . . . 44

HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . . 44

HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . 44

HD Sharpness Filter and Adaptive Filter Application

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

ADAPTIVE FILTER CONTROL APPLICATION . . . . . . 46

SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . 47

Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . 48

DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . 48

SAV/EAV STEP EDGE CONTROL . . . . . . . . . . . . . . . . . 48

BOARD DESIGN AND LAYOUT CONSIDERATIONS . 50

DAC Termination and Layout Considerations . . . . . . . . 50

VIDEO OUTPUT BUFFER AND OPTIONAL

OUTPUT FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 51

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 52

Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX 1—COPY GENERATION

MANAGEMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . 53

HD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . 53

SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . . 53

HD CGMS Data Registers . . . . . . . . . . . . . . . . . . . . . . . 53

Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 53

APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . . 55

APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . . 56

APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . . 57

APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . . 60

Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . . 60

Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . . 61

Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 63

Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 65

Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 66

APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . . 67

APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . . 68

HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 68

RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . . 74

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 76

REV. B

–3–

ADV7330–SPECIFICATIONS

(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; V V

= 1.235 V, R

REF

= 3040 , R

SET

= 300 . All specifications T

LOAD

= 2.375 V to 3.6 V,

DD_IO

MIN

to T

MAX

(0C to 70C), unless otherwise noted.)

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE

(With No Oversampling Ratio) Resolution 11 Bits Integral Nonlinearity 1.5 LSB Differential Nonlinearity

, +ve 0.5 LSB

Differential Nonlinearity2, –ve 1.0 LSB

DIGITAL OUTPUTS

Output Low Voltage, V

Output High Voltage, V

2.4 [2.0]

0.4 [0.4]

Three-State Leakage Current ±1.0 µAV

VI VI

SINK

SOURCE

= 0.4 V, 2.4 V

= 3.2 mA

= 400 µA

Three-State Output Capacitance 2 pF

DIGITAL AND CONTROL INPUTS

Input High Voltage, V Input Low Voltage, V

Input Leakage Current 3 µAV Input Capacitance, C

0.8 V = 2.4 V

2pF

ANALOG OUTPUTS

Full-scale Output Current 4.1 4.33 4.6 mA Output Current Range 4.1 4.33 4.6 mA DAC to DAC Matching 1.0 % Output Compliance Range, V Output Capacitance, C

OUT

0 1.0 1.4 V

7pF

VOLTAGE REFERENCE

Internal Reference Range, V External Reference Range, V V

Current

REF

1.15 1.235 1.3 V

±10 µA

POWER REQUIREMENTS Normal Power Mode

170 190

mA SD (16×) 110 mA PS (8×) 95 mA HDTV (2×)

DD_IO

7, 8

1.0 mA 24 28 mA

Sleep Mode

DD_IO

200 µA 10 µA 250 µA

Power Supply Rejection Ratio 0.01 %/%

NOTES

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL, the actual step value lies below the ideal step value.

Value in brackets for V

External current required to overdrive internal V

IDD, the circuit current, is the continuous current required to drive the digital core.

Guaranteed maximum by characterization.

IAA is the total current required to supply all DACs including the V

All DACs on.

Specifications subject to change without notice.

= 2.375 V to 2.75 V.

DD_IO

REF

circuitry and the PLL circuitry.

REF

REV. B–4–

ADV7330

(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; V

DYNAMIC SPECIFICATIONS

Parameter Min Typ Max Unit Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth 12.5 MHz Chroma Bandwidth 5.8 MHz SNR 65.6 dB Luma ramp unweighted

HDTV MODE

Luma Bandwidth 30 MHz Chroma Bandwidth 13.75 MHz

STANDARD DEFINITION MODE

Hue Accuracy 0.4 Degrees Color Saturation Accuracy 0.4 % Chroma Nonlinear Gain 1.2 ±%Referenced to 40 IRE Chroma Nonlinear Phase –0.2 ± Degrees Chroma/Luma Intermodulation 0 ±% Chroma/Luma Gain Inequality 97.0 ±% Chroma/Luma Delay Inequality –1.1 ns Luminance Nonlinearity 0.5 ±% Chroma AM Noise 84 dB Chroma PM Noise 75.2 dB Differential Gain 0.20 % NTSC Differential Phase 0.15 Degrees NTSC SNR 59.1 dB Luma ramp

Specifications subject to change without notice.

= 3040 , R

SET

= 300 . All specifications T

LOAD

72 dB Flat field full bandwidth

77.7 dB Flat field full bandwidth

MIN

= 2.375 V to 3.6 V, V

DD_IO

to T

(0C to 70C), unless otherwise noted.)

MAX

REF

= 1.235 V,

REV. B

–5–

ADV7330

TIMING SPECIFICATIONS

(VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V; V R

= 3040 , R

SET

= 300 . All specifications T

LOAD

= 2.375 V to 3.6 V, V

DD_IO

to T

MIN

(0C to 70C), unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Conditions

MPU PORT

SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth, t SCLOCK Low Pulsewidth, t Hold Time (Start Condition), t Setup Time (Start Condition), t Data Setup Time, t

SDATA, SCLOCK Rise Time, t SDATA, SCLOCK Fall Time, t Setup Time (Stop Condition), t

0.6 µs

1.3 µs

0.6 µs After this period, the first clock is generated

0.6 µsRelevant for repeated start condition 100 ns

300 ns 300 ns

0.6 µs

RESET Low Time 100 ns

ANALOG OUTPUTS

Analog Output Delay

7ns

Output Skew 1 ns

CLOCK CONTROL AND PIXEL PORT

CLK

Clock High Time, t Clock Low Time, t Data Setup Time, t Data Hold Time, t SD Output Access Time, t SD Output Hold Time, t HD Output Access Time, t HD Output Hold Time, t

PIPELINE DELAY

27 MHz Progressive scan mode

81 MHz HDTV mode/async mode 40 % of one clk cycle 40 % of one clk cycle

2.0 ns

15 ns

5.0 ns

14 ns

5.0 ns

63 clk cycles SD (2×, 16×)

76 clk cycles SD component mode (16×)

35 clk cycles PS (1×)

41 clk cycles PS (8×)

36 clk cycles HD (2×, 1×)

NOTES

Guaranteed by characterization.

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of the DAC output full-scale transition.

Data: C [9:0]; Y [9:0], S[9:0]. Control: HSYNC_I/P, VSYNC_I/P, BLANK_I/P, HSYNC_O/P , VSYNC_O/P, BLANK_O/P.

SD, PS = 27 MHz, HD = 74.25 MHz.

Specifications subject to change without notice.

= 1.235 V,

REF

REV. B–6–

CLKIN

ADV7330

CONTROL

INPUTS

CONTROL

OUTPUTS

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

Figure 1. HD/PS 4:2:2 Input Mode (HD: Input Mode 010) (PS: Input Mode 001)

CONTROL

INPUTS

HSYNC_I/P VSYNC_I/P BLANK_I/P

Y7–Y0

C7–C0

HSYNC_O/P VSYNC_O/P BLANK_O/P

CLKIN

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

Y0 Y1 Y2 Y3 Y4 Y5

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

t12

Cb0 Y0 Y1 Crxxx YxxxCr0

CONTROL

OUTPUTS

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

Y7–Y0

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

Figure 2. PS 4:2:2 1× 8-Bit Interleaved at 27 MHz Hsync/Vsync Input Mode (Input Mode 100)

REV. B

–7–

ADV7330

CLKIN

3FF 00 XY Cb0* Y0 Cr0 Y100

*Y0, Cb, SEQUENCE AS PER SUBADDRESS 01h BIT 1

CONTROL

OUTPUTS

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

Y7–Y0

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

Figure 3. PS 4:2:2 1× 8-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)

CLKIN

t10

CONTROL

INPUTS

CONTROL

OUTPUTS

HSYNC_I/P VSYNC_I/P BLANK_I/P

Y7–Y0

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

t11

Cb0 Y0 Cr2 Y1 Cbxxx Cbxxx

t13

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

Figure 4. PS 4:2:2 1× 8-Bit Interleaved at 54 MHz Hsync/Vsync I/P Mode (Input Mode 011)

CLKIN

Y7–Y0

CONTROL

OUTPUTS

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

3FF 00 00 XY Cb0 Y0 Cr0 Y1

Figure 5. PS 4:2:2 1× 8-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 011)

REV. B–8–

CONTROL

INPUTS

CLKIN

HSYNC_I/P VSYNC_I/P BLANK_I/P

ADV7330

IN SLAVE MODE

CONTROL

OUTPUTS

CONTROL

INPUTS

CONTROL

OUTPUTS

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

CLKIN

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

Y7–Y0

C7–C0

HSYNC_O/P VSYNC_O/P BLANK_O/P

SYNC_I/P

VSYNC_I/P

Y7–Y0

Cb Y

YCbY

Figure 6. 8-Bit SD Pixel Input Mode (Input Mode 000)

Cb0

Cr0

Cb2

Figure 7. 16-Bit SD Pixel Input Mode (Input Mode 000)

Cr2

IN MASTER/SLAVE MODE

IN SLAVE MODE

IN MASTER/SLAVE MODE

LANK_I/P

Y7–Y0

C7–C0

A = 16 CLK CYCLES FOR 525p A = 12 CLK CYCLES FOR 626p A = 44 CLK CYCLES FOR 1080i @ 30Hz, 25Hz A = 70 CLK CYCLES FOR 720p AS RECOMMENDED BY STANDARD

B (MIN) = 122 CLK CYCLES FOR 525p B (MIN) = 132 CLK CYCLES FOR 625p B (MIN) = 236 CLK CYCLES FOR 1080i @ 30Hz, 25Hz B (MIN) = 300 CLK CYCLES FOR 720p

Y0 Y1

Cb0 Cr0

Y2 Y3

Cr1 Cb1

Figure 8. HD 4:2:2 Input Timing Diagram

REV. B

–9–

ADV7330

SYNC_I/P

VSYNC_I/P

LANK_I/P

Y7–Y0

A = 32 CLK CYCLES FOR 525p A = 24 CLK CYCLES FOR 626p AS RECOMMENDED BY STANDARD

Figure 9. PS 4:2:2, 1 × 8-Bit Interleaved Input Timing Diagram

SYNC_I/P

VSYNC_I/P

PAL = 24 CLK CYCLES

NTSC = 32 CLK CYCLES

LANK_I/P

Y7–Y0

*SELECTED BY ADDRESS 44h BIT 7

Figure 10. SD Timing Input for Timing Mode 1

SDA

B (MIN) = 244 CLK CYCLES FOR 525p B (MIN) = 264 CLK CYCLES FOR 625p

PAL = 264 CLK CYCLES NTSC = 244 CLK CYCLES

Cb Y

Cr Y

SCLK

Figure 11. MPU Port Timing Diagram

REV. B–10–

ADV7330

ABSOLUTE MAXIMUM RATINGS

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.0 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.0 V

to GND_IO . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

DD_IO

Digital Input Voltage to DGND . . . . –0.3 V to V

to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

1, 2

DD_IO

+ 0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DGND to GND_IO . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to GND_IO . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Ambient Operating Temperature (T

) . . . . . . . . 0°C to 70°C

Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C

Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . . 260°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

Analog output short circuit to any power supply or common can be of an indefinite duration.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADV7330KST 0°C to 70°CLow Profile Quad Flat Package ST-64-2

THERMAL CHARACTERISTICS

␪JC = 11°C/W

= 47°C/W

␪

The ADV7330 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255°C (±5°C).

In addition, it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7330 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–11–

ADV7330

PIN CONFIGURATION

GND_IO

TEST14

TEST13

TEST12

TEST11

TEST10

TEST9

DGND

VDDTEST8

TEST7

TEST6

TEST5

TEST4

HSYNC_O/

VSYNC_O/P

49505152535455565758596061626364

DD_IO

TEST0

TEST1

DGND

TEST2

TEST3

NC = NO CONNECT

PIN 1 IDENTIFIER

C I

ALSB

SDA

ADV7330

TOP VIEW

(Not to Scale)

SCLK

VSYNC_I/P

BLANK_I/P

HSYNC_I/P

C3C4C5C6C7

BLANK_O/

TEST16

REF

TEST15

AGND

DAC A

DAC B

DAC C

COMP

SET

EXT_LF

RESET

32313029282726252423222120191817

CLKIN

RTC_SCR_TR

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic I/O Function

11, 57 DGND G Digital Ground.

2, 3, 14, 15, TEST0–TEST14 I Not used, tie to DGND. 51–55, 58–63

40 AGND G Analog Ground.

32 CLKIN I Pixel Clock Input for HD (74.25 MHz Only, PS (27 MHz), SD (27 MHz)). 36 COMP O Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V

39 DAC A O CVBS/GREEN/Y Analog Output.

38 DAC B O Chroma/BLUE/Pb Analog Output.

37 DAC C O Luma/RED/Pr Analog Output. 25 BLANK_I/P IVideo Blanking Control Signal. For HD and PS, this input is active high. For SD

input, this input is active low.

23 HSYNC_I/P IVideo Horizontal Sync Control Signal. 24 VSYNC_I/P IVideo Vertical Sync Control Signal.

4–9, 12, 13 Y7–Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved

progressive scan data. The LSB is set up on Pin Y0.

16–18, 26–30 C7–C0 I 8-Bit SD/Progressive Scan/HDTV Input Port. The LSB is set up on Pin C0. 33 RESET IThis input resets the on-chip timing generator and sets the ADV7330 into the default

35 R

SET

IA 3040 Ω resistor must be connected from this pin to AGND and is used to control

the amplitudes of the DAC outputs.

22 SCLK I I

21 SDA I/O I

20 ALSB I TTL Address Input. This signal sets up the LSB of the I

DD_IO

PPower Supply for Digital Inputs and Outputs.

C Port Serial Interface Clock Input.

C Port Serial Data Input/Output.

tied low, the I

C filter is activated, which reduces noise on the I2C interface.

C address. When this pin is

REV. B–12–

ADV7330

PIN FUNCTION DESCRIPTIONS (continued)

Pin Number Mnemonic I/O Function

10, 56 V

41 V

45, 47 TEST15, TEST16 O Not used, do not connect.

34 EXT_LF I External Loop Filter for the Internal PLL.

31 RTC_SCR_TR I Multifunctional Input: Real-Time Control (RTC) Input, Timing Reset Input,

48 BLANK_O/P O Video Blanking Control Signal. For HD and PS, this input is active high. For SD input,

50 HSYNC_O/P OVideo Horizontal Sync Control Signal. 49 VSYNC_O/P OVideo Vertical Sync Control Signal.

19 I

CIThis input pin must be tied high (V

64 GND_IO Digital Input/Output Ground.

42–44 NC No Connect.

46 V

TERMINOLOGY

REF

SD Standard definition video, conforming to ITU-R

BT.601/656. HD High definition video, such as progressive scan or HDTV. PS Progressive scan video, conforming to SMPTE 293M,

ITU-R BT.1358, BTA T-1004EDTC2, BTA1362

PDigital Power Supply.

PAnalog Power Supply.

Subcarrier Reset Input.

this output is active low.

) for the ADV7330 to interface over the I2C port.

DD_IO

I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output

(1.235 V).

HDTV High definition television video, conforming to SMPTE

274M or SMPTE 296M. YCrCb SD, PS, or HD component digital video. YPrPb SD, PS, or HD component analog video.

MPU PORT DESCRIPTION

The ADV7330 supports a 2-wire serial (I2C compatible) microprocessor bus driving multiple peripherals. This bus operates in an Open Drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The ADV7330 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 12. The LSB sets either a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7330 to Logic 0 or Logic 1. When ALSB is set to 1, there is greater input bandwidth on the I on this bus. When ALSB is set to 0, there is reduced input bandwidth on the I than 50 ns will not pass into the I

C lines, which allows high speed data transfers

C lines, which means that pulses of less

C internal controller. This

mode is recommended for noisy systems.

1 1 0 1 0 1 A1 X

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE 1 READ

Figure 12. ADV7330 Slave Address = D4h

To control the various devices on the bus, the following protocol must be followed. First the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA, while SCL remains high. This indicates that an address/ data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is when the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data.

A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A Logic 1 on the LSB of the first byte means that the master will read information from the peripheral.

The ADV7330 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence, starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers.

REV. B

–13–

ADV7330

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7330 will not issue an acknowledge and will return to the idle condition. If in auto-increment mode the user exceeds the highest subaddress, the following action will be taken:

1. In read mode, the highest subaddress register contents will continue to be output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition is when the SDA line is not pulled low on the ninth pulse.

2. In write mode, the data for the invalid byte will not be loaded into any subaddress register, a no acknowledge will be issued by the ADV7330, and the part will return to the idle condition.

Before writing to the subcarrier frequency registers, it is a requirement that the ADV7330 reset at least once after power-up.

The four subcarrier frequency registers must be updated starting with subcarrier frequency register 0 through subcarrier frequency register 3. The subcarrier frequency will not update until the

last subcarrier frequency register byte has been received by the ADV7330.

Figure 13 illustrates an example of data transfer for a write sequence and the start and stop conditions. Figure 14 shows bus write and read sequences.

REGISTER ACCESS

The MPU can write to or read from all of the registers of the ADV7330 except the subaddress registers that are write-only registers. The subaddress register determines which register the next read or write operation accesses. All communications with the part go through the bus start with an access to the subaddress register. Then a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed.

Register Programming

The following tables describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place.

WRITE

SEQUENCE

READ

SEQUENCE

SDATA

SCLOCK

1–7 8

START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP

9S1–7 8 9

1–7

Figure 13. Bus Data Transfer

S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P

LSB = 0

S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P

S = START BIT P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER

LSB = 1

A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER

Figure 14. Write and Read Sequence

REV. B–14–

ADV7330

SR7–

SR0

00h Power Mode Sleep Mode. With this control

01h Input Mode 0Disabled

enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled. I registers can be read from and written to in sleep mode.

PLL and Oversampling Control. This control allows the internal PLL cct to be powered down and the oversampling to be switched off.

DAC C. Power On/Off. 0 DAC C Off

DAC B. Power On/Off. 0 DAC B Off

DAC A. Power On/Off. 0

BTA T-1004 or BT 1362 Compatibility.

Clock Edge 0

Reserved 0 Reserved 0

ut Mode 0 0 0 SD Input 38h

Reserved 0

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit

1 DAC B On

xxx

001 PS Input 010 HDTV Input 011 PS 54 MHz In 100 PS 27 MHz Input 101 Reserved 110 Reserved

111 Reserved

1 DAC A On

Sleep Mode Off FCh

1 Sleep Mode On

PLL On

1 PLL Off

1 DAC C On

DAC A Off

1Enabled

Cb Clocked on Rising Edge

1Y Clocked on Rising Edge

Reserved

Only for PS dualedge clk mode

Only for PS interleaved input at 27 MHz

REV. B

–15–

ADV7330

SR7–

SR0

02h Mode Register 0 Reserved 00 Zero must be written

Test Pattern Black Bar 0

RGB Matrix 0 Disable

Sync on RGB

RGB/YUV Output 0 RGB component

SD Sync 0 No Sync Output

HD Sync

03h RGB Matrix 0 04h RGB Matrix 1 x x LSB for RV F0h

05h RGB Matrix 2 x x x x x x x x Bit 9–2 for GY 4Eh 06h RGB Matrix 3 x x x x x x x x Bit 9–2 for GU

07h RGB Matrix 4 x x x x x x x x Bit 9–2 for GV 24h 08h RGB Matrix 5 x x x x x x x x Bit 9–2 for BU 09h RGB Matrix 6 x x x x x x x x Bit 9–2 for RV 7Ch 0Ah xx xx xx xxReserved 0Bh

DAC A,B,C Output Level

0Ch Reserved 00h 0Dh Reserved 0Eh Reserved 0Fh Reserved 00h

NOTES

For more detail, refer to Appendix 7.

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

Positive Gain to DAC Output Voltage 0 0 0 0 0 0 0 0 0% 00h

Negative Gain to DAC Output Voltage 1 1 0 0 0 0 0 0 –7.5%

1 Output SD Syncs on

0No Sync Output 1 Output HD Syncs on

xx LSB for GU

00 00 00 010.018% 00 00 00 100.036%

00 11 11 117.382% 01 00 00 007.5%

11 00 00 01–7.382% 10 00 00 10–7.364%

11 11 11 11–0.018%

0No S

1YUV component

xx LSB for GV

1 Enabled

1 Enable Programmable

xx LSB for BU

to these bits

Disabled

Programmable RGB Matrix

RGB Martix

Sync on all RGB Outputs

Out

uts

Out

HSYNC_O/P, VSYNC_O/P, BLANK_O/P

LSB for GY

………

… …….

20h

11h, Bit 2 must also be enabled

03h

0Eh

92h

00h 00h

REV. B–16–

SR7–

SR0

10h HD Mode

11h HD Mode

HD Output Standard 0 0 EIA770.2 Output 00h

01EIA770.1 Output 10Output levels for Full Input

HD Input Control Signals 0 0

01 EAV/SAV codes 10 Async Timing Mode

HD 625p 0 525p

HD 720p 0 1080i

HD BLANK Polarity 0 BLANK Active High

HD Macrovision for 525p/625p 0 Macrovision Off

HD Pixel Data Valid 0 Pixel Data Valid Off 00h

HD Test Pattern Enable 0 HD Test Pattern Off

HD Test Pattern Hatch/Field 0 Hatch

HD VBI Open 0 Disabled

HD Undershoot Limiter 0 0 Disabled

HD Sharpness Filter 0 Disabled

1 Macrovision On

1 Enabled

1 720p

1 BLANK Active Low

01 –11 IRE 10 –6 IRE 11 –1.5 IRE

11 Reserved

1 625p

1 Field/Frame

1 Enabled

11Reserved

1 Pixel Data Valid On

0 Reserved

1 HD Test Pattern On

Ran

HSYNC, VSYNC, BLANK

ADV7330

Values

REV. B

–17–

ADV7330

;

SR7–

SR0

12h HD Mode Register 3 000

13h HD Mode Register 4

14h HD Mode Register 5

15h HD Mode Register 6

NOTES

When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are

HD Y Delay with respect to falling edge of HSYNC

HD Color Delay with respect to falling edge of HSYNC

HD CGMS 0 Disabled

HD CGMS CRC

HD Cr/Cb Sequence

Reserved 00 must be written to this bit. Reserved 0 0 must be written to this bit. Sinc Filter on DAC A, B, C

Reserved 0 0 must be written to this bit. HD Chroma SSAF

Reserved HD Double Buffering

HD Timing Reset

1080i Frame Rate

Reserved

HD Vsync/Field Input

Lines/Frame

Reserved

HD RGB Input

HD Sync on PrPb 0

HD Color DAC Swap 0 DAC E = Pr; DAC F = Pb

HD Gamma Curve A/B 0 Gamma Curve A

HD Gamma Curve Enable 0 Disabled

HD Adaptive Filter Mode 0

HD Adaptive Filter Enable 0

0 1 Enabled

0 1

00 0

00 1 01 0 01 13 Clk Cycles 10 0

0 1

00 0

1 Mode B

0011 Clk Cycle 010 0113 Clk Cycles 100

0 1 Enabled

00 30 Hz/2200 Total Samples/Line 01 25 Hz/2640 Total Samples/Line

1 Enabled

0 Clk Cycle

2 Clk C

cles

4 Clk Cycles 0 Clk Cycle

1 Clk Cycle

cles

2 Clk C

4 Clk C

cles

Enabled Disabled

Cb after Falling Edge of HSYNC

Cr after Falling Edge of HSYNC

Disabled

Disabled Enabled

Disabled

Enabled

xA low-high-low transition resets the

internal HD timing counters.

0 must be written to these bits.

Field Input

Vsync Input

Update Field/Line Counter

Field/Line Counter Free Running

0 must be written to this bit.

Disabled

DAC E = Pb

Gamma Curve B

Enabled Mode A

Disabled Enabled

DAC F = Pr

free running and wrap around when external sync signals indicate so.

Values

00h

4Ch

00h

REV. B–18–

ADV7330

SR7–

SR0

16h HD Y Level 17h HD Cr Level 18h HD Cb Level 19h Reserved 00h 1Ah Reserved 00h 1Bh Reserved 1Ch Reserved 00h 1Dh Reserved 1Eh Reserved 00h 1Fh 20h HD Sharpness Filter HD Sharpness Filter Gain Value A

Gain

21h HD CGMS Data 0 HD CGMS Data Bits 0 0 0 0 C19 C18 C17 C16 CGMS 19–16 00h 22h HD CGMS Data 1 HD CGMS Data Bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS 15–8 00h 23h HD CGMS Data 2 HD CGMS Data Bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS 7–0 00h 24h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A0 00h 25h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A1 00h 26h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A2 00h 27h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A3 00h 28h HD Gamma A 29h HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A5 00h 2Ah HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A6 00h 2Bh HD Gamma A 2Ch HD Gamma A HD Gamma Curve A Data Points x x x x x x x x A8 00h 2Dh HD Gamma A 2Eh HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B0 00h 2Fh HD Gamma B HD Gamma Curve B Data Points 30h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B2 00h 31h HD Gamma B HD Gamma Curve B Data Points 32h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B4 00h 33h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B5 00h 34h HD Gamma B HD Gamma Curve B Data Points 35h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B7 00h 36h HD Gamma B HD Gamma Curve B Data Points 37h HD Gamma B HD Gamma Curve B Data Points x x x x x x x x B9 00h

NOTES

For the internal test pattern only.

Reserved 00h

HD Sharpness Filter Gain Value B

HD Gamma Curve A Data Points x x x x x x x x

HD Gamma Curve A Data Points x x x x x x x x A7 00h

HD Gamma Curve A Data Points x x x x x x x x A9 00h

xxxxx xxxxxxxxCr Color Value 80h xxxxx

0000 Gain B = 0

00 1

.. .. .. .. …….

11 1

0 1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

xxxxxxxxB1 00h

xxxxxxxxB3 00h

xxxxxxxxB6 00h

xxxxxxxx

xx x

0000Gain A = 0 00h

00 1

.. .. .. .. ……

0111Gain A = +7 1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

Setting

Y Color Value

Cb Color Value

Gain A = +1

Gain B = +1

Gain B = +7

A4 00h

B8 00h

Reset Values

A0h

80h

00h

REV. B

–19–

ADV7330

SR7SR0

38h HD Adaptive Filter HD Adaptive Filter Gain 1

39h HD Adaptive Filter HD Adaptive Filter Gain 2

3Ah HD Adaptive Filter HD Adaptive Filter Gain 3

3Bh HD Adaptive Filter HD Adaptive Filter Threshold A

3Ch HD Adaptive Filter HD Adaptive Filter Threshold B

3Dh HD Adaptive Filter HD Adaptive Filter Threshold C

Gain 1 Value A

HD Adaptive Filter Gain 1 Value B

Gain 2 Value A

HD Adaptive Filter Gain 2 Value B

Gain 3 Value A

HD Adaptive Filter Gain 3 Value B

Threshold A Value

Threshold B Value

Threshold C Value

Setting

0000Gain A = 0 0001Gain A = +1

.. .. .. .. ……

0111Gain A = +7 1000Gain A = –8

.. .. .. .. ……

0000 Gain B = 0 0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7 1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0000 Gain B = 0 0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7 1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1

0000 Gain B = 0 0001 Gain B = +1

.. .. .. .. …….

0111 Gain B = +7 1000 Gain B = –8

.. .. .. .. ……..

1111 Gain B = –1 xxxxxxxxThreshold A

xxxxxxxxThreshold B

xxxxxxxxThreshold C

1111Gain A = –1

0000Gain A = 0 0001Gain A = +1

.. .. .. .. ……

0111Gain A = +7 1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

0000Gain A = 0 0001Gain A = +1

.. .. .. .. ……

0111Gain A = +7 1000Gain A = –8

.. .. .. .. ……

1111Gain A = –1

Reset Values

00h

REV. B–20–

ADV7330

SR7–

SR0

3Eh Reserved 00h

3Fh Reserved 00h

40h SD Mode Register 0 SD Standard 0 0 NTSC 00h

SD Luma Filter 0 0 0 LPF NTSC

001 LPF PAL

010 Notch NTSC

011 Notch PAL

100

101

110

111

SD Chroma Filter 0 0 0

00 1

01 0

01 1

10 0

10 1

11 0

11 1

41h Reserved 00h

42h SD Mode Register 1 SD PrPb SSAF 0

SD DAC Output 1 0

SD DAC Output 2 0

SD Pedestal 0

SD Square Pixel 0

SD VCR FF/RW Sync 0

SD Pixel Data Valid 0

SD SAV/EAV Step Edge Control 0

43h SD Mode Register 2 SD Pedestal YPrPb Output 0

SD Output Levels Y 0

SD Output Levels PrPb 0 0

SD VBI Open 0

SD CC Field Control 0 0

Reserved 0

01PAL B, D, G, H, I

10PAL M

11PAL N

SSAF Luma

Luma CIF

Luma QCIF

Reserved

1.3 MHz

0.65 MHz

1.0 MHz

2.0 MHz

Reserved

Chroma CIF

Chroma QCIF

3.0 MHz

Disabled

Enabled

Refer to the Output Configuration

section

Refer to the Output Configuration

section

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

No Pedestal on YPrPb

7.5 IRE Pedestal on YPrPb

Y = 700 mV/300 mV

Y = 714 mV/286 mV

700 mV p-p (PAL); 1000 mV p-p (NTSC)

700 mV p-p

1000 mV p-p

648 mV p-p

Disabled

Enabled

CC Disabled

CC on Odd Field Only

CC on Even Field Only

CC on Both Fields

Reserved

Values

08h

00h

REV. B

–21–

ADV7330

SR7–

SR0

44h SD Mode Register 3

45h Reserved 00h 46h Reserved 00h 47h SD Mode Register 4

48h SD Mode Register 5

49h SD Mode Register 6

SD VSYNC-3H

SD RTC/TR/SCR* 00 Genlock Disabled

SD Active Video Length 0 720 Pixels

SD Chroma 0 Chroma Enabled

SD Burst 0 Enabled

SD Color Bars 0 Disabled

SD DAC Swap

SD PrPb Scale 0 Disabled

SD Y Scale 0 Disabled

SD Hue Adjust 0 Disabled

SD Brightness 0 Disabled

SD Luma SSAF Gain 0 Disabled

Reserved 0 0 must be written to this bit. Reserved 0 0 must be written to this bit. Reserved 0 0 must be written to this bit. Reserved 00 must be written to this bit.

Reserved 00 must be written to this bit. SD Double Buffering 0 Disabled

SD Input Format 0 8-Bit Input

Reserved 0 0 must be written to this bit. SD Digital Noise Reduction 0 Disabled

SD Gamma Control 0 Disabled

SD Gamma Curve 0 Gamma Curve A

SD Undershoot Limiter 0 0 Disabled

Reserved 00 must be written to this bit. SD Black Burst Output on DAC Luma 0 Disabled

SD Chroma Delay 0 0 Disabled

Reserved 0 0 must be written to this bit. Reserved 0 0 must be written to this bit.

1 Enabled

1 Gamma Curve B

1 Chroma Disabled

1 Disabled

1 Enabled

01 4 Clk Cycles 10 8 Clk Cycles 11 Reserved

01 Subcarrier Reset 10 Timing Reset 11 RTC Enabled

1 710 (NTSC)/702 (PAL)

1 Enabled

1 16-Bit Input

1 Enabled

*See Figure 23, RTC Timing and Connections.

Disabled

VSYNC = 2.5 Lines (PAL) VSYNC = 3 Lines (NTSC)

DAC B = Luma DAC C = Chroma DAC B = Chroma DAC C = Luma

1 Enabled

01–11 IRE 10–6 IRE 11–1.5 IRE

Values

00h

REV. B–22–

ADV7330

SR7–

SR0

4Ah SD Timing Register 0 SD Slave/Master Mode

SD Timing Mode

SD BLANK Input

SD Luma Delay

SD Min. Luma Value

SD Timing Reset x 0 0 0 0 0 0 0 A low-high-low transition will reset the

4Bh SD Timing Register 1

SD HSYNC Width 0 0

SD HSYNC to VSYNC Delay 0 0

SD HSYNC to VSYNC Rising x 0 T Edge Delay (Mode 1 Only)

VSYNC Width (Mode 2 Only)

HSYNC to Pixel Data Adjust 0 0 0 Clk Cycles

4Ch

SD F

Phase

4Dh SD F

4Eh SD F

4Fh

50h SD F

51h SD Closed Captioning Extended Data on Even Fields

52h SD Closed Captioning Extended Data on Even Fields

53h SD Closed Captioning Data on Odd Fields

54h SD Closed Captioning Data on Odd Fields

55h SD Pedestal Register 0 Pedestal on Odd Fields

56h SD Pedestal Register 1 Pedestal on Odd Fields

57h SD Pedestal Register 2 Pedestal on Even Fields

58h SD Pedestal Register 3 Pedestal on Even Fields

00 Mode 0

01 Mode 1

10 Mode 2

11 Mode 3

0 Enabled

1Disabled

00 No Delay

01 2 Clk Cycles

10 4 Clk Cycles

11 6 Clk Cycles

0– 40 IRE

1– 7.5 IRE

01 T

11 T

x1 T

00 1 Clk Cycle

01 4 Clk Cycles

10 16 Clk Cycles

11 128 Clk Cycles

01 1 Clk Cycle

10 2 Clk Cycles

11 3 Clk Cycles

xx xxxxxxSubcarrier Frequency Bit 7–0

xx xxxxxxSubcarrier Frequency Bit 15–8

xx xxxxxxSubcarrier Frequency Bit 23–16

xx xxxxxxSubcarrier Frequency Bit 31–24

xx xxxxxxSubcarrier Phase Bit 9–2

xx xxxxxxExtended Data Bit 7–0

xx xxxxxxExtended Data Bit 15–8

xx xxx xxxData Bit 7–0

xx xxxxxxData Bit 15–8

17 16 15 14 13 12 11 10

25 24 23 22 21 20 19 18

17 16 15 14 13 12 11 10

25 24 23 22 21 20 19 18

0Slave Mode

1 Master Mode

internal SD timing counters.

= 1 Clk Cycle

01T

11T

= 4 Clk Cycles

= 16 Clk Cycles

= 128 Clk Cycles

= 0 Clk Cycle

= 4 Clk Cycles

= 8 Clk Cycles

= 18 Clk Cycles

= T

Setting any of these bits to 1 00h

will disable pedestal on the 00h

line number indicated by the 00h

bit settings. 00h

+ 32 µs

08h

00h

16h

7Ch

F0h

21h

00h

LINE 313 LINE 314LINE 1

SYNC

VSYNC

Figure 15. Timing Register 1 in PAL Mode

REV. B

–23–

ADV7330

SR7–

SR0

59h SD CGMS/WSS 0 SD CGMS Data

5Ah SD CGMS/WSS 1 SD CGMS/WSS Data

5Bh SD CGMS/WSS 2 5Ch SD LSB Register

5Dh SD Y Scale 5Eh SD V Scale 5Fh SD U Scale 60h SD Hue Register 61h

SD Brightness/

62h SD Luma SSAF SD Luma SSAF Gain/Attenuation

63h SD DNR 0 Coring Gain Border

64h SD DNR 1 DNR Threshold

SD CGMS CRC

SD CGMS on Odd Fields

SD CGMS on Even Fields

SD WSS

SD CGMS/WSS Data 7 6 5 4 3 SD LSB for Y Scale Value SD LSB for U Scale Value x x SD U Scale Bit 1–0 SD LSB for V Scale Value x x SD V Scale Bit 1–0 SD LSB for F SD Y Scale Value x x x x x x x x SD Y Scale Bit 7–2 00h SD V Scale Value x x x x x x x x SD V Scale Bit 7–2 00h SD U Scale Value x x x x x x x x SD U Scale Bit 7–2 00h SD Hue Adjust Value x x x x x x x x SD Hue Adjust Bit 7–0 00h SD Brightness Value x x x x x x x SD Brightness Bit 6–0 00h SD Blank WSS Data

Coring Gain Data

Border Area

Block Size Control 0 8 Pixels

Phase x x Subcarrier Phase Bits 1–0

0 Disabled

1 Enabled 0 Disabled 1 Enabled

0 Disabled 1 Enabled

13 12 11 10 9 8

15 14 CGMS Data Bits C15–C14

0 Disabled 1 Enabled 00 000000–4 dB 00 0001100 dB 00 0011004 dB

00 00 No Gain 00 01 +1/16 (–1/8) 00 10 +2/16 (–2/8) 00 11 +3/16 (–3/8) 01 00 +4/16 (–4/8) 01 01 +5/16 (–5/8) 01 10 +6/16 (–6/8) 01 11 10 00 +8/16 (–1)

1 16 Pixels

0 000000

0 000011

… ………… ……

1 1111062

1 1111163 02 Pixels 14 Pixels

19 18 17 16 CGMS data bits C19-C16 0 Disabled 1 Enabled

CGMS Data Bits C13–C8 or WSS Data Bits C13–C8

210

0000No Gain 0001+1/16 (–1/8) 0010+2/16 (–2/8) 0011+3/16 (–3/8) 0100+4/16 (–4/8) 0101+5/16 (–5/8) 0110+6/16 (–6/8) 0111+7/16 (–7/8) 1000+8/16 (–1)

CGMS/WSS Data Bits C7–C0 SD Y Scale Bit 1–0

+7/16 (–7/8)

00h

00h 00h

Line 23

00h

00h In DNR modes the values in the parentheses apply.

00h

REV. B–24–

ADV7330

SR7–

SR0

65h SD DNR 2 DNR Input Select 0 0 1

DNR Mode

DNR Block Offset

66h SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A0 00h 67h SD Gamma A SD Gamma Curve A Data Points x x x x x 68h SD Gamma A SD Gamma Curve A Data Points x x x x x 69h SD Gamma A SD Gamma Curve A Data Points x x x x x 6Ah SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A4 00h 6Bh SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A5 00h 6Ch SD Gamma A SD Gamma Curve A Data Points x x x x x 6Dh SD Gamma A SD Gamma Curve A Data Points x x x x x 6Eh SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A8 00h 6Fh SD Gamma A SD Gamma Curve A Data Points x x x x x x x x A9 00h 70h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B0 00h 71h SD Gamma B SD Gamma Curve B Data Points x x x x x 72h SD Gamma B SD Gamma Curve B Data Points x x x x x 73h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B3 00h 74h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B4 00h 75h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B5 00h 76h SD Gamma B SD Gamma Curve B Data Points x x x x x 77h SD Gamma B SD Gamma Curve B Data Points x x x x x 78h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B8 00h 79h SD Gamma B SD Gamma Curve B Data Points x x x x x x x x B9 00h 7Ah SD Brightness Detect SD Brightness Value 7Bh Field Count Register Field Count

7C Reserved 00h

Reserved 0 Reserved 0 0 must be written to this bit. Reserved 0 0 must be written to this bit. Revision Code

1 0 0 Filter D

0 000 0 Pixel Offset 0 001 1 Pixel Offset … ……… … 1 110 14 Pixel Offset 1 111 15 Pixel Offset

x xxx x

xx Read-Only

0 DNR Mode 1 DNR Sharpness Mode

010Filter B 011Filter C

xxx xxx xxx

xxx xxx

xxxRead-Only

Filter A

A1 A2 A3 00h

A6 00h A7 00h

B1 00h B2 00h

B6 00h B7 00h

0 must be written to this bit.

Values

00h

00h 00h

REV. B

–25–

ADV7330

SR7– SR0

7Dh Reserved 7Eh Reserved 7Fh Reserved 80h 81h 82h Macrovision MV Control Bits x x x x x x x x 00h 83h Macrovision MV Control Bits x x x x x x x x 00h 84h Macrovision MV Control Bits x x x x x x x x 00h 85h 86h Macrovision MV Control Bits 87h Macrovision MV Control Bits x x x x x x x x 00h 88h Macrovision MV Control Bits x x x x x x x x 00h 89h 8Ah 8Bh 8Ch Macrovision MV Control Bits x x x x x x x x 00h 8Dh Macrovision MV Control Bits x x x x x x x x 00h 8Eh 8Fh 90h Macrovision MV Control Bits x x x x x x x x 00h 91h Macrovision MV Control Bits x 00h

Macrovision Macrovision

Macrovision

Macrovision Macrovision Macrovision

Macrovision Macrovision

MV Control Bits MV Control Bits

MV Control Bits

MV Control Bits MV Control Bits MV Control Bits

MV Control Bits MV Control Bits

xx xx

00000

xx x 00h xx x 00h

xx x 00h xx x 00h xx x

xx x xx x

0 must be written to these bits.

Values

00h

00h 00h

REV. B–26–

ADV7330

INPUT CONFIGURATION

Note that the ADV7330 defaults to progressive scan 54 MHz mode on power-up. Address(01h): Input Mode = 011

Standard Definition Address(01h): Input Mode = 000

The 8-bit multiplexed input data is input on Pins Y7–Y0, with Y0 being the LSB. Input standards supported are ITU-R BT.601/656.

In 16-bit input mode the Y pixel data is input on Pins Y7–Y0 and CrCb data on Pins C7–C0.

Input sync signals are optional and are input on the VSYNC_I/P, HSYNC_I/P, and BLANK_I/P pins.

ADV7330

VSYNC_I/P

MPEG2

DECODER

YCrCb

27MHz

HSYNC_I/P BLANK_I/P

CLKIN

Y[7:0]

Figure 16. SD Input Mode

Progressive Scan or HDTV Mode Address(01h): Input Mode 001 or 010, Respectively

YCrCb progressive scan, HDTV, or any other HD YCrCb data can be input in 4:2:2. In 4:2:2 input mode, the Y data is input on Pins Y7–Y0 and the CrCb data on Pins C7–C0.

If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p), or BTA T-1004/1362, the async timing mode must be used.

MPEG2

DECODER

YCrCb

27MHz

ADV7330

CLKIN

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz Address(01h): Input Mode 100 or 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or 54 MHz. The input data is interleaved onto a single 8-bit bus and is input on Pins Y7–Y0. When a 27 MHz clock is supplied, the data is clocked in on the rising and falling edge of the input clock and CLOCK EDGE [Address 01h, Bit 1] must be set accordingly.

The following figures show the possible conditions.

CLKIN

Y7–Y0

3FF 00 00 XY Cb0 Y0 Cr0 Y1

Figure 18a. Cb Data on Rising Edge—Clock Edge Address 01h Bit 1 Should be Set to 0

CLKIN

Y7–Y0

3FF 00 00 XY Y0 Cb0 Y1 Cr0

Figure 18b. Y Data on Rising Edge—Clock Edge Address 01h Bit 1 Should be Set to 1

With a 54 MHz clock, the data is latched on every rising edge.

CLKIN

PIXEL INPUT

DATA

3FF 00 00 XY Cb0 Y0 Cr0 Y1

Figure 18c. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

MPEG2

DECODER

YCrCb

27MHz OR 54MHz

ADV7330

CLKIN

REV. B

INTERLACED

PROGRESSIVE

CbCr

C[7:0]

Y[7:0]

VSYNC_I/P HSYNC_I/P BLANK_I/P

Figure 17. Progressive Scan Input Mode

–27–

INTERLACED

PROGRESSIVE

YCrCb

Y[7:0]

VSYNC_I/P HSYNC_I/P BLANK_I/P

Figure 19. 1 8-Bit PS at 27 MHz or 54 MHz

ADV7330

Table I provides an overview of possible input configurations.

Table I. Input Configurations

Input Input Input Register Format Total Bits Video Pins Subaddress Setting

ITU-R 8 4:2:2 YCrCb Y7–Y0 01h 00h BT.656 48h 00h

16 4:2:2 Y Y7–Y0 01h 00h

YCrCb C7–C0 48h 08h

PS 8 (27 MHz clock) 4:2:2 YCrCb Y7–Y0 10h 40h

13h 40h

8 (54 MHz clock) 4:2:2 YCrCb Y7–Y0 10h 30h

13h 40h

16 4:2:2 Y Y7–Y0 01h 10h

CrCb C7–C0 13h 40h

HDTV 16 4:2:2 Y Y7–Y0 01h 20h

CrCb C7–C0 13h 40h

OUTPUT CONFIGURATION

Tables II and III show which output signals are assigned to the DACs when according control bits are set.

Table II. Output Configuration in SD Mode

RGB/YPrPb Output SD DAC Output 1 SD DAC Output 1 SD DAC Swap 02h, Bit 5 42h, Bit 2 42h, Bit 1 44h, Bit 7 DAC A DAC B DAC C

0000GBR 0001GBR 0010CVBS Luma Chroma 0011CVBS Chroma Luma 0100CVBS B R 0101CVBS B R 0110GLuma Chroma 0111GChroma Luma 1000YPbPr 1001YPbPr 1010CVBS Luma Chroma 1011CVBS Chroma Luma 1100CVBS Pb Pr 1101CVBS Pb Pr 1110YLuma Chroma 1111YChroma Luma

Table III. Output Configuration in HD/PS Mode

HD Input RGB/YPrPb Output HD Color Swap Format 02h, Bit 5 15h, Bit 3 DAC A DAC B DAC C

YCrCb 4:2:2 1 0 Y Pb Pr YCrCb 4:2:2 1 1 Y Pr Pb YCrCb 4:2:2 0 0 G B R YCrCb 4:2:2 0 1 G R B

REV. B–28–

ADV7330

TIMING MODES HD Async Timing Mode [Subaddress 10h, Bit 3,2]

For any input data that does not conform to the standards selectable in input mode, Subaddress 10h, asynchronous timing mode can be used to interface to the ADV7330. Timing control signals for Hsync, Vsync, and Blank have to be programmed by the user. Macrovision and programmable oversampling rates are not available in async timing mode. In async mode, the PLL must be turned off [Subaddress 01h, Bit 1 = 1].

CLK

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

SET ADDRESS 10h,

BIT 6 TO 1

HORIZONTAL SYNC

Figures 20a and 20b show an example of how to program the ADV7330 to accept a different high definition standard other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R BT.1358.

The following truth table must be followed when programming the control signals in async timing mode.

For standards that do not require a tri-sync level, BLANK_I/P must be tied low at all times.

PROGRAMMABLE INPUT TIMING

ACTIVE VIDEO

ANALOG OUTPUT

Figure 20a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility

CLK

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

SET ADDRESS 10h,

BIT 6 TO 1

ANALOG OUTPUT

81 66 66 243 1920

HORIZONTAL SYNC

ab c d e

ACTIVE VIDEO

Figure 20b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signals

REV. B

–29–

ADV7330

Table IV. Async Timing Mode Truth Table

Reference in

HSYNC_I/P VSYNC_I/P BLANK_I/P* Figures 20a and 20b

1 → 0 0 0 or 1 50% point of falling edge of tri-level horizontal sync signal a 00 → 1 0 or 1 25% point of rising edge of tri-level horizontal sync signal b 0 → 1 0 or 1 0 50% point of falling edge of tri-level horizontal sync signal c 10 or 1 0 → 1 50% start of active video d 10 or 1 1 → 0 50% end of active video e

*When async timing mode is enabled, BLANK_I/P (Pin 25) becomes an active high input.

BLANK_I/P is set to active low at Address 10h, Bit 6.

HD Timing Reset [Address 14h, Bit 0]

A timing reset is achieved in setting the HD timing reset control bit at Address 14h from 0 to 1. In this state, the horizontal and vertical counters will remain reset. When this bit is set back to 0, the internal counters will commence counting again. PLL must be powered off by this mode.

The minimum time the pin has to be held high is one clock cycle, otherwise this reset signal might not be recognized. This timing reset applies to the HD timing counters only.

REV. B–30–

ADV7330

SD Real-Time Control, Subcarrier Reset, Timing Reset [Subaddress 44h, Bit 2,1]

Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 44h, Bit 1,2], the ADV7330 can be used in timing reset mode, subcarrier phase reset mode, or RTC mode.

A timing reset is achieved in a low-to-high transition on the RTC_SCR_TR pin (Pin 31). In this state, the horizontal and vertical counters will remain reset. On releasing this pin (set to low), the internal counters will commence counting again, the field count will start on Field 1, and the subcarrier phase will also be reset.

The minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the SD timing counters only.

In subcarrier phase reset, a low-to-high transition on the RTC_SCR_TR pin (Pin 31) will reset the subcarrier phase to zero on the field following the subcarrier phase reset when the SD RTC/TR/SCR control bits at Address 44h are set to 01.

DISPLAY

307 310

NO TIMING RESET APPLIED

START OF FIELD 4 OR 8 FSC PHASE = FIELD 4 OR 8

313 320

This reset signal will have to be held high for a minimum of one clock cycle.

Since the field counter is not reset, it is recommended that the reset signal be applied in Field 7 [PAL] or Field 3 [NTSC]. The reset of the phase will then occur on the next field, i.e., Field 1 being lined up correctly with the internal counters. The field count register at Address 7Bh can be used to identify the number of the active field.

In RTC mode, the ADV7330 can be used to lock to an external video source. The real-time control mode allows the ADV7330 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital data stream in the RTC format (such as an ADV7183A video decoder, see Figure 23), the part will automatically change to the compensated subcarrier frequency on a line by line basis. This digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00h should be written into all four subcarrier frequency registers when this mode is used.

DISPLAY

START OF FIELD 1

307 1 2 3 4 5 6 7 21

TIMING RESET APPLIED

PHASE = FIELD 1

Figure 21. Timing Reset Timing Diagram

DISPLAY

307 310 313 320

NO FSC RESET APPLIED

DISPLAY

307 310 313 320

FSC RESET APPLIED

START OF FIELD 4 OR 8

Figure 22. Subcarrier Reset Timing Diagram

TIMING RESET PULSE

PHASE = FIELD 4 OR 8

PHASE = FIELD 1

RESET PULSE

REV. B

–31–

ADV7330

Reset Sequence

A reset is activated with a high-to-low transition on the RESET pin (Pin 33) according to the Timing Specifications. The ADV7330 will revert to the default output configuration.

Figure 24 illustrates the RESET sequence timing.

SD VCR FF/RW Sync [Subaddress 42h, Bit 5]

In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct

CLKIN

LCC1

COMPOSITE VIDEO

e.g., VCR OR CABLE

H/L TRANSITION

COUNT START

RTC

TIME SLOT: 01

NOTES

FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7330, FSC DSS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS

BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7330.

SEQUENCE BIT. PAL: 0 = LINE NORMAL, 1 = LINE INVERTED. NTSC: 0 = NO CHANGE.

RESET BIT. RESET ADV7330 DSS.

128

ADV7183A

VIDEO

DECODER

SUBCARRIER

LOW

13 0

14 BITS

PHASE

GLL

P17–P10

RESERVED

142119

4 BITS

RTC_SCR_TR

Y7–Y0

number of lines/fields are reached. In rewind mode, this sync signal usually occurs after the total number of lines/fields are reached. Conventionally this means that the output video will have corrupted field signals, one generated by the incoming video and one generated when the internal lines/field counters reach the end of a field.

When the VCR FF/RW sync control is enabled [Subaddress 42h, Bit 5], the lines/field counters are updated according to the incoming vsync signal, and the analog output matches the incoming vsync signal.

This control is available in all slave timing modes except Slave Mode 0.

ADV7330

DAC A

DAC B

DAC C

PLL INCREMENT

VALID

INVALID

SAMPLE

SEQUENCE

BIT

8/LINE

LOCKED

CLOCK

6768

5 BITS

RESERVED

RESET

BIT

RESERVED

RESET

DACs

A, B, C

DIGITAL TIMING

PIXEL DATA

VALID

XXXXXX

Figure 23. RTC Timing and Connections

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

Figure 24.

RESET

Timing Sequence

VALID VIDEO

TIMING ACTIVE

REV. B–32–

ADV7330

Vertical Blanking Interval

The ADV7330 accepts input data that contains VBI data (such as CGMS, WSS, VITS) in SD and HD modes.

For SMPTE 293M (525p) standards, VBI data can be inserted on Lines 13 to 42 of each frame, or Lines 6 to 43 for the ITU-R BT.1358 [625p] standard.

For SD NTSC, this data can be present on Lines 10 to 20; in PAL, on Lines 7 to 22.

If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h, Bit4 for SD], VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave modes.

In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten; it is possible to use VBI in this timing mode as well.

In Slave Mode 1 or 2, the BLANK control bit must be set to enabled [Address 4Ah, Bit 3] to allow VBI data to pass through the ADV7330; otherwise, the ADV7330 automatically blanks the VBI to standard.

If CGMS is enabled and VBI disabled, the CGMS data will nevertheless be available at the output.

SD Subcarrier Frequency Registers [Subaddress 4Ch–4Fh]

Four 8-bit wide registers are used to set up the subcarrier frequency. The value of these registers is calculated using the following equation:

Subcarrier Frequency Register

=×

MHz clk cyclesin onevideo line

#27

Subcarrier FrequencyValuein onevideo line

For example, NTSC mode,

Subcarrier FrequencyValue =

227 5



1716



×=

2 569408542

 





Subcarrier Register Value = 21F07C1Eh

SD F

SD FSC Register 3: 21h

Refer to the MPU Port Description section for details on how to access the subcarrier frequency registers.

Square Pixel Timing [Register 42h, Bit 4]

In square pixel mode, the timing diagrams in Figures 25 and 26 apply.

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

EAV CODE

FF0000X

4 CLOCK

END OF ACTIVE

VIDEO LINE

10801

FF00FFABABA

ANCILLARY DATA

272 CLOCK

344 CLOCK

(HANC)

801

SAV CODE

10FF0

XYC

4 CLOCK

START OF ACTIVE

VIDEO LINE

1280 CLOCK

1536 CLOCK

Figure 25. EAV/SAV Embedded Timing

SYNC

FIELD

PAL = 44 CLOCK CYCLES

NTSC = 44 CLOCK CYCLES

LANK

PIXEL DATA

Cb Y

Cr Y

PAL = 136 CLOCK CYCLES NTSC = 208 CLOCK CYCLES

REV. B

Figure 26. Active Pixel Timing

–33–

ADV7330

)

FILTER SECTION

Table V shows an overview of the programmable filters available on the ADV7330.

Table V. Selectable Filters of the ADV7330

Filter Subaddress

SD Luma LPF NTSC 40h SD Luma LPF PAL 40h SD Luma Notch NTSC 40h SD Luma Notch PAL 40h SD Luma SSAF 40h SD Luma CIF 40h SD Luma QCIF 40h SD Chroma 0.65 MHz 40h SD Chroma 1.0 MHz 40h SD Chroma 1.3 MHz 40h SD Chroma 2.0 MHz 40h SD Chroma 3.0 MHz 40h SD Chroma CIF 40h SD Chroma QCIF 40h SD UV SSAF 42h HD Chroma Input 13h HD Sinc Filter 13h HD Chroma SSAF 13h

HD Sinc Filter

0.5

0.4

0.3

0.2

0.1

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

Filter 27. HD Sinc Filter Enabled

0.5

0.4

0.3

0.2

0.1

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

Figure 28. HD Sinc Filter Disabled

10 15 20 25

FREQUENCY (MHz

10 15 20 25

FREQUENCY (MHz

3050

REV. B–34–

ADV7330

SD Internal Filter Response [Subaddress 40h; Subaddress 42, Bit 0]

The Y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost/attenuation, a CIF response, and a QCIF response. The UV filter supports several different frequency responses including six low-pass responses, aCIF response, and a QCIF response, as can be seen in the typical performance characteristics graphs on the following pages.

If SD SSAF gain is enabled, there is the option of 12 responses in the range of –4 dB to +4 dB [Subaddress 47, Bit 4]. The desired response can be chosen by the user by programming the correct value via the I2C [Subaddress 62h]. The variation of frequency responses can be seen in the typical performance characteristics graphs on the following pages.

In addition to the chroma filters listed in Table VI, the ADV7330 contains an SSAF filter specifically designed for and applicable to the color difference component outputs, U and V.

This filter has a cutoff frequency of about 2.7 MHz and –40 dB at 3.8 MHz, as can be seen in Figure 29. This filter can be controlled with Address 42h, Bit 0.

If this filter is disabled, the selectable chroma filters shown in Table VI can be used for the CVBS or chroma signal.

Table VI. Internal Filter Specifications

Pass-Band Ripple 3 dB Bandwidth

Filter (dB)

(MHz)

Luma LPF NTSC 0.16 4.24 Luma LPF PAL 0.1 4.81 Luma Notch NTSC 0.09 2.3/4.9/6.6 Luma Notch PAL 0.1 3.1/5.6/6.4 Luma SSAF 0.04 6.45 Luma CIF 0.127 3.02 Luma QCIF Monotonic 1.5 Chroma 0.65 MHz Monotonic 0.65 Chroma 1.0 MHz Monotonic 1 Chroma 1.3 MHz 0.09 1.395 Chroma 2.0 MHz 0.048 2.2 Chroma 3.0 MHz Monotonic 3.2 Chroma CIF Monotonic 0.65 Chroma QCIF Monotonic 0.5

NOTES

Pass-band ripple refers to the maximum fluctuations from the 0 dB response in the pass band, measured in (dB). The pass band is defined to have 0 (Hz) to fc (Hz) frequency limits for a low-pass filter, 0 (Hz) to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, f2 are the –3 dB points.

3 dB bandwidth refers to the –3 dB cutoff frequency.

EXTENDED UV FILTER MODE

–10

–20

–30

GAIN (dB)

–40

–50

–60

6543210

FREQUENCY (MHz)

Figure 29. UV SSAF Filter

REV. B

–35–

ADV7330–Typical Performance Characteristics

PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 1. PS—UV (8× Oversampling Filter (Linear))

PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

1.0

0.5

–0.5

–1.0

GAIN (dB)

–1.5

–2.0

–2.5

–3.0

Y PASS BAND IN PS OVERSAMPLING MODE

122468100

FREQUENCY (MHz)

TPC 4. PS—Y (8× Oversampling Filter (Pass Band))

Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 2. PS—UV (8× Oversampling Filter (SSAF))

Y RESPONSE IN PS OVERSAMPLING MODE

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

20020 40 60 80 100 120 140 160 1800

TPC 3. PS—Y (8× Oversampling Filter)

–80

FREQUENCY (MHz)

TPC 5. HDTV—UV (2× Oversampling Filter)

Y RESPONSE IN HDTV OVERSAMPLING MODE

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

FREQUENCY (MHz)

TPC 6. HDTV—Y (2× Oversampling Filter)

14020 40 60 80 100 1200

REV. B–36–

ADV7330

)

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz

TPC 7. Luma NTSC Low-Pass Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

TPC 8. Luma PAL Low-Pass Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

121086420

–70

FREQUENCY (MHz)

121086420

TPC 10. Luma PAL Notch Filter

Y RESPONSE IN SD OVERSAMPLING MODE

–10

–20

–30

–40

GAIN (dB)

–50

–60

–70

–80

121086420

020406080100 120 140 160 180 200

FREQUENCY (MHz)

TPC 11. Y-16× Oversampling Filter

REV. B

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

FREQUENCY (MHz)

TPC 9. Luma NTSC Notch Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

121086420

–70

FREQUENCY (MHz)

121086420

TPC 12. Luma SSAF Filter up to 12 MHz

–37–

ADV7330

)

–2

–4

–6

MAGNITUDE (dB)

–8

–10

–12

01234 7

FREQUENCY (MHz)

TPC 13. Luma SSAF Filter—Programmable Responses

MAGNITUDE (dB)

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

TPC 16. Luma CIF LP Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–1

01234 7

FREQUENCY (MHz

TPC 14. Luma SSAF Filter—Programmable Gain

–1

–2

MAGNITUDE (dB)

–3

–4

–5

01234 7

FREQUENCY (MHz

TPC 15. Luma SSAF Filter—Programmable Attenuation

–70

02468 12

FREQUENCY (MHz)

TPC 17. Luma QCIF LP Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

TPC 18. Chroma 3.0 MHz LP Filter

REV. B–38–

ADV7330

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

TPC 19. Chroma 2.0 MHz LP Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

TPC 22. Chroma 0.65 MHz LP Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

TPC 20. Chroma 1.3 MHz LP Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

TPC 21. Chroma 1.0 MHz LP Filter

–60

–70

02468 12

FREQUENCY (MHz)

TPC 23. Chroma CIF LP Filter

–10

–20

–30

–40

MAGNITUDE (dB)

–50

–60

–70

02468 12

FREQUENCY (MHz)

TPC 24. Chroma QCIF LP Filter

REV. B

–39–

ADV7330

COLOR CONTROLS AND RGB MATRIX

HD Y Level, Cr Level, Cb Level [Subaddress 16h–18h]

Three 8-bit wide registers at Addresses 16h, 17h, 18h are used to program the output color of the internal HD test pattern generator, whether it is the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls on external pixel data input. For this purpose, the RGB matrix is used.

The standard used for the values for Y and the color difference signals to obtain white, black, and the saturated primary and complementary colors conforms to the ITU-R BT.601-4 standard.

Table VII shows sample color values to be programmed into the color registers when output standard selection is set to EIA 770.2.

Table VII. Sample Color Values for EIA770.2 Output Standard Selection

Sample Color Y Value CR Value CB Value

White 235 (EB) 128 (80) 128 (80) Black 16 (10) 128(80) 128 (80) Red 81 (51) 240 (F0) 90 (5A) Green 145 (91) 34 (22) 54 (36) Blue 41 (29) 110 (6E) 240 (F0) Yellow 210 (D2) 146 (92) 16 (10) Cyan 170 (AA) 16 (10) 166 (A6) Magenta 106 (6A) 222 (DE) 202 (CA)

Programming the RGB Matrix

The RGB matrix should be enabled [Address 02h, Bit 3], the output should be set to RGB [Address 02h, Bit 5], Sync on PrPb should be disabled [Address 15h, Bit 2], and Sync on RGB is optional [Address 02h, Bit 4].

GY at addresses 03h and 05h controls the output levels on the green signal, BU at 04h and 08h the blue signal output levels, and RV at 04h and 09h the red output levels. To control YPrPb output levels, YPrPb output should be enabled [Address 02h, Bit 5]. In this case, GY [Address 05h; Address 03, Bit 0–1] is used for the Y output, RV [Address 09h; Address 04, Bit 0–1] is used for the Pr output, and BU [Address 08h; Address 04h, Bit 2–3] is used for the Pb output.

If RGB output is selected, the RGB matrix scaler uses the following equations:

GGYYGUPb GV

=×+×+×

BGYYBU Pb

=×+×

RGYYRV

=×+×PrPr

If YPrPb output is selected, the following equations are used:

YGYY

=×

UBUPb

=×

VRV

=×Pr

On power-up, the RGB matrix is programmed with default values.

Table VIII. RGB Matrix Default Values

HD RGB Matrix [Subaddress 03h–09h]

When the programmable RGB matrix is disabled [Address 02h, Bit 3], the internal RGB matrix takes care of all YCrCb to YPrPb or RGB scaling according to the input standard programmed into the device.

When the programmable RGB matrix is enabled, the color components are converted according to the 1080i standard [SMPTE 274M]:

YRGB

'. '. '. '

=++

0 2126 0 7152 0 0722

CB B Y

'[./( . )](' ')

=− −

05 100722

CR R Y

'[./( . )](' ')

=− −

05 102126

This is reflected in the preprogrammed values for GY = 138Bh, GU = 93h, GV = 3B, BU = 248h, RV = 1F0.

If another input standard is used, the scale values for GY, GU, GV, BU, and RV have to be adjusted according to this input standard. The user must consider that the color component conversion might use different scale values. For example, SMPTE 293M uses the following conversion:

YRGB

'. '. '. '

=++

0 299 0 587 0 114

CB B Y

'[./( . )](' ')

=− −

05 1 0114

CR R Y

'[./( . )](' ')

=− −

05 1 0299

The programmable RGB matrix can be used to control the HD output levels in cases where the video output does not confirm to standards due to altering the DAC output stages such as termination resistors. The programmable RGB matrix is used for external HD data and is not functional when the HD test pattern is enabled.

Address Default

03h 03h 04h F0h 05h 4Eh 06h 0Eh 07h 24h 08h 92h 09h 7Ch

When the programmable RGB matrix is not enabled, the ADV7330 automatically scales YCrCb inputs to all standards supported by this part.

SD Luma and Color Control [Subaddresses 5Ch, 5Dh, 5Eh, 5Fh]

SD Y SCALE, SD Cr SCALE, and SD Cb SCALE are 10-bit wide control registers to scale the Y, U, and V output levels.

Each of these registers represents the value required to scale the U or V level from 0.0 to 2.0, and the Y level from 0.0 to 1.5 of its initial level. The value of these 10 bits is calculated using the following equation:

YUor V Scalar Value Scale Factor,, =×512

For example:

Scale factor = 1.18

Y, U, or V Scalar Value = 1.18 × 512 = 665.6 Y, U, or V Scalar Value = 665 (rounded to the nearest integer) Y, U, or V Scalar Value = 1010 0110 01b

Address 5Ch, SD LSB Register = 15h Address 5Dh, SD Y Scale Register = A6h Address 5Eh, SD V Scale Register = A6h Address 5Fh, SD U Scale Register = A6h

REV. B–40–

ADV7330

SD Hue Adjust Value [Subaddress 60h]

The hue adjust value is used to adjust the hue on the composite and chroma outputs.

These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. The ADV7330 provides a range of ±22.5° increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 80h. FFh and 00h represent the upper and lower limits (respectively) of adjustment attainable.

(Hue Adjust) [°] = 0.17578125° × (HCRd–128), for positive hue adjust value.

For example, to adjust the hue by +4°, write 97h to the hue adjust value register:

  

0 17578125

*rounded to the nearest integer



128 105 97

+= =dh

 

To adjust the hue by –4°, write 69h to the hue adjust value register:

−

  

0 17578125

*rounded to the nearest integer

SD Brightness Control [Subaddress 61h]



128 105 69

+= =

 

*dh

The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the scaled Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and PAL, the setup can vary from –7.5 IRE to +15 IRE.

The brightness control register is an 8-bit wide register. Seven bits of this 8-bit register are used to control the brightness level. This brightness level can be a positive or negative value.

For example: Standard: NTSC with pedestal. To add +20 IRE brightness level, write 28h to Address 61h, SD brightness.

Standard: PAL. To add –7 IRE brightness level, write 72h to Address 61h, SD brightness.

2 015631

IREValue

[]

72015631 14 109417 0001110

[]

0001110 1110010 72

[]

Table IX. Brightness Control Values*

into twos complement

[]

Setup Setup Level in Level in Setup NTSC with NTSC No Level in SD Pedestal Pedestal PAL Brightness

22.5 IRE 15 IRE 15 IRE 1Eh 15 IRE 7.5 IRE 7.5 IRE 0Fh

7.5 IRE 0 IRE 0 IRE 00h 0 IRE –7.5 IRE –7.5 IRE 71h

*Values in the range of 3Fh to 44h might result in an invalid output signal.

SD Brightness Detect [Subaddress 7Ah]

The ADV7330 allows monitoring of the brightness level of the incoming video data. Brightness detect is a read-only register.

Double Buffering [Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]

Double-buffered registers are updated once per field on the falling edge of the VSYNC signal. Double buffering improves the overall performance since modifications to register settings will not be made during active video, but take effect on the start of the active video.

Double buffering can be activated on the following HD registers: HD Gamma A and Gamma B curves, and HD CGMS registers. Double buffering can be activated on the following SD registers: SD Gamma A and Gamma B curves, SD Y scale, SD U scale, SD V scale, SD brightness, SD closed captioning, and SD Macrovision Bits 5–0.

REV. B

[]

SD BrightnessValue H

[

IREValue H

[[

20 2 015631 40 31262 28

×=

2 015631

]]

×= =

HHH

100 IRE

0 IRE

]

NTSC WITHOUT PEDESTAL

NO SETUP

VALUE ADDED

Figure 30. Examples of Brightness Control Values

POSITIVE SETUP

VALUE ADDED

–41–

NEGATIVE SETUP

VALUE ADDED

+7.5 IRE

–7.5 IRE

ADV7330

PROGRAMMABLE DAC GAIN CONTROL

DACs A, B, and C are controlled by Reg 0B. The I2C control registers will adjust the output signal gain up or down from its absolute level.

CASE A

GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0Ah, 0Bh

700mV

300mV

CASE B

700mV

300mV

NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0Ah, 0Bh

Figure 31. Programmable DAC Gain—Positive and Negative Gain

In Case A, the video output signal is gained. The absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal.

In Case B, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal.

The range of this feature is specified for ±7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC tune feature can change this output current from 4.008 mA (–7.5%) to 4.658 mA (+7.5%).

The reset value of the vid_out_ctrl registers is 00h → nominal DAC output current. Table X is an example of how the output current of the DACs varies for a nominal 4.33 mA output current.

Table X.

DAC Current

0100 0000 (40h) 4.658 7.5000 0011 1111 (3Fh) 4.653 7.3820 0011 1110 (3Eh) 4.648 7.3640

... ... ...

0000 0010 (02h) 4.43 0.0360 0000 0001 (01h) 4.38 0.0180 0000 0000 (00h) 4.33 0.0000 (I

C Reset Value,

Nominal) 1111 1111 (FFh) 4.25 –0.0180 1111 1110 (FEh) 4.23 –0.0360

... ... ...

1100 0010 (C2h) 4.018 –7.3640 1100 0001 (C1h) 4.013 –7.3820 1100 0000 (C0h) 4.008 –7.5000

REV. B–42–

ADV7330

Gamma Correction [Subaddress 24h–37h for HD, Subaddress 66h–79h for SD]

Gamma correction is available for SD and HD video. For each standard there are 20 8-bit wide registers. They are used to program the gamma correction curves A and B. HD gamma curve A is programmed at Addresses 24h–2Dh, HD gamma curve B at 2Eh–37h. SD gamma curve A is programmed at Addresses 66h–6Fh, SD gamma curve B at Addresses 70h–79h.

Generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used.

Gamma correction uses the function

Signal Signal

()

OUT IN



where  = gamma power factor.

Gamma correction is performed on the luma data only. The user has the choice to use two different curves, curve A or curve B. At any one time, only one of these curves can be used. The response of the curve is programmed at 10 predefined locations. In changing the values at these locations, the gamma curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed.

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

300

250

200

150

100

SIGNAL OUTPUT

0.5

For the length of 16 to 240, the gamma correction curve has to be calculated as follows:



yx=

where:

y = gamma corrected output x = linear input signal

 = gamma power factor

To program the gamma correction registers, the seven values for y have to be calculated using the following formula:





240 16

()







−()16

−

240 16 16

×−

()

 



where:

= Value for x along x-axis at points

(n–16)

n = 24, 32, 48, 64, 80, 96, 128, 160, 192 or 224

= Value for y along the y-axis, which has to be written into

the gamma correction register

For example:

= [(8 / 224)

= [16 / 224)

= [(32 / 224)

= [(48 / 224)

= [(64 / 224)

= [(80 / 224)

= [(112 / 224)

128

= [(144 / 224)

160

= [(176 / 224)

192

= [(208 / 224)

*rounded to the nearest integer

224

0.5

× 224] + 16 = 58*

0.5

× 224] + 16 = 76*

0.5

× 224] + 16 = 101*

0.5

× 224] + 16 =120*

0.5

× 224] + 16 =136*

0.5

× 224] + 16 = 150*

0.5

× 224] + 16 = 174*

0.5

× 224] + 16 = 195*

0.5

× 224] + 16 = 214*

0.5

× 224] + 16 = 232*

The gamma curves in Figure 32 and 33 are examples only; any user defined curve is acceptable in the range of 16–240.

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

300

VARIOUS GAMMA VALUES

GAMMA CORRECTED AMPLITUDE

SIGNAL INPUT

50 100 150 200 250

LOCATION

Figure 32. Signal Input (Ramp) and Signal Output for Gamma 0.5

REV. B

–43–

250

200

150

100

GAMMA CORRECTED AMPLITUDE

SIGNAL INPUT

50 100 150 200 250

0.3

0.5

1.5

1.8

LOCATION

Figure 33. Signal Input (Ramp) and Selectable Gamma Output Curves

ADV7330

HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddress 20h, 38h–3Dh]

There are three filter modes available on the ADV7330: sharpness filter mode and two adaptive filter modes.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges shown in the figures below, the following register settings must be used: HD sharpness filter must be enabled and HD adaptive filter enable must be set to disabled.

To select one of the 256 individual responses, the according gain values for each filter, which range from –8 to +7 , must be programmed into the HD sharpness filter gain register at Address 20h.

HD Adaptive Filter Mode

The HD adaptive filter threshold A, B, C registers, the HD adaptive filter gain 1, 2, 3 registers, and the HD sharpness filter gain register are used in Adaptive Filter mode. To activate the adaptive filter control, HD sharpness filter must be enabled and HD adaptive filter gain must be enabled.

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

FREQUENCY (MHz)

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5 FREQUENCY (MHz)

FILTER B RESPONSE (Gain Kb)

INPUT

SIGNAL:

STEP

1.5

1.4

1.3

1.2

1.1

1.0

0.9

MAGNITUDE

0.8

0.7

0.6

0.5

FILTER A RESPONSE (Gain Ka)

Figure 34. Sharpness and Adaptive Filter Control Block

The derivative of the incoming signal is compared to the three programmable threshold values: HD adaptive filter threshold A, B, C. The recommended threshold range is from 16–235, although any value in the range of 0–255 can be used.

The edges can then be attenuated with the settings in HD adaptive filter gain 1, 2, 3 registers and HD sharpness filter gain register. According to the settings of the HD adaptive filter mode control, there are two Adaptive Filter modes available:

1. Mode A is used when adaptive filter mode is set to 0. In this case, Filter B (LPF) will be used in the adaptive filter block. Also, only the programmed values for Gain B in the HD sharpness filter gain, HD adaptive filter gain 1, 2, 3 are applied when needed. The Gain A values are fixed and cannot be changed.

2. Mode B is used when adaptive filter gain is set to 1. In this mode a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the HD sharpness filter gain, HD adaptive filter gain 1, 2, 3 become active when needed.

1.6

1.5

1.4

1.3

1.2

1.1

MAGNITUDE RESPONSE (Linear Scale)

1.0 024681012

FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7

FREQUENCY (MHz)

REV. B–44–

ADV7330

HD Sharpness Filter and Adaptive Filter Application Examples

HD Sharpness Filter Application

The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in the figures below. Input data was generated by an external signal source.

Table XI.

Address Setting Figure 35

00h FCh 01h 10h 02h 20h 10h 00h 11h 81h 20h 00h a 20h 08h b 20h 04h c 20h 40h d 20h 80h e 20h 22h f

The effect of the sharpness filter can also be seen when using the internally generated cross hatch pattern.

Table XII.

Address Register Setting

00h FCh 01h 10h 02h 20h 10h 00h 11h 85h 20h 99h

In toggling the sharpness filter enable bit [Address 11h, Bit 8], it can be seen that the line contours of the crosshatch pattern change their sharpness.

CH1 500mV M 4.00s CH1

REF A 500mV 4.00s 1 9.99978ms

ALL FIELDS

CH1 500mV M 4.00s CH1

REF A 500mV 4.00s 1 9.99978ms

ALL FIELDS

Figure 35. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value

REV. B

–45–

ADV7330

ADAPTIVE FILTER CONTROL APPLICATION

Figures 36 and 37 show a typical signal to be processed by the adaptive filter control block.

: 692mV @: 446mV

: 332ns @: 12.8ms

Figure 36. Input Signal to Adaptive Filter Control

: 692mV @: 446mV

: 332ns @: 12.8ms

Figure 37. Output Signal After Adaptive Filter Control

The following register settings were used to obtain the results shown in Figure 37, i.e., to remove the ringing on the Y signal.

Input data was generated by an external signal source.

When changing the adaptive filter mode to Mode B [Address 15h, Bit 6], the following output can be obtained:

: 674mV

@: 446mV

: 332ns

@: 12.8ms

Figure 38. Output Signal from Adaptive Filter Control

The adaptive filter control can also be demonstrated using the internally generated crosshatch test pattern and toggling the adaptive filter control bit [Address 15h, Bit 7].

Table XIV.

Address Register Setting

00h FCh 01h 10h 02h 20h 10h 00h 11h 85h 15h 80h 20h 00h 38h ACh 39h 9Ah 3Ah 88h 3Bh 28h 3Ch 3Fh 3Dh 64h

Table XIII.

Address Register Setting

00h FCh 01h 10h 02h 20h 10h 00h 11h 81h 15h 80h 20h 00h 38h ACh 39h 9Ah 3Ah 88h 3Bh 28h 3Ch 3Fh 3Dh 64h

All other registers are set as normal.

REV. B–46–

ADV7330

SD Digital Noise Reduction [Subaddress 63h, 64h, 65h]

DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal [DNR input select]. The absolute value of the filter output is compared to a programmable threshold value ['DNR threshold control]. There are two DNR modes available: DNR mode and DNR sharpness mode.

In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount [coring gain border, coring gain data] of this noise signal will be subtracted from the original signal.

In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold now being identified as a valid signal, a fraction of the signal [coring gain border, coring gain data] will be added to the original signal in order to boost high frequency components and to sharpen the video image.

In MPEG systems, it is common to process the video information in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels × 16 pixels for MPEG1 systems [block size control]. DNR can be applied to the resulting block transition areas, which are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels [border area].

Y DATA

INPUT

Y DATA

INPUT

DNR MODE

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR SHARPNESS MODE

NOISE SIGNAL PATH

INPUT FILTER

BLOCK

MAIN SIGNAL PATH

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

< THRESHOLD?

FILTER OUTPUT

> THRESHOLD

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

FILTER

OUTPUT

> THRESHOLD?

FILTER OUTPUT

< THRESHOLD

SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL

–

DNR OUT

ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL

DNR OUT

Figure 39. DNR Block Diagram

It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset.

The digital noise reduction registers are three 8-bit wide registers. They are used to control the DNR processing.

Coring Gain Border [Address 63h, Bits 3–0]

These four bits are assigned to the gain factor applied to border areas.

In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.

Coring Gain Data [Address 63h, Bits 7–4]

These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block.

APPLY BORDER CORING GAIN

OFFSET CAUSED BY VARIATIONS IN INPUT TIMING

DNR27 – DNR24 = 01H

APPLY DATA CORING GAIN

OXXXXXXOOXXXXXXO

Figure 40. DNR Block Offset Control

DNR Threshold [Address 64h, Bits 5–0]

These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.

Border Area [Address 64h, Bit 6]

In setting this bit to a Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to a Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.

720485 PIXELS

(NTSC)

88 PIXEL BLOCK 88 PIXEL BLOCK

2 PIXEL

BORDER

DATA

REV. B

Figure 41. DNR Border Area

–47–

ADV7330

Block Size Control [Address 64h, Bit 7]

This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic 1 defines a 16 pixel × 16 pixel data block and a Logic 0 defines an 8 pixel × 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.

DNR Input Select Control [Address 65h, Bit 2–0]

Three bits are assigned to select the filter that is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that will be DNR processed. Figure 42 shows the filter responses selectable with this control.

1.0 FILTER D

0.8

FILTER C

0.6

MAGNITUDE

0.4

0.2

012 3456

FILTER B

FILTER A

FREQUENCY (Hz)

Figure 42. DNR Input Select

DNR Mode Control [Address 65h, Bit 4]

This bit controls the DNR mode selected. A Logic 0 selects DNR mode, a Logic 1 selects DNR sharpness mode.

DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1.

When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. The overall effect is that the signal will be boosted (similar to using Extended SSAF filter).

Block Offset Control [Address 65h, Bits 7–4]

Four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.

SD ACTIVE VIDEO EDGE [Subaddress 42h, Bit 7]

When the active video edge is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled in such a way that maximum transitions on these pixels are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8. All other active video passes through unprocessed.

SAV/EAV STEP EDGE CONTROL

The ADV7330 has the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing.

An algorithm monitors SAV and EAV and governs when the edges are too fast. The result will be reduced ringing at the start and end of active video for fast transitions.

Subaddress 42h, Bit 7 = 1 enables this feature.

LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED

100 IRE

0 IRE

Figure 43. Example for Active Video Edge Functionality

LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED

100 IRE

87.5 IRE

50 IRE

12.5 IRE 0 IRE

REV. B–48–

ADV7330

VOLTS

024

IRE:FLT

100

0.5

–50

Figure 44. Address 42h, Bit 7 = 0

VOLTS

IRE:FLT

100

F2 L135

681012

0.5

–50

02–2 4 6 8 10 12

L135

Figure 45. Address 42h, Bit 7 = 1

REV. B

–49–

ADV7330

BOARD DESIGN AND LAYOUT CONSIDERATIONS DAC Termination and Layout Considerations

The ADV7330 contains an on-board voltage reference. The V

REF

pin is normally terminated to VAA through a 0.1 µF capacitor when the internal V be used with an external V

The RSET resistors connected between the R

is used. Alternatively, the ADV7330 can

REF

(AD1580).

REF

pin and AGND

SET

are used to control the full-scale output current and therefore the DAC voltage output levels. For full-scale output, R have a value of 3040 Ω. The R

has a value of 300 Ω for full-scale output.

LOAD

values should not be changed.

SET

must

VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER

Output buffering on all three DACs is necessary in order to drive output devices, such as SD or HD monitors.

Analog Devices produces a range of suitable op amps for this application, such as the AD8061. More information on line driver buffering circuits is given in the relevant op amp data sheets.

An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7330 is connected to a device that requires this filtering.

The filter specifications vary with the application.

Table XV. External Filter Requirements

Cutoff Frequency Attenuation

Application Oversampling (MHz) –50 dB @ (MHz)

SD 2× >6.5 20.5 SD 16× >6.5 209.5 PS 1× >12.5 14.5 PS 8× >12.5 203.5 HDTV 1× >30 44.25 HDTV 2× >30 118.5

Table XVI shows possible output rates from the ADV7330.

Table XVI.

Input Mode PLL Output Address 01h, Bit 6–4 Address 00h, Bit 1 Rate

SD Off 27 MHz (2×)

On 216 MHz (16×)

PS Off 27 MHz (1×)

On 216 MHz (8×)

HDTV Off 74.25 MHz (1×)

On 148.5 MHz (2×)

DAC

OUTPUT

10H

22pF600

600

560

75

BNC OUTPUT

Figure 46. Example for Output Filter for SD, 16× Oversampling

–10

–20

–30

–40

GAIN (dB)

–50

GROUP DELAY (sec)

–60

–70

–80

1M 10M 100M

CIRCUIT FREQUENCY RESPONSE

PHASE (Deg)

FREQUENCY (Hz)

MAGNITUDE (dB)

–30

–60

–90

–120

–150

–180

–210

–240

24n

21n

18n

15n

12n

Figure 47. Filter Plot for Output Filter for SD, 16× Oversampling

REV. B–50–

ADV7330

DAC

OUTPUT

4.7H

6.8pF 600

6.8pF600

560

Figure 48. Example Output Filter for PS,

Oversampling

DAC OUTPUT

300

75

220nH470nH

75

82pF33pF

500

Figure 49. Example Output Filter for HDTV,

Oversampling

–10

–20

–30

GROUP DELAY (Sec)

–40

–50

GAIN (dB)

–60

–70

–80

–90

1M 10M 100M 1G

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

FREQUENCY (Hz)

Figure 50. Filter Plot for Output Filter for PS,

Oversampling

–10

–20

–30

GAIN (dB)

–40

–50

GROUP DELAY (Sec)

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

75

500

PHASE (Deg)

BNC OUTPUT

480

18n

400

16n

320

14n

240

12n

160

10n

–80

–160

–240

480

18n

360

15n

240

12n

120

–120

PC BOARD LAYOUT CONSIDERATIONS

The ADV7330 is optimally designed for low noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7330, it is imperative that great care be given to the PC board layout.

The layout should be optimized for lowest noise on the ADV7330 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of V

and GND_IO pins should be kept as short as possible to

DD_IO

and AGND, VDD and DGND, and

minimized inductive ringing.

It is recommended that a 4-layer printed circuit board is used with power and ground planes separating the layer of the signal carrying traces of the components and solder-side layer. Component placement should be carefully considered in order to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry.

There should be a separate analog ground plane and a separate digital ground plane.

Power planes should encompass a digital power plane and an analog power plane. The analog power plane should contain the DACs and all associated circuitry, V

circuitry. The digital

REF

power plane should contain all logic circuitry.

The analog and digital power planes should be individually connected to the common power plane at one single point through a suitable filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB’s ground plane. As well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry.

To avoid crosstalk between the DAC outputs, it is recommended to leave as much space as possible between the tracks of the individual DAC output pins. The addition of ground tracks between outputs is also recommended.

Supply Decoupling

Noise on the analog power plane can be further reduced by the use of decoupling capacitors.

Optimum performance is achieved by the use of 10 nF and 0.1 µF ceramic capacitors. Each group of V

, VDD, or V

DD_IO

pins should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance.

A 1 µF tantalum capacitor is recommended across the V

supply

in addition to 10 nF ceramic capacitor. See Figure 52.

–60

1M 10M 100M 1G

FREQUENCY (Hz)

Figure 51. Example for Output Filter HDTV, 2× Oversampling

REV. B

–240

–51–

ADV7330

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane.

Due to the high clock rates used, long clock lines to the ADV7330 should be avoided to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane.

POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP

0.1F

COMP36V

I2C

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

VDDV

ADV7330

10, 56

DD_IO

REF

5k

DD_IO

Analog Signal Interconnect

The ADV7330 should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch.

For optimum performance, the analog outputs should each be source and load terminated, as shown in Figure 52. The termination resistors should be as close as possible to the ADV7330 to minimize reflections.

For optimum performance, it is recommended that all decoupling and external components relating to ADV7330 be located on the same side of the PCB and as close as possible to the ADV7330.

Any unused inputs should be tied to ground.

10nF 1F

10nF 0.1F

100nF

1.1k

DD_IO

RECOMMENDED EXTERNAL AD1580 FOR OPTIMUM PERFORMANCE

UNUSED

INPUTS

SHOULD BE

GROUNDED

4.7k

4.7F

C0–C7

Y0–Y7

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

820pF

680

3.9nF

RESET

CLKIN

EXT_LF

GND_ IO64AGND40DGND

DAC A

DAC B

DAC C

SCLK

SDA

ALSB

SET

2, 11, 14, 15, 51–55, 57–63

300

100

3040

CVBS/GREEN/Y

LUMA/BLUE/Pb

CHROMA/RED/Pr

DD_IO

5k

DD_IO

5k

SELECTION HERE DETERMINES DEVICE ADDRESS

5k

C BUS

Figure 52. ADV7330 Circuit Layout

REV. B–52–

ADV7330

APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM HD CGMS Data Registers 2–0 [Subaddress 21h, 22h, 23h]

HD CGMS is available in 525p mode only, conforming to ‘CGMS-A EIA-J CPR1204-1, Transfer Method of Video ID Information Using Vertical Blanking Interval (525p system), March 1998’, and IEC61880, 1998, Video systems (525/60) — video and accompanied data using the vertical blanking intervalanalog interface.

When HD CGMS is enabled [Subaddress 12h, Bit 6 = 1], CGMS data is inserted on Line 41. The HD CGMS data registers are to be found at address 21h, 22h, 23h.

SD CGMS Data Registers 2–0 [Subaddress 59h, 5Ah, 5Bh]

The ADV7330 supports copy generation management system (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can be transmitted only when the ADV7330 is configured in NTSC mode. The CGMS data is 20 bits long; the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit; see Figure 54.

HD CGMS Data Registers [Subaddress 12h, Bit 6]

The ADV7330 supports copy generation management system (CGMS) in HDTV mode (720p and 1080i) in accordance to EIAJ CPR-1204-2. The HD CGMS data registers are to be found at Addresses 21h, 22h, and 23h.

720p System

CGMS data is applied to Line 24 of the luminance vertical blanking interval.

1080i System

CGMS data is applied to Line 19 and also on Line 582 of the luminance vertical blanking interval.

CGMS CRC Functionality

If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC [Subaddress 12h, Bit 7] is set to Logic 1, the last six bits, C19–C14, which comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7330 based on the lower 14 bits (C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x

+ x + 1 with a preset value of 111111. If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC [Subaddress 12h, Bit 7] is set to Logic 0, all 20 bits (C0–C19) are output directly from the CGMS registers (no CRC calculated, must be calculated by the user).

Function of CGMS Bits

Word 0–6 bits; Word 1–4 bits; Word 2–6 bits; CRC 6 bits; CRC polynomial = x

+ x + 1 (preset to 111111).

Table XVII.

Bit Function

WORD0 1 0 B1 Aspect ratio 16:9 4:3 B2 Display format Letterbox Normal B3 Undefined

WORD0 B4, B5, B6 Identification information about video and

other signals (e.g., audio)

WORD1 B7, B8, B9, B10 Identification signal incidental to Word 0

WORD2 B11, B12, B13, B14 Identification signal and information

incidental to Word 0

REV. B

–53–

ADV7330

70% 10%

+700mV

0mV

–300mV

5.8s 0.15s 6T

CRC SEQUENCE

REF

BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

21.2s 0.22s 22T

T = 1/(fH  33) = 963ns

= HORIZONTAL SCAN FREQUENCY

T 30ns

Figure 53. PS CGMS Waveform

+700mV

70% 10%

0mV

–300mV

+700mV

70% 10%

+100 IRE

+70 IRE

0 IRE

–40 IRE

11.2s

3.128s 90ns

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

49.1s 0.5s

2.235s 20ns

Figure 54. SD CGMS Waveform

CRC SEQUENCE

REF

BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

T 30ns

17.2s 160ns 22 T

T = 1/(f

 1650/58) = 781.93ns

= HORIZONTAL SCAN FREQUENCY

Figure 55. HDTV 720p CGMS Waveform

CRC SEQUENCE

REF

BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

CRC SEQUENCE

0mV

–300mV

4.15s 60ns

T 30ns

22.84s 210ns 22 T

T = 1/(fH  2200/77) = 1.038s

= HORIZONTAL SCAN FREQUENCY

Figure 56. HDTV 1080i CGMS Waveform

REV. B–54–

ADV7330

APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddress 59h, 5Ah, 5Bh]

The ADV7330 supports wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the ADV7330 is configured in PAL mode. The WSS data is 14 bits long, and the function of each of these bits is shown in Table XVII. The WSS data is

Table XVIII. Function of WSS Bits

Bit Description

Bit 0–Bit 2 Aspect Ratio/Format/Position

Bit 3 Odd Parity Check of Bit 0 to Bit 2

B0, B1, B2 B3 Aspect Ratio Format Position 0001 4:3 Full Format N/A 1000 14:9 Letterbox Center 0100 14:9 Letterbox Top

1101 16:9 Letterbox Center 0010 16:9 Letterbox Top 1011 >16:9 Letterbox Center 0111 14:9 Full Format Center 111 0 16:9 N/A N/A

B4 0Camera Mode 1Film Mode

B5 0 Standard Coding 1Motion Adaptive Color Plus

preceded by a run-in sequence and a start code (see Figure 57). If SD WSS [Address 59h, Bit 7] is set to Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 µs from the falling edge of HSYNC) is available for the insertion of video.

It is possible to blank the WSS portion of Line 23 with Subaddress 61h, Bit 7.

Bit Description

B6 0No Helper 1Modulated Helper

B7 Reserved

B9 B10 0 0 No Open Subtitles 1 0 Subtitles in Active Image Area 0 1 Subtitles out of Active Image Area 1 1 Reserved

B11 0No Surround Sound Information 1 Surround Sound Mode

B12 Reserved

B13 Reserved

500mV

11.0s

RUN-IN

SEQUENCE

START

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10

CODE

38.4s

42.5s

Figure 57. WSS Waveform Diagram

W11

W12

W13

ACTIVE

VIDEO

REV. B

–55–

ADV7330

APPENDIX 3—SD CLOSED CAPTIONING [Subaddress 51h–54h]

The ADV7330 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic 1 start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits and one odd parity bit. The data for these bytes is stored in the SD closed captioning registers (Address 53h–54h).

The ADV7330 also supports the extended closed captioning operation, which is active during even fields and is encoded on Scan Line 284. The data for this operation is stored in the SD closed captioning registers (Address 51h–52h).

All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7330. All pixel inputs are ignored during Lines 21 and 284 if closed captioning is enabled.

50 IRE

40 IRE

10.5s  0.25s

REFERENCE COLOR BURST

FREQUENCY = F

(9 CYCLES)

= 3.579545MHz

AMPLITUDE = 40 IRE

10.003s

27.382s 33.764s

12.91s

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284.

The ADV7330 uses a single buffering method. This means that the closed captioning buffer is only one byte deep; therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data must be loaded one line before (Line 20 or Line 283) it is output on Lines 21 and 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn will load the new data (two bytes) every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes on Line 21 or a TV will not recognize them. If there is a message like “Hello World” that has an odd number of characters, it is important to pad it out to even in order to get “end of caption” 2-byte control code to land in the same field.

TWO 7-BIT + PARITY ASCII CHARACTERS

(DATA)

S T

D0–D6 D0–D6

A R T

P A R

I T Y

P A R

I T Y

BYTE 1BYTE 0

Figure 58. Closed Captioning Waveform, NTSC

REV. B–56–

APPENDIX 4—TEST PATTERNS

The ADV7330 can generate SD and HD test patterns.

ADV7330

CH2 200mV M 10.0sA CH2 1.20V

30.6000s

Figure 59. NTSC Color Bars

CH2 100mV M 10.0s CH2 EVEN

1.82600ms

Figure 62. PAL Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)

CH2 200mV M 10.0sA CH2 1.21V

30.6000s

Figure 60. PA0L Color Bars

CH2 100mV M 10.0s CH2 EVEN

1.82380ms

Figure 61. NTSC Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)

CH2 200mV M 4.0s CH2 EVEN

Figure 63. 525p Hatch Pattern

CH2 200mV M 4.0s CH2 EVEN

Figure 64. 625p Hatch Pattern

1.82944ms

1.84208ms

REV. B

–57–

ADV7330

CH2 200mV M 4.0s CH2 EVEN

1.82872ms

Figure 65. 525p Field Pattern

CH2 100mV M 4.0s CH2 EVEN

1.82936ms

Figure 67. 525p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV)

CH2 200mV M 4.0s CH2 EVEN

1.84176ms

Figure 66. 625p Field Pattern

CH2 100mV M 4.0s CH2 EVEN

1.84176ms

Figure 68. 625p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV)

REV. B–58–

ADV7330

The following register settings are used to generate a SD NTSC CVBS output on DAC A:

Subaddress Setting

00h 10h 40h 10h 42h 40h 44h 40h 4Ah 08h

All other registers are set to normal/default.

For PAL CVBS output on DAC A, the same settings are used except that subaddress = 40h and register setting = 11h.

The following register settings are used to generate an SD NTSC black bar pattern output on DAC A:

Subaddress Setting

00h 10h 02h 04h 40h 10h 42h 40h 44h 40h 4Ah 08h

All other registers are set to normal/default.

For PAL black bar pattern output on DAC A, the same settings are used except that subaddress = 40h and register setting = 11h.

The following register settings are used to generate a 525p hatch pattern on DAC A:

Subaddress Setting

00h 10h 01h 10h 10h 40h 11h 05h 16h A0h 17h 80h 18h 80h

All other registers are set to normal/default.

For 625p hatch pattern on DAC A, the same register settings are used except that subaddress = 10h and register setting = 50h.

For a 525p black bar pattern output on DAC A, the same settings are used as above except that subaddress = 02h and register setting = 24h.

For 625p black bar pattern output on DAC A, the same settings are used as above except that subaddress = 02h and register setting = 24h; and subaddress = 10h and register setting = 50h.

REV. B

–59–

ADV7330

APPENDIX 5—SD TIMING MODES [Subaddress 4Ah]

Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7330 is controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. VSYNC_O/P, HSYNC_O/P, and BLANK_O/P (if not used) pins should be tied high during this mode. Blank output is available.

ANALOG

VIDEO

INPUT PIXELS

NTSC /PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

EAV CODE

FF0000X

4 CLOCK

END OF ACTIVE

VIDEO LINE

10801

FF00FFABABA

ANCILLARY DATA

268 CLOCK

280 CLOCK

(HANC)

Figure 69. SD Slave Mode 0

801

SAV CODE

10FF0

XYC

4 CLOCK

START OF ACTIVE

VIDEO LINE

1440 CLOCK

REV. B–60–

Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7330 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on HSYNC_O/P, the V bit is output on BLANK_O/P, and the F bit is output on VSYNC_O/P pin.

ADV7330

DISPLAY

522 523 524 525 1 2 3 4

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

EVEN FIELD

ODD FIELD

EVEN FIELD

VERTICAL BLANK

Figure 70. SD Master Mode 0 (NTSC)

DISPLAY

10 11 20 21 22

DISPLAY

283

284

285

DISPLAY

622 623 624 625 1 2 3 4

DISPLAY

309 310 311 312 314 315 316 317

EVEN FIELD

ODD FIELD

313

EVEN FIELD

Figure 71. SD Master Mode 0 (PAL)

VERTICAL BLANK

318

319 320

DISPLAY

22 23

DISPLAY

335 336

334

REV. B

–61–

ADV7330

ANALOG

VIDEO

Figure 72. SD Master Mode 0, Data Transitions

Mode 1—Slave Option (Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode, the ADV7330 accepts horizontal SYNC and odd/ even field signals. A transition of the field input when HSYNC_I/P is low indicates a new frame i.e., vertical retrace. The BLANK_I/P signal is optional. When the BLANK_I/P input is disabled, the ADV7330 automatically blanks all normally blank lines as per CCIR-624. HSYNC is applied to the HSYNC_I/P pin, BLANK to the BLANK_I/P pin, and Field to the VSYNC_I/P pin.

284

DISPLAY

285

DISPLAY

522 523 524 525

SYNC_I/P

LANK_I/P

FIELD

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

SYNC_I/P

LANK_I/P

FIELD

1234

EVEN FIELD

ODD FIELD EVEN FIELD

ODD FIELD

VERTICAL BLANK

678

VERTICAL BLANK

10 11

20 21 22

283

Figure 73. SD Slave Mode 1 (NTSC)

REV. B–62–

Mode 1—Master Option

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7330 can generate horizontal sync and odd/even field signals. A transition of the field output when HSYNC_O/P is low indicates a new frame i.e., vertical retrace. The blank signal is optional. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC is output on the HSYNC_O/P pin, BLANK on the BLANK_O/P pin, and Field on the VSYNC_O/P pin.

ADV7330

SYNC_O/P

LANK_O/P

FIELD

SYNC_O/P

LANK_O/P

FIELD

DISPLAY

622 623 624 625 1234

EVEN FIELD

DISPLAY

309 310 311 312 313 314 315 316

ODD FIELD

EVEN FIELD

VERTICAL BLANK

Figure 74. SD Slave Mode 1 (PAL)

317

318 319

320

DISPLAY

21 22 23

DISPLAY

334 335 336

SYNC_O/P

FIELD

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

LANK_O/P

PIXEL

REV. B

DATA

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 75. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave

–63–

Cb Y

Cr Y

ADV7330

Mode 2—Slave Option (Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode, the ADV7330 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC_I/P and VSYNC_I/P inputs indicates the start of an odd field. A VSYNC_I/P low transition when HSYNC_I/P is high indicates the start of an even field. The blank signal is optional. When the blank input is disabled, the ADV7330 automatically blanks all normally blank lines as per CCIR-624. HSYNC is input on the HSYNC_I/P pin, BLANK on the BLANK _I/P pin, and VSYNC on the VSYNC_I/P pin.

SYNC_I/P

LANK_I/P

VSYNC_I/P

SYNC_I/P

LANK_I/P

VSYNC_I/P

DISPLAY

522 523 524 525

DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

EVEN FIELD

ODD FIELD

VERTICAL BLANK

678

ODD FIELD

VERTICAL BLANK

EVEN FIELD

10 11

Figure 76. SD Slave Mode 2 (NTSC)

DISPLAY

VERTICAL BLANK

20 21 22

DISPLAY

283

284

DISPLAY

285

622 623 624 625 1234

SYNC_I/P

LANK_I/P

VSYNC_I/P

SYNC_I/P

LANK_I/P

VSYNC_I/P

DISPLAY

309 310 311 312 313 314 315 316

EVEN FIELD

ODD FIELD

VERTICAL BLANK

EVEN FIELD

317

318 319

320

21 22 23

DISPLAY

334 335 336

Figure 77. SD Slave Mode 2 (PAL)

REV. B–64–

Mode 2—Master Option

(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7330 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC_O/P and VSYNC_O/P outputs indicates the start of an odd field. A VSYNC_O/P low transition when HSYNC_O/P is high indicates the start of an even field. HSYNC is output on the HSYNC_O/P pin, BLANK on the BLANK_O/P pin, and VSYNC on the VSYNC_O/P pin.

SYNC_O/P

VSYNC_O/P

PAL = 12  CLOCK/2

LANK_O/P

NTSC = 16  CLOCK/2

ADV7330

PIXEL

DATA

SYNC_O/P

VSYNC_O/P

LANK_O/P

PIXEL

DATA

Cb Y Cr

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

Figure 78. SD Timing Mode 2—Even to Odd Field Transition Master/Slave

PAL = 864  CLOCK/2

PAL = 12  CLOCK/2

NTSC = 16  CLOCK/2

PAL = 132  CLOCK/2

NTSC = 122  CLOCK/2

NTSC = 858  CLOCK/2

Cb Y Cr Y Cb

Figure 79. SD Timing Mode 2—Odd to Even Field Transition Master/Slave

REV. B

–65–

ADV7330

Mode 3—Master/Slave Option (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV7330 accepts or generates horizontal sync and odd/even field signals. A transition of the field input when HSYNC_I/P is high indicates a new frame, i.e., vertical retrace. The BLANK_I/P signal is optional. When the BLANK_I/P input is disabled, the ADV7330 automatically blanks all normally blank lines as per CCIR-624. HSYNC is interfaced on HSYNC_I/P, BLANK on BLANK_I/P, VSYNC on VSYNC_I/P.

SYNC_I/P

LANK_I/P

FIELD

SYNC_I/P

LANK_I/P

FIELD

284

DISPLAY

285

DISPLAY

522 523 524 525

DISPLAY DISPLAY

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274

1234

ODD FIELDEVEN FIELD

ODD FIELD EVEN FIELD

VERTICAL BLANK

678

VERTICAL BLANK

10 11

20 21 22

283

Figure 80. SD Timing Mode 3 (NTSC)

REV. B–66–

ADV7330

DISPLAY

622 623 624 625 1234

SYNC_I/P

LANK_I/P

FIELD

DISPLAY

309 310 311 312 313 314 315 316

SYNC_I/P

LANK_I/P

FIELD

APPENDIX 6—HD TIMING

VERTICAL BLANK

ODD FIELDEVEN FIELD

VERTICAL BLANK

318 319

317

ODD FIELDEVEN FIELD

Figure 81. SD Timing Mode 3 (PAL)

320

DISPLAY

21 22 23

DISPLAY

334 335 336

DISPLAY

FIELD 1

1124 1125 1 2 5 6 7 8

VSYNC_I/P

SYNC_I/P

FIELD 2

VSYNC_I/P

SYNC_I/P

561 562 563 564 567 568 569 570

VERTICAL BLANKING INTERVAL

566565

20 22 560

DISPLAY

584

583 585 1123

Figure 82. 1080i Hsync and Vsync Input Timing

REV. B

–67–

ADV7330

APPENDIX 7—VIDEO OUTPUT LEVELS

HD YPrPb Output Levels

INPUT CODE

EIA-770.2, STANDARD FOR Y

OUTPUT VOLTAGE

INPUT CODE

EIA-770.3, STANDARD FOR Y

OUTPUT VOLTAGE

940

CTV V

EIA-770.2, STANDARD FOR Pr/Pb

960

512

700mV

300mV

OUTPUT VOLTAGE

700mV

CTV V

Figure 83. EIA 770.2 Standard Output Signals (525p/625p)

INPUT CODE

EIA-770.1, STANDARD FOR Y

940

OUTPUT VOLTAGE

782mV

940

700mVCTV V

300mV

EIA-770.3, STANDARD FOR Pr/Pb

960

512

600mV

CTV V

OUTPUT VOLTAGE

700mV

Figure 85. EIA 770.3 Standard Output Signals (1080i, 720p)

INPUT CODE

1023

Y–OUTPUT LEVELS FOR

FULL I/P SELECTION

OUTPUT VOLTAGE

EIA-770.1, STANDARD FOR Pr/Pb

960

512

CTV V

714mV

286mV

OUTPUT VOLTAGE

700mV

Figure 84. EIA 770.1 Standard Output Signals (525p/625p)

700mV

CTV V

300mV

INPUT CODE

1023

Pr/Pb–OUTPUT LEVELS FOR

FULL I/P SELECTION

CTV V

OUTPUT VOLTAGE

700mV

300mV

Figure 86. Output Levels for Full I/P Selection

REV. B–68–

RGB Output Levels

ADV7330

700mV

300mV

700mV

300mV

700mV

300mV

550mV

Figure 87. HD RGB Output Levels

700mV 550mV

700mV

300mV

700mV

300mV

700mV

300mV

550mV

Figure 89. SD RGB Output Levels—RGB Sync Disabled

700mV 550mV

300mV

0mV

700mV

300mV

0mV

700mV

300mV

0mV

550mV

Figure 88. HD RGB Output Levels—RGB Sync Enabled

300mV

0mV

700mV

300mV

0mV

700mV

300mV

0mV

550mV

Figure 90. SD RGB Output Levels—RGB Sync Enabled

REV. B

–69–

ADV7330

YPrPb Output Levels

WHITE

160mV

YELLOW

CYAN

220mV

GREEN

280mV

MAGENTA

RED

110mV

332mV

BLUE

BLACK

1000mV

WHITE

1260mV

YELLOW

CYAN

GREEN

2000mV

MAGENTA

RED

2150mV

900mV

BLUE

BLACK

60mV

Figure 91. U Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

220mV

160mV

60mV

Figure 92. U Levels—PAL

WHITE

YELLOW

CYAN

GREEN

2000mV

280mV

MAGENTA

RED

110mV

MAGENTA

RED

2150mV

332mV

BLUE

BLACK

140mV

Figure 94. U Levels—PAL

WHITE

YELLOW

CYAN

GREEN

MAGENTA

300mV

Figure 95. Y Levels—NTSC

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

1260mV

1000mV

140mV

Figure 93. U Levels—NTSC

900mV

300mV

Figure 96. Y Levels—PAL

REV. B–70–

VOLTS IRE:FLT

100

0.5

ADV7330

APL = 44.5% 525 LINE NTSC SLOW CLAMP TO 0.00V AT 6.77s

VOLTS

0.4

0.2

–0.2

–50

IRE:FLT

F1 L76



PRECISION MODE OFF

40 50

SYNCHRONOUS SYNC = A

FRAMES SELECTED 1 2

Figure 97. NTSC Color Bars 75%

REV. B

–50

–0.4

F1 L76

NOISE REDUCTION: 15.05dB APL NEEDS SYNC-SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V AT 6.72s

10 20

30 40 50 60

s

PRECISION MODE OFF

SYNCHRONOUS SYNC = B

Figure 98. NTSC Chroma

–71–

FRAMES SELECTED 1 2

ADV7330



0.6

0.4

0.2

IRE:FLT

F2 L238

10 20

VOLTS

–0.2

NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V AT 6.72

VOLTS

30 40 50 60

s

PRECISION MODE OFF

Figure 99. NTSC Luma

SYNCHRONOUS SYNC = SOURCE

FRAMES SELECTED 1 2

0.6

0.4

0.2

–0.2

L608

10020

NOISE REDUCTION: 0.00dB APL = 39.1% 625 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00V AT 6.72s

30 40 50 60

s

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1 2 3 4

Figure 100. PAL Color Bars 75%

REV. B–72–

0.5

–0.5

ADV7330

10 20 30 40 50 60

APL NEEDS SYNC = SOURCE 625 LINE PAL, NO FILTERING SLOW CLAMP TO 0.00V AT 6.72s

VOLTS

0.5

L575

10020

APL NEEDS SYNC = SOURCE 625 LINE PAL, NO FILTERING SLOW CLAMP TO 0.00V AT 6.72s

s NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

Figure 101. PAL Chroma

30 40 50 60 70

s NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

Figure 102. PAL Luma

FRAMES SELECTED 1

REV. B

–73–

ADV7330

APPENDIX 8—VIDEO STANDARDS

SMPTE274M

ANALOG WAVEFORM

EAV CODE

INPUT PIXELS

SAMPLE NUMBER

F F

2112 2116 2156 2199

*FVH = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1 SAV/EAV: LINE 21–560; 584–1123: V = 0

FOR A FIELD RATE OF 30Hz: 40 SAMPLES FOR A FIELD RATE OF 25Hz: 480 SAMPLES

000

4 CLOCK 4 CLOCK

Figure 103. EAV/SAV Input Data Timing Diagram—SMPTE 274M

DATUM

DIGITAL HORIZONTAL BLANKING

272T

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

44 188 192 2111

4T 1920T

SAV CODE

CbC

000

DIGITAL

ACTIVE LINE

SMPTE293M

ANALOG WAVEFORM

INPUT PIXELS

SAMPLE NUMBER

EAV CODE

F F

719 723 736 799 853 0

*FVH = FVH AND PARITY BITS SAV: LINE 43–525 = 200H SAV: LINE 1–42 = 2AC EAV: LINE 43–525 = 274H EAV: LINE 1–42 = 2D8

000

4 CLOCK 4 CLOCK

0HDATUM

DIGITAL HORIZONTAL BLANKING

ANCILLARY DATA

(OPTIONAL)

SAV CODE

000

Figure 104. EAV/SAV Input Data Timing Diagram—SMPTE 293M

DIGITAL

ACTIVE LINE

CbC

857 719

REV. B–74–

ADV7330

ACTIVE

VIDEO

522 523 524 525 12567891213141516424344

VERTICAL BLANK

Figure 105. SMPTE 293M (525p)

ACTIVE

VIDEO

622 623 624 625 1 2 5 6 7 8 9 12 1310 11 43 44 454

VERTICAL BLANK

Figure 106. ITU-R BT.1358 (625p)

DISPLAY

VERTICAL BLANKING INTERVAL

747 748 749 750 1 2 5 6 7 8 26 2725744 7454

Figure 107. SMPTE 296M (720p)

ACTIVE

VIDEO

ACTIVE

VIDEO

FIELD 1

FIELD 2

VERTICAL BLANKING INTERVAL

1124 1125 1 2 5 6 7 8

VERTICAL BLANKING INTERVAL

561 562 563 564 567 568 569 570

566565

Figure 108. SMPTE 274M (1080i)

DISPLAY

20 22 560

DISPLAY

584

583 585 1123

REV. B

–75–

ADV7330

OUTLINE DIMENSIONS

64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

1.45

1.40

1.35

0.15

0.05

10ⴗ

6ⴗ 2ⴗ

SEATING PLANE

ROTATED 90ⴗ CCW

VIEW A

0.08 MAX COPLANARITY

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09

7ⴗ

3.5ⴗ 0ⴗ

COMPLIANT TO JEDEC STANDARDS MS-026BCD

1.60 MAX

VIEW A

PIN 1

0.50 BSC

12.00 BSC SQ

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

4964

10.00

BSC SQ

Revision History

Location Page

7/04—Data sheet changed from REV. A to REV. B.

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Changes to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5/04—Data sheet changed from REV. 0 to REV. A.

Changes to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Change to Mode Register 0, SD Sync and HD Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Removed Footnote 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Change to HD Mode Register 5, Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Removed Footnote 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Change to Register 43h, Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Change to Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Change to Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Changes to Figures 105 and 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

C03750–0–7/04(B)

–76–

REV. B

Datasheet ADV7330 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

DETAILED FUNCTIONAL BLOCK DIAGRAM

DYNAMIC SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ORDERING GUIDE

THERMAL CHARACTERISTICS

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

TERMINOLOGY

MPU PORT DESCRIPTION

REGISTER ACCESS

Register Programming

Subaddress Register (SR7–SR0)

INPUT CONFIGURATION

OUTPUT CONFIGURATION

Reset Sequence

Vertical Blanking Interval

FILTER SECTION

HD Sinc Filter

COLOR CONTROLS AND RGB MATRIX

Programming the RGB Matrix

PROGRAMMABLE DAC GAIN CONTROL

HD Sharpness Filter Mode

HD Adaptive Filter Mode

HD Sharpness Filter and Adaptive Filter Application Examples

HD Sharpness Filter Application

ADAPTIVE FILTER CONTROL APPLICATION

BORDER AREA

CORING GAIN DATA

CORING GAIN BORDER

SAV/EAV STEP EDGE CONTROL

VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER

PC BOARD LAYOUT CONSIDERATIONS

Supply Decoupling

Digital Signal Interconnect

Analog Signal Interconnect

720p System

1080i System

CGMS CRC Functionality

Function of CGMS Bits

APPENDIX 4—TEST PATTERNS

Mode 1—Master Option

Mode 2—Master Option

APPENDIX 6—HD TIMING

APPENDIX 7—VIDEO OUTPUT LEVELS

HD YPrPb Output Levels

RGB Output Levels

YPrPb Output Levels

APPENDIX 8—VIDEO STANDARDS

OUTLINE DIMENSIONS

Revision History